diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/fs/10.linux-boot/ref | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
34 files changed, 17327 insertions, 17313 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 0d25f966b..edbc5da0f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1001,6 +1001,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1026,25 +1027,28 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1073,6 +1077,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 560862c38..dcd646636 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:25 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:18:50 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107825000 -Exiting @ tick 1901719660500 because m5_exit instruction encountered +info: Launching CPU 1 @ 110215000 +Exiting @ tick 1900727015500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7d7f83f12..af3e1799f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897808 # Number of seconds simulated -sim_ticks 1897807508000 # Number of ticks simulated -final_tick 1897807508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900727 # Number of seconds simulated +sim_ticks 1900727015500 # Number of ticks simulated +final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94343 # Simulator instruction rate (inst/s) -host_op_rate 94343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3156287920 # Simulator tick rate (ticks/s) -host_mem_usage 338708 # Number of bytes of host memory used -host_seconds 601.28 # Real time elapsed on the host -sim_insts 56726638 # Number of instructions simulated -sim_ops 56726638 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 852800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24659584 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 537024 # Number of bytes read from this memory -system.physmem.bytes_read::total 28824960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7794816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7794816 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385306 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8391 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121794 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121794 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12993722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1397217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15188558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449361 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 514649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4107274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4107274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4107274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12993722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19295833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450390 # Total number of read requests seen -system.physmem.writeReqs 121794 # Total number of write requests seen -system.physmem.cpureqs 577229 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28824960 # Total number of bytes read from memory -system.physmem.bytesWritten 7794816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28824960 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7794816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5032 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28018 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28103 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27949 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7700 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7581 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7677 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7592 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7617 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7323 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7475 # Track writes on a per bank basis +host_inst_rate 47037 # Simulator instruction rate (inst/s) +host_op_rate 47037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1570523818 # Simulator tick rate (ticks/s) +host_mem_usage 354648 # Number of bytes of host memory used +host_seconds 1210.25 # Real time elapsed on the host +sim_insts 56926994 # Number of instructions simulated +sim_ops 56926994 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory +system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory +system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449493 # Total number of read requests seen +system.physmem.writeReqs 120791 # Total number of write requests seen +system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28767552 # Total number of bytes read from memory +system.physmem.bytesWritten 7730624 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7578 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7608 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7520 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7649 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7589 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7444 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7350 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry -system.physmem.totGap 1897802972000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 1900722456000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450390 # Categorize read packet sizes +system.physmem.readPktSize::6 449493 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121794 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 319842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120791 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.totQLat 7744912500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15549496250 # Sum of mem lat for all requests -system.physmem.totBusLat 2251660000 # Total cycles spent in databus access -system.physmem.totBankLat 5552923750 # Total cycles spent in bank access -system.physmem.avgQLat 17198.23 # Average queueing delay per request -system.physmem.avgBankLat 12330.73 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.totQLat 7695436000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15487088500 # Sum of mem lat for all requests +system.physmem.totBusLat 2247130000 # Total cycles spent in databus access +system.physmem.totBankLat 5544522500 # Total cycles spent in bank access +system.physmem.avgQLat 17122.81 # Average queueing delay per request +system.physmem.avgBankLat 12336.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34528.96 # Average memory access latency -system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34459.71 # Average memory access latency +system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.90 # Average write queue length over time -system.physmem.readRowHits 422298 # Number of row buffer hits during reads -system.physmem.writeRowHits 93666 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.91 # Row buffer hit rate for writes -system.physmem.avgGap 3316770.43 # Average gap between requests -system.l2c.replacements 343496 # number of replacements -system.l2c.tagsinuse 65280.770120 # Cycle average of tags in use -system.l2c.total_refs 2576734 # Total number of references to valid blocks. -system.l2c.sampled_refs 408507 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.307686 # Average number of references to valid blocks. +system.physmem.avgWrQLen 9.46 # Average write queue length over time +system.physmem.readRowHits 421587 # Number of row buffer hits during reads +system.physmem.writeRowHits 92850 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.87 # Row buffer hit rate for writes +system.physmem.avgGap 3332940.18 # Average gap between requests +system.l2c.replacements 342617 # number of replacements +system.l2c.tagsinuse 65285.001346 # Cycle average of tags in use +system.l2c.total_refs 2569094 # Total number of references to valid blocks. +system.l2c.sampled_refs 407591 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.303118 # Average number of references to valid blocks. system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53812.537758 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5294.598219 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5895.682544 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 204.689512 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 73.262087 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.821114 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.080789 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.089961 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003123 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001118 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996106 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 850039 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 731128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 225279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 71901 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1878347 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820480 # number of Writeback hits -system.l2c.Writeback_hits::total 820480 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 168 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 442 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 153309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26446 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179755 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 850039 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 884437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 225279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98347 # number of demand (read+write) hits -system.l2c.demand_hits::total 2058102 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 850039 # number of overall hits -system.l2c.overall_hits::cpu0.data 884437 # number of overall hits -system.l2c.overall_hits::cpu1.inst 225279 # number of overall hits -system.l2c.overall_hits::cpu1.data 98347 # number of overall hits -system.l2c.overall_hits::total 2058102 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13328 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1952 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 891 # number of ReadReq misses +system.l2c.occ_blocks::writebacks 53776.663341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5305.450361 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5913.032495 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 209.604016 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 80.251133 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.820567 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.080955 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.090226 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003198 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001225 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996170 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 815796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 714354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 262043 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83568 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1875761 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 814734 # number of Writeback hits +system.l2c.Writeback_hits::total 814734 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 351 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 525 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 146833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 31831 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178664 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 815796 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 861187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 262043 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 115399 # number of demand (read+write) hits +system.l2c.demand_hits::total 2054425 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 815796 # number of overall hits +system.l2c.overall_hits::cpu0.data 861187 # number of overall hits +system.l2c.overall_hits::cpu1.inst 262043 # number of overall hits +system.l2c.overall_hits::cpu1.data 115399 # number of overall hits +system.l2c.overall_hits::total 2054425 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13356 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272983 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1945 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 897 # number of ReadReq misses system.l2c.ReadReq_misses::total 289181 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2698 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1139 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3837 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 440 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 900 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 112836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7617 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120453 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13328 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 385846 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1952 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8508 # number of demand (read+write) misses -system.l2c.demand_misses::total 409634 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13328 # number of overall misses -system.l2c.overall_misses::cpu0.data 385846 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1952 # number of overall misses -system.l2c.overall_misses::cpu1.data 8508 # number of overall misses -system.l2c.overall_misses::total 409634 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 910367500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11910960000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 149515000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 66485999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 13037328499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1032000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4998458 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6030458 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 158500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1306498 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7467468497 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 736712000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8204180497 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 910367500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19378428497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 149515000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 803197999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21241508996 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 910367500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19378428497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 149515000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 803197999 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21241508996 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 863367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1004138 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 227231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 72792 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2167528 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820480 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820480 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2866 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4279 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 484 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 266145 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34063 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300208 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 863367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1270283 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 227231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 106855 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2467736 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 863367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1270283 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 227231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 106855 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2467736 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.271885 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008590 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.012240 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133415 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941382 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806086 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.896705 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.909091 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.950413 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.929752 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.423964 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.223615 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.401232 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.303748 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008590 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.079622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165996 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.303748 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008590 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.079622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165996 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68304.884454 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 43628.292004 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76595.799180 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74619.527497 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 45083.627552 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.505560 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4388.461809 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1571.659630 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2609.086364 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 344.565217 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1451.664444 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66179.840627 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96719.443350 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68111.051589 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68304.884454 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50223.219878 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76595.799180 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 94405.030442 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51854.848465 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68304.884454 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50223.219878 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76595.799180 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 94405.030442 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51854.848465 # average overall miss latency +system.l2c.UpgradeReq_misses::cpu0.data 2769 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1340 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4109 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 587 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1147 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 111939 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7676 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 119615 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13356 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 384922 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1945 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8573 # number of demand (read+write) misses +system.l2c.demand_misses::total 408796 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13356 # number of overall misses +system.l2c.overall_misses::cpu0.data 384922 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses +system.l2c.overall_misses::cpu1.data 8573 # number of overall misses +system.l2c.overall_misses::total 408796 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 905864000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11898970000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 151230500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 68201999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 13024266499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 960000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 6372986 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7332986 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 888499 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1024499 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7329049500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 758770499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8087819999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 905864000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19228019500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 151230500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 826972498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21112086498 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 905864000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19228019500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 151230500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 826972498 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21112086498 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 829152 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 987337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 263988 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 84465 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2164942 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 814734 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 814734 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2943 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1691 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4634 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 608 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 615 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1223 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 258772 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 39507 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298279 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 829152 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1246109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 263988 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 123972 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2463221 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 829152 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1246109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 263988 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 123972 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2463221 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016108 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.276484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.010620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133574 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940877 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792431 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.886707 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921053 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.954472 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.937858 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.432578 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.194295 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.401017 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016108 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.308899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.069153 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165960 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016108 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.308899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.069153 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165960 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67824.498353 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43588.685010 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77753.470437 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76033.443701 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 45038.458609 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 346.695558 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4755.959701 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1784.615722 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1586.605357 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 231.686542 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 893.198779 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65473.601694 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 98849.726290 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 67615.432839 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51644.552535 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51644.552535 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,8 +364,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80274 # number of writebacks -system.l2c.writebacks::total 80274 # number of writebacks +system.l2c.writebacks::writebacks 79271 # number of writebacks +system.l2c.writebacks::total 79271 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits @@ -378,111 +378,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13327 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273010 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1936 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 890 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 13355 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272983 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 896 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2698 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1139 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3837 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 440 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 900 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 112836 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7617 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120453 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13327 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 385846 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1936 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8507 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409616 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13327 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 385846 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1936 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8507 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409616 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 744135298 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8568292303 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124663136 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55431194 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9492521931 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27188160 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11417094 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 38605254 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4415934 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604459 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 9020393 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6092451578 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 643571973 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6736023551 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 744135298 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14660743881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 124663136 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 699003167 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16228545482 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 744135298 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14660743881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 124663136 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 699003167 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16228545482 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1360923000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28763500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389686500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2006926500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 610979500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2617906000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3367849500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 639743000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4007592500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012227 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133407 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941382 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806086 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.896705 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909091 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.950413 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929752 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423964 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.223615 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.401232 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165989 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165989 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31384.536475 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62282.240449 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 32827.581437 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.153447 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.787533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.311962 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10036.213636 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.693478 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.658889 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53993.863466 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84491.528555 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55922.422447 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2769 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1340 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4109 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 587 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1147 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 111939 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7676 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 119615 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13355 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 384922 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8572 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408778 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13355 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 384922 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8572 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408778 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 739303821 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8556722771 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 126469885 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 57202686 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9479699163 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27888734 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13415324 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 41304058 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5612547 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5879586 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 11492133 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5964907547 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 664977742 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6629885289 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 739303821 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14521630318 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 126469885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 722180428 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16109584452 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 739303821 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14521630318 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 126469885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 722180428 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16109584452 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1362723500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28760000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391483500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2034614500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637502000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2672116500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3397338000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 666262000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4063600000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276484 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133566 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940877 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792431 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.886707 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921053 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954472 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.937858 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.432578 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.194295 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.401017 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165953 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165953 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31345.258756 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63842.283482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 32783.237008 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.771036 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.435821 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.094914 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.405357 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10019.296425 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53287.125551 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86630.763679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55426.871956 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -493,39 +493,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.485600 # Cycle average of tags in use +system.iocache.replacements 41699 # number of replacements +system.iocache.tagsinuse 0.509415 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705456155000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.485600 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.030350 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.030350 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.warmup_cycle 1705456216000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.509415 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.031838 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.031838 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21380998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21380998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10586787421 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10586787421 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10608168419 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10608168419 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10608168419 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10608168419 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21612998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21612998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10624659943 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10624659943 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10646272941 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10646272941 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10646272941 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10646272941 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -534,40 +534,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.063848 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 254784.063848 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254215.735316 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254215.735316 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254215.735316 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254215.735316 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 281558 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120743.005587 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120743.005587 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255695.512683 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255695.512683 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255116.650476 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255116.650476 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284705 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26875 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27170 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.476577 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.478653 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424789680 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8424789680 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8436965929 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8436965929 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8436965929 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8436965929 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12304249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12304249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8462672446 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8462672446 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8474976695 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8474976695 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8474976695 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8474976695 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.928379 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.928379 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.713964 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202184.713964 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12324830 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10383801 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330699 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7879276 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5243296 # Number of BTB hits +system.cpu0.branchPred.lookups 12043910 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.545403 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784421 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32635 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8754095 # DTB read hits -system.cpu0.dtb.read_misses 29935 # DTB read misses -system.cpu0.dtb.read_acv 546 # DTB read access violations -system.cpu0.dtb.read_accesses 624217 # DTB read accesses -system.cpu0.dtb.write_hits 5744304 # DTB write hits -system.cpu0.dtb.write_misses 8066 # DTB write misses -system.cpu0.dtb.write_acv 350 # DTB write access violations -system.cpu0.dtb.write_accesses 207709 # DTB write accesses -system.cpu0.dtb.data_hits 14498399 # DTB hits -system.cpu0.dtb.data_misses 38001 # DTB misses -system.cpu0.dtb.data_acv 896 # DTB access violations -system.cpu0.dtb.data_accesses 831926 # DTB accesses -system.cpu0.itb.fetch_hits 984231 # ITB hits -system.cpu0.itb.fetch_misses 30400 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1014631 # ITB accesses +system.cpu0.dtb.read_hits 8552844 # DTB read hits +system.cpu0.dtb.read_misses 30306 # DTB read misses +system.cpu0.dtb.read_acv 545 # DTB read access violations +system.cpu0.dtb.read_accesses 625084 # DTB read accesses +system.cpu0.dtb.write_hits 5600708 # DTB write hits +system.cpu0.dtb.write_misses 7703 # DTB write misses +system.cpu0.dtb.write_acv 337 # DTB write access violations +system.cpu0.dtb.write_accesses 207517 # DTB write accesses +system.cpu0.dtb.data_hits 14153552 # DTB hits +system.cpu0.dtb.data_misses 38009 # DTB misses +system.cpu0.dtb.data_acv 882 # DTB access violations +system.cpu0.dtb.data_accesses 832601 # DTB accesses +system.cpu0.itb.fetch_hits 972187 # ITB hits +system.cpu0.itb.fetch_misses 27447 # ITB misses +system.cpu0.itb.fetch_acv 929 # ITB acv +system.cpu0.itb.fetch_accesses 999634 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101829868 # number of cpu cycles simulated +system.cpu0.numCycles 100158206 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24831231 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63164825 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12324830 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6027717 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11886034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1687418 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36616651 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 197530 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292271 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 247 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7635312 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223745 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74945500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.842810 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.180311 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63059466 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 761662 1.02% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1556791 2.08% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 699013 0.93% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2562383 3.42% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 515928 0.69% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568129 0.76% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 822428 1.10% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4399700 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74945500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121034 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620298 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26048767 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36112585 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10811010 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 918999 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1054138 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507624 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35116 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62016567 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105227 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1054138 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27056479 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14636567 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17989986 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10129953 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4078375 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58716570 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6669 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 641571 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1425002 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39326634 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71486416 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71104766 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 381650 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34557314 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4769312 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1434958 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 208601 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11111126 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9162338 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6008284 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124943 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 741369 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52108127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1785217 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50965376 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88359 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5842472 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2979590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1208696 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74945500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680033 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329236 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52296103 69.78% 69.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10307056 13.75% 83.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4639666 6.19% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3056082 4.08% 93.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2432821 3.25% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1212271 1.62% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 643524 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 306857 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51120 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74945500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 83315 12.44% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 310574 46.36% 58.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 276009 41.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35160159 68.99% 69.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56163 0.11% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9109271 17.87% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5812211 11.40% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 806271 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50965376 # Type of FU issued -system.cpu0.iq.rate 0.500495 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 669898 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177086282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59482873 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49950097 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 548226 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 265331 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258806 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51344519 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 286981 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 543841 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued +system.cpu0.iq.rate 0.498985 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1097645 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12633 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 446832 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18414 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 123451 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1054138 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10442164 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794127 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57094083 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 608812 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9162338 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6008284 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1572405 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581948 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5528 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12633 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164589 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 346313 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510902 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50577895 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8807105 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387480 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3200739 # number of nop insts executed -system.cpu0.iew.exec_refs 14572965 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8058105 # Number of branches executed -system.cpu0.iew.exec_stores 5765860 # Number of stores executed -system.cpu0.iew.exec_rate 0.496690 # Inst execution rate -system.cpu0.iew.wb_sent 50296670 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50208903 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25061095 # num instructions producing a value -system.cpu0.iew.wb_consumers 33769433 # num instructions consuming a value +system.cpu0.iew.exec_nop 3133489 # number of nop insts executed +system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7905275 # Number of branches executed +system.cpu0.iew.exec_stores 5621640 # Number of stores executed +system.cpu0.iew.exec_rate 0.495223 # Inst execution rate +system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24627791 # num instructions producing a value +system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493067 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742124 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6306622 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 576521 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477545 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73891362 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686006 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.603918 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54863146 74.25% 74.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7931478 10.73% 84.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4331360 5.86% 90.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2351860 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1314304 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 548181 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466916 0.63% 97.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 432440 0.59% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1651677 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73891362 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50689891 # Number of instructions committed -system.cpu0.commit.committedOps 50689891 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49720528 # Number of instructions committed +system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13626145 # Number of memory references committed -system.cpu0.commit.loads 8064693 # Number of loads committed -system.cpu0.commit.membars 196335 # Number of memory barriers committed -system.cpu0.commit.branches 7657959 # Number of branches committed -system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46940801 # Number of committed integer instructions. -system.cpu0.commit.function_calls 646411 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1651677 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13302179 # Number of memory references committed +system.cpu0.commit.loads 7888682 # Number of loads committed +system.cpu0.commit.membars 189617 # Number of memory barriers committed +system.cpu0.commit.branches 7516247 # Number of branches committed +system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions. +system.cpu0.commit.function_calls 629253 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129041756 # The number of ROB reads -system.cpu0.rob.rob_writes 115048006 # The number of ROB writes -system.cpu0.timesIdled 1051806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26884368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693778600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47771172 # Number of Instructions Simulated -system.cpu0.committedOps 47771172 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47771172 # Number of Instructions Simulated -system.cpu0.cpi 2.131618 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.131618 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469127 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469127 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66565111 # number of integer regfile reads -system.cpu0.int_regfile_writes 36349916 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127030 # number of floating regfile reads -system.cpu0.fp_regfile_writes 128672 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1690077 # number of misc regfile reads -system.cpu0.misc_regfile_writes 805917 # number of misc regfile writes +system.cpu0.rob.rob_reads 126376352 # The number of ROB reads +system.cpu0.rob.rob_writes 112693596 # The number of ROB writes +system.cpu0.timesIdled 1033507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26786615 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701289214 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46865102 # Number of Instructions Simulated +system.cpu0.committedOps 46865102 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 46865102 # Number of Instructions Simulated +system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.467911 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.467911 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65365755 # number of integer regfile reads +system.cpu0.int_regfile_writes 35683177 # number of integer regfile writes +system.cpu0.fp_regfile_reads 120752 # number of floating regfile reads +system.cpu0.fp_regfile_writes 122064 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1632145 # number of misc regfile reads +system.cpu0.misc_regfile_writes 781535 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 862820 # number of replacements -system.cpu0.icache.tagsinuse 510.307143 # Cycle average of tags in use -system.cpu0.icache.total_refs 6727960 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 863332 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.793016 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.307143 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996694 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996694 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6727960 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6727960 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6727960 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6727960 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6727960 # number of overall hits -system.cpu0.icache.overall_hits::total 6727960 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 907351 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 907351 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 907351 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 907351 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 907351 # number of overall misses -system.cpu0.icache.overall_misses::total 907351 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12784635489 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12784635489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12784635489 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12784635489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12784635489 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12784635489 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7635311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7635311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7635311 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7635311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7635311 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7635311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118836 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118836 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118836 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118836 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118836 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118836 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14090.066015 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14090.066015 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14090.066015 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14090.066015 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5023 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 178 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.219101 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 828572 # number of replacements +system.cpu0.icache.tagsinuse 510.309366 # Cycle average of tags in use +system.cpu0.icache.total_refs 6631345 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 829084 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.998399 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.309366 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996698 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6631345 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6631345 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6631345 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6631345 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6631345 # number of overall hits +system.cpu0.icache.overall_hits::total 6631345 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 870628 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 870628 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 870628 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 870628 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 870628 # number of overall misses +system.cpu0.icache.overall_misses::total 870628 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12335909994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12335909994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12335909994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12335909994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12335909994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12335909994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7501973 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7501973 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7501973 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7501973 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7501973 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7501973 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116053 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116053 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116053 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116053 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116053 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116053 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14168.979167 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14168.979167 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14168.979167 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14168.979167 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2773 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.124138 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43874 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43874 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43874 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43874 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43874 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43874 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863477 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 863477 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 863477 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 863477 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 863477 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 863477 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10532261990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10532261990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10532261990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10532261990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10532261990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10532261990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113090 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113090 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12197.501485 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41361 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 41361 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41361 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 41361 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41361 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41361 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 829267 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 829267 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 829267 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 829267 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 829267 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 829267 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10145672495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10145672495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10145672495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10145672495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10145672495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10145672495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110540 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.110540 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.110540 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.506492 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1272509 # number of replacements -system.cpu0.dcache.tagsinuse 505.757504 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10329025 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1273021 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.113790 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.757504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987808 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987808 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6350853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6350853 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3621976 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3621976 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184435 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184435 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9972829 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9972829 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9972829 # number of overall hits -system.cpu0.dcache.overall_hits::total 9972829 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1585015 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1585015 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1737486 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1737486 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3322501 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3322501 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3322501 # number of overall misses -system.cpu0.dcache.overall_misses::total 3322501 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34267378500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34267378500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66512674680 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 66512674680 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293615500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293615500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 21928500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 100780053180 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 100780053180 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 100780053180 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 100780053180 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7935868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359462 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5359462 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13295330 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13295330 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13295330 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13295330 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199728 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199728 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324190 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324190 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113014 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113014 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015958 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015958 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249900 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249900 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21619.592559 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21619.592559 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38280.984526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38280.984526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14380.228230 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14380.228230 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7331.494483 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7331.494483 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30332.587764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30332.587764 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2151725 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48206 # number of cycles access was blocked +system.cpu0.dcache.replacements 1248443 # number of replacements +system.cpu0.dcache.tagsinuse 505.648747 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10075338 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1248955 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.067014 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.648747 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987595 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6210455 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6210455 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3519332 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3519332 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 154524 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177828 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 177828 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9729787 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9729787 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9729787 # number of overall hits +system.cpu0.dcache.overall_hits::total 9729787 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1542913 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1542913 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1697969 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1697969 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3731 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3731 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3240882 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3240882 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3240882 # number of overall misses +system.cpu0.dcache.overall_misses::total 3240882 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33525948000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 33525948000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65021398230 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 65021398230 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277810500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 277810500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27308500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 27308500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98547346230 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98547346230 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98547346230 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98547346230 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7753368 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7753368 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217301 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5217301 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 174253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181559 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 181559 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12970669 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12970669 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12970669 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12970669 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.198999 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325450 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.325450 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113220 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113220 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020550 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249862 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249862 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249862 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249862 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21728.994441 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21728.994441 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.630938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.630938 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14081.326981 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14081.326981 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7319.351380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7319.351380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30407.569986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30407.569986 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2105320 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 47301 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.636041 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.508996 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 748436 # number of writebacks -system.cpu0.dcache.writebacks::total 748436 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585810 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 585810 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465270 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465270 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4533 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4533 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2051080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2051080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2051080 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2051080 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999205 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 999205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272216 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272216 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15885 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15885 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1271421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271421 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1271421 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21496696000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21496696000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9690926222 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9690926222 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183269000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183269000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31187622222 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31187622222 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31187622222 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31187622222 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1452303000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1452303000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128092999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128092999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3580395999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3580395999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125910 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125910 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050792 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015958 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015958 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095629 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095629 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21513.799471 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21513.799471 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35600.134533 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35600.134533 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.236387 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.236387 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5331.494483 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5331.494483 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 729881 # number of writebacks +system.cpu0.dcache.writebacks::total 729881 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558235 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 558235 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432207 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432207 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4308 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4308 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990442 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1990442 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990442 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1990442 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 984678 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265762 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265762 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15421 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250440 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1250440 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250440 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1250440 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21285796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21285796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9471560262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9471560262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30757356762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30757356762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30757356762 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30757356762 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454223000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454223000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2157391999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2647984 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2186587 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 77884 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1531761 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883024 # Number of BTB hits +system.cpu1.branchPred.lookups 2951549 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.647636 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 183996 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8305 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1962214 # DTB read hits -system.cpu1.dtb.read_misses 10693 # DTB read misses +system.cpu1.dtb.read_hits 2175312 # DTB read hits +system.cpu1.dtb.read_misses 10933 # DTB read misses system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 324562 # DTB read accesses -system.cpu1.dtb.write_hits 1265832 # DTB write hits -system.cpu1.dtb.write_misses 2093 # DTB write misses -system.cpu1.dtb.write_acv 66 # DTB write access violations -system.cpu1.dtb.write_accesses 133005 # DTB write accesses -system.cpu1.dtb.data_hits 3228046 # DTB hits -system.cpu1.dtb.data_misses 12786 # DTB misses -system.cpu1.dtb.data_acv 91 # DTB access violations -system.cpu1.dtb.data_accesses 457567 # DTB accesses -system.cpu1.itb.fetch_hits 437198 # ITB hits -system.cpu1.itb.fetch_misses 6975 # ITB misses -system.cpu1.itb.fetch_acv 228 # ITB acv -system.cpu1.itb.fetch_accesses 444173 # ITB accesses +system.cpu1.dtb.read_accesses 324345 # DTB read accesses +system.cpu1.dtb.write_hits 1433020 # DTB write hits +system.cpu1.dtb.write_misses 2283 # DTB write misses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_accesses 133154 # DTB write accesses +system.cpu1.dtb.data_hits 3608332 # DTB hits +system.cpu1.dtb.data_misses 13216 # DTB misses +system.cpu1.dtb.data_acv 89 # DTB access violations +system.cpu1.dtb.data_accesses 457499 # DTB accesses +system.cpu1.itb.fetch_hits 457840 # ITB hits +system.cpu1.itb.fetch_misses 7553 # ITB misses +system.cpu1.itb.fetch_acv 250 # ITB acv +system.cpu1.itb.fetch_accesses 465393 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,508 +1219,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16140506 # number of cpu cycles simulated +system.cpu1.numCycles 18134862 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6118318 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12482084 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2647984 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1067020 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2239129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 408271 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6344159 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65784 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 57491 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1512128 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52849 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15112669 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.825935 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199937 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12873540 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143819 0.95% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 241770 1.60% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 180451 1.19% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 309857 2.05% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119919 0.79% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 135082 0.89% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 201991 1.34% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 906240 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15112669 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164058 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.773339 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6050197 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6601549 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2093593 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 113312 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 254017 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116024 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7481 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12238533 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22436 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 254017 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6259861 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 497059 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5456265 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1994881 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 650584 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11345893 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56627 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 159750 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7468114 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13547421 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13404114 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 143307 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6384399 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1083715 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 455985 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 44016 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2004753 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2075172 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1340696 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190596 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 106471 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9962736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502412 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9694977 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29943 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1444595 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 720781 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 360981 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15112669 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.641513 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316207 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10849099 71.79% 71.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1954888 12.94% 84.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 839816 5.56% 90.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 558366 3.69% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 473326 3.13% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 218082 1.44% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 140204 0.93% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 70683 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8205 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15112669 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3691 1.86% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 106885 53.95% 55.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87531 44.18% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6046898 62.37% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16423 0.17% 62.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2053041 21.18% 83.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1289229 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 273248 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9694977 # Type of FU issued -system.cpu1.iq.rate 0.600661 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 198107 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020434 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34523477 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11810363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9424990 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 207196 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101110 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98065 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9781516 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 108042 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94596 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued +system.cpu1.iq.rate 0.597126 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 286791 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 870 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1822 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126158 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10101 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 254017 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327186 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41525 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10980256 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 148232 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2075172 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1340696 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 454941 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 34335 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2140 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1822 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35734 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100242 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135976 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9604840 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1980291 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 90137 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 515108 # number of nop insts executed -system.cpu1.iew.exec_refs 3254225 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1434575 # Number of branches executed -system.cpu1.iew.exec_stores 1273934 # Number of stores executed -system.cpu1.iew.exec_rate 0.595077 # Inst execution rate -system.cpu1.iew.wb_sent 9552134 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9523055 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4457844 # num instructions producing a value -system.cpu1.iew.wb_consumers 6254214 # num instructions consuming a value +system.cpu1.iew.exec_nop 600729 # number of nop insts executed +system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1609931 # Number of branches executed +system.cpu1.iew.exec_stores 1442207 # Number of stores executed +system.cpu1.iew.exec_rate 0.591458 # Inst execution rate +system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4954529 # num instructions producing a value +system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.590010 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712774 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1499365 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 141431 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 128632 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14858652 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633306 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577285 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11337498 76.30% 76.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1644581 11.07% 87.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 614314 4.13% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 371520 2.50% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264064 1.78% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 106187 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110282 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 108223 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301983 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14858652 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9410077 # Number of instructions committed -system.cpu1.commit.committedOps 9410077 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16732673 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10592581 # Number of instructions committed +system.cpu1.commit.committedOps 10592581 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3002919 # Number of memory references committed -system.cpu1.commit.loads 1788381 # Number of loads committed -system.cpu1.commit.membars 45067 # Number of memory barriers committed -system.cpu1.commit.branches 1346773 # Number of branches committed -system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8720568 # Number of committed integer instructions. -system.cpu1.commit.function_calls 150616 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 301983 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3379323 # Number of memory references committed +system.cpu1.commit.loads 1996302 # Number of loads committed +system.cpu1.commit.membars 53397 # Number of memory barriers committed +system.cpu1.commit.branches 1516852 # Number of branches committed +system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9798554 # Number of committed integer instructions. +system.cpu1.commit.function_calls 169964 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 341197 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25374737 # The number of ROB reads -system.cpu1.rob.rob_writes 22071443 # The number of ROB writes -system.cpu1.timesIdled 132837 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1027837 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3778857265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8955466 # Number of Instructions Simulated -system.cpu1.committedOps 8955466 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8955466 # Number of Instructions Simulated -system.cpu1.cpi 1.802308 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.802308 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554844 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554844 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12383422 # number of integer regfile reads -system.cpu1.int_regfile_writes 6777735 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53544 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53234 # number of floating regfile writes -system.cpu1.misc_regfile_reads 526951 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221547 # number of misc regfile writes -system.cpu1.icache.replacements 226688 # number of replacements -system.cpu1.icache.tagsinuse 470.806939 # Cycle average of tags in use -system.cpu1.icache.total_refs 1276285 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 227200 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.617452 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.806939 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919545 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919545 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1276285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1276285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1276285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1276285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1276285 # number of overall hits -system.cpu1.icache.overall_hits::total 1276285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 235843 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 235843 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 235843 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 235843 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 235843 # number of overall misses -system.cpu1.icache.overall_misses::total 235843 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3268518999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3268518999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3268518999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3268518999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3268518999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3268518999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1512128 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1512128 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1512128 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1512128 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1512128 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1512128 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155968 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155968 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155968 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155968 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155968 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155968 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13858.876452 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13858.876452 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13858.876452 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13858.876452 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked +system.cpu1.rob.rob_reads 28468767 # The number of ROB reads +system.cpu1.rob.rob_writes 24605693 # The number of ROB writes +system.cpu1.timesIdled 153691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1134548 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782736336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 10061892 # Number of Instructions Simulated +system.cpu1.committedOps 10061892 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 10061892 # Number of Instructions Simulated +system.cpu1.cpi 1.802331 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802331 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554837 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554837 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13798288 # number of integer regfile reads +system.cpu1.int_regfile_writes 7546279 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63929 # number of floating regfile reads +system.cpu1.fp_regfile_writes 63981 # number of floating regfile writes +system.cpu1.misc_regfile_reads 608468 # number of misc regfile reads +system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes +system.cpu1.icache.replacements 263438 # number of replacements +system.cpu1.icache.tagsinuse 470.047000 # Cycle average of tags in use +system.cpu1.icache.total_refs 1391700 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 263950 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.272590 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1875178456000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.047000 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1391700 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1391700 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1391700 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1391700 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1391700 # number of overall hits +system.cpu1.icache.overall_hits::total 1391700 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 273170 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 273170 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 273170 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 273170 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 273170 # number of overall misses +system.cpu1.icache.overall_misses::total 273170 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3762343999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3762343999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3762343999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3762343999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3762343999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3762343999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1664870 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1664870 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1664870 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1664870 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1664870 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1664870 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164079 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.164079 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164079 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.164079 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164079 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.164079 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13772.903317 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13772.903317 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13772.903317 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13772.903317 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.153846 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 42.857143 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8582 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8582 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8582 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8582 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8582 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8582 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227261 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 227261 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 227261 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 227261 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 227261 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 227261 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711595499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711595499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711595499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2711595499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711595499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2711595499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150292 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150292 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.150292 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11931.635868 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9145 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9145 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9145 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9145 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9145 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9145 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 264025 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 264025 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 264025 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 264025 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 264025 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 264025 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3130972999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3130972999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3130972999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3130972999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3130972999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3130972999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158586 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.158586 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.158586 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.623233 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108752 # number of replacements -system.cpu1.dcache.tagsinuse 491.542258 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2641634 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109154 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.200982 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.542258 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.960043 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.960043 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1618348 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1618348 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 952576 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 952576 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33975 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33975 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2570924 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2570924 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2570924 # number of overall hits -system.cpu1.dcache.overall_hits::total 2570924 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 209179 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 209179 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 220095 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 220095 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5405 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5405 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3147 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3147 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 429274 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 429274 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 429274 # number of overall misses -system.cpu1.dcache.overall_misses::total 429274 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3175995000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3175995000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7543341183 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7543341183 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56499500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 56499500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22652500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22652500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10719336183 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10719336183 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10719336183 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10719336183 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1827527 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1827527 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172671 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1172671 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39380 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 39380 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35757 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35757 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3000198 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3000198 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3000198 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3000198 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114460 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114460 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187687 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187687 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137252 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137252 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088011 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088011 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143082 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143082 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143082 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143082 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15183.144580 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15183.144580 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34273.114714 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34273.114714 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10453.191489 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10453.191489 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7198.125199 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7198.125199 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24970.848882 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24970.848882 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 239004 # number of cycles access was blocked +system.cpu1.dcache.replacements 126485 # number of replacements +system.cpu1.dcache.tagsinuse 490.826755 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2951833 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 126890 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 23.262929 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 490.826755 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.958646 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.958646 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1783497 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1783497 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1082553 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1082553 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39938 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39938 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38621 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 38621 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2866050 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2866050 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2866050 # number of overall hits +system.cpu1.dcache.overall_hits::total 2866050 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 242860 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 242860 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 251463 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 251463 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6629 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6629 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3956 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3956 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 494323 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 494323 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 494323 # number of overall misses +system.cpu1.dcache.overall_misses::total 494323 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3676780500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3676780500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8111413586 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8111413586 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67692000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 67692000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29045500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 29045500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11788194086 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11788194086 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11788194086 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11788194086 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2026357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42577 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 42577 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3360373 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3360373 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3360373 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3360373 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119851 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.119851 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188501 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.188501 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142354 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142354 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092914 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092914 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147104 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.147104 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147104 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.147104 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15139.506300 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15139.506300 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32256.887041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32256.887041 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10211.494946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10211.494946 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.138524 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.138524 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23847.148698 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23847.148698 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 244071 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3894 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4071 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.377504 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 59.953574 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72044 # number of writebacks -system.cpu1.dcache.writebacks::total 72044 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129793 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129793 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180819 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 180819 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 604 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 604 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 310612 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 310612 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 310612 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 310612 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79386 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79386 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39276 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39276 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4801 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4801 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3147 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3147 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118662 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118662 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118662 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118662 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 971821000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 971821000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1116428485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1116428485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39070500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39070500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16358500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16358500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088249485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2088249485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088249485 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2088249485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30977500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30977500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647178500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647178500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678156000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678156000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043439 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043439 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033493 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033493 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121915 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121915 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088011 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088011 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039551 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039551 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.717683 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12241.717683 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28425.208397 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28425.208397 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8137.992085 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8137.992085 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5198.125199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5198.125199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 84853 # number of writebacks +system.cpu1.dcache.writebacks::total 84853 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150731 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 150731 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205632 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 205632 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 643 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 643 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 356363 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 356363 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 356363 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 356363 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92129 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 92129 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45831 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 45831 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5986 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5986 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3956 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 137960 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 137960 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 137960 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 137960 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1123159500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1123159500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1210930487 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1210930487 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47601500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47601500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21133500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21133500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2334089987 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2334089987 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2334089987 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2334089987 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30974500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30974500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675233500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675233500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045465 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045465 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034356 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092914 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092914 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041055 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041055 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12191.161306 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12191.161306 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1729,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6549 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181634 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64148 40.44% 40.44% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.21% 41.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92227 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158624 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63158 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62964 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128371 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862438042500 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62559000 0.00% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567042000 0.03% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 94587500 0.00% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34644439500 1.83% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897806670500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984567 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682707 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809279 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1786,60 +1786,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151888 91.03% 93.33% # number of callpals executed -system.cpu0.kern.callpal::rdps 6165 3.69% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4486 2.69% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166848 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed +system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed +system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 161075 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1258 system.cpu0.kern.mode_good::user 1259 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.180023 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.305202 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895901736500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1904926000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3470 # number of times the context was actually changed +system.cpu0.kern.swap_context 3343 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2462 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58111 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18212 36.94% 36.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.90% 40.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28864 58.55% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49296 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17825 47.44% 47.44% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 5.12% 52.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17528 46.65% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37573 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872585348000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531683000 0.03% 98.71% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 134630500 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24248440000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897500101500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978750 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.607262 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.762192 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1863,36 +1863,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43980 85.81% 88.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2592 5.06% 93.50% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed -system.cpu1.kern.callpal::rti 3095 6.04% 99.56% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 255 0.44% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1393 2.41% 2.86% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.87% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.88% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49964 86.52% 89.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2595 4.49% 93.90% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.90% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.91% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.91% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.91% # number of callpals executed +system.cpu1.kern.callpal::rti 3286 5.69% 99.61% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.32% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51254 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches -system.cpu1.kern.mode_switch::user 489 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 710 -system.cpu1.kern.mode_good::user 489 -system.cpu1.kern.mode_good::idle 221 -system.cpu1.kern.mode_switch_good::kernel 0.498596 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 57746 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1619 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 771 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 283 +system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090722 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.326512 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4824136000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 831285000 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891834463500 99.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1141 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a041cd935..46893c808 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -520,7 +520,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -540,7 +540,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -615,6 +615,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -646,7 +647,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 80fb6a8f2..e4e5656be 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 10:45:16 -gem5 started Feb 13 2013 13:46:08 -gem5 executing on u200540-lin +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:18:16 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1854310111000 because m5_exit instruction encountered +Exiting @ tick 1854315933000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 7557c7dd3..f7cc8bd0e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854310449000 # Number of ticks simulated -final_tick 1854310449000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854316 # Number of seconds simulated +sim_ticks 1854315933000 # Number of ticks simulated +final_tick 1854315933000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91767 # Simulator instruction rate (inst/s) -host_op_rate 91767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3212612251 # Simulator tick rate (ticks/s) -host_mem_usage 333588 # Number of bytes of host memory used -host_seconds 577.20 # Real time elapsed on the host -sim_insts 52967561 # Number of instructions simulated -sim_ops 52967561 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875392 # Number of bytes read from this memory +host_inst_rate 49330 # Simulator instruction rate (inst/s) +host_op_rate 49330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1727408560 # Simulator tick rate (ticks/s) +host_mem_usage 351576 # Number of bytes of host memory used +host_seconds 1073.47 # Real time elapsed on the host +sim_insts 52953842 # Number of instructions simulated +sim_ops 52953842 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28492160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7502272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7502272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388678 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7502848 # Number of bytes written to this memory +system.physmem.bytes_written::total 7502848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445190 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117223 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117223 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15365367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19411222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445190 # Total number of read requests seen -system.physmem.writeReqs 117223 # Total number of write requests seen -system.physmem.cpureqs 562598 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28492160 # Total number of bytes read from memory -system.physmem.bytesWritten 7502272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28492160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7502272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28082 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7509 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7384 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis +system.physmem.num_reads::total 445253 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117232 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117232 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13416864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15367496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4046154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4046154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4046154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13416864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19413650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445253 # Total number of read requests seen +system.physmem.writeReqs 117232 # Total number of write requests seen +system.physmem.cpureqs 562681 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28496192 # Total number of bytes read from memory +system.physmem.bytesWritten 7502848 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28496192 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7502848 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 180 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27571 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28084 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27782 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27722 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7292 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7370 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7331 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7642 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854305000000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854310455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445190 # Categorize read packet sizes +system.physmem.readPktSize::6 445253 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117223 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117232 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -128,46 +128,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5079 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.totQLat 7465727500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15177783750 # Sum of mem lat for all requests -system.physmem.totBusLat 2225655000 # Total cycles spent in databus access -system.physmem.totBankLat 5486401250 # Total cycles spent in bank access -system.physmem.avgQLat 16771.98 # Average queueing delay per request -system.physmem.avgBankLat 12325.36 # Average bank access latency per request +system.physmem.wrQLenPdf::15 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.totQLat 7494847250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15211767250 # Sum of mem lat for all requests +system.physmem.totBusLat 2225940000 # Total cycles spent in databus access +system.physmem.totBankLat 5490980000 # Total cycles spent in bank access +system.physmem.avgQLat 16835.24 # Average queueing delay per request +system.physmem.avgBankLat 12334.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34097.34 # Average memory access latency +system.physmem.avgMemAccLat 34169.31 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -175,21 +175,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.50 # Average write queue length over time -system.physmem.readRowHits 417731 # Number of row buffer hits during reads -system.physmem.writeRowHits 91366 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes -system.physmem.avgGap 3297052.17 # Average gap between requests +system.physmem.avgWrQLen 12.10 # Average write queue length over time +system.physmem.readRowHits 417708 # Number of row buffer hits during reads +system.physmem.writeRowHits 91270 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.85 # Row buffer hit rate for writes +system.physmem.avgGap 3296639.83 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265060 # Cycle average of tags in use +system.iocache.tagsinuse 1.265086 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265060 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704475467000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265086 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079068 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079068 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10634247416 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10634247416 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10655175414 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10655175414 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10655175414 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10655175414 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10643328423 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10643328423 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10664256421 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10664256421 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10664256421 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10664256421 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.247016 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255926.247016 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255366.696561 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255366.696561 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255366.696561 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 283342 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256144.792621 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256144.792621 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255584.336034 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255584.336034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27068 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27214 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.467785 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.438010 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472247190 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8472247190 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8484178439 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8484178439 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8484178439 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8484178439 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8481334185 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8481334185 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8493265434 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8493265434 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8493265434 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8493265434 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203895.051742 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203895.051742 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.612678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203335.612678 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204113.741456 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204113.741456 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13849744 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9420297 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5813323 # Number of BTB hits +system.cpu.branchPred.lookups 13854129 # Number of BP lookups +system.cpu.branchPred.condPredicted 11621858 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 400402 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9160821 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5815827 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.710613 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 901783 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38632 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.485871 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906747 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38946 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912266 # DTB read hits -system.cpu.dtb.read_misses 41544 # DTB read misses -system.cpu.dtb.read_acv 542 # DTB read access violations -system.cpu.dtb.read_accesses 940163 # DTB read accesses -system.cpu.dtb.write_hits 6601788 # DTB write hits -system.cpu.dtb.write_misses 10570 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 337668 # DTB write accesses -system.cpu.dtb.data_hits 16514054 # DTB hits -system.cpu.dtb.data_misses 52114 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1277831 # DTB accesses -system.cpu.itb.fetch_hits 1306011 # ITB hits -system.cpu.itb.fetch_misses 36868 # ITB misses -system.cpu.itb.fetch_acv 1103 # ITB acv -system.cpu.itb.fetch_accesses 1342879 # ITB accesses +system.cpu.dtb.read_hits 9920210 # DTB read hits +system.cpu.dtb.read_misses 41076 # DTB read misses +system.cpu.dtb.read_acv 544 # DTB read access violations +system.cpu.dtb.read_accesses 941527 # DTB read accesses +system.cpu.dtb.write_hits 6593814 # DTB write hits +system.cpu.dtb.write_misses 10775 # DTB write misses +system.cpu.dtb.write_acv 404 # DTB write access violations +system.cpu.dtb.write_accesses 338229 # DTB write accesses +system.cpu.dtb.data_hits 16514024 # DTB hits +system.cpu.dtb.data_misses 51851 # DTB misses +system.cpu.dtb.data_acv 948 # DTB access violations +system.cpu.dtb.data_accesses 1279756 # DTB accesses +system.cpu.itb.fetch_hits 1305070 # ITB hits +system.cpu.itb.fetch_misses 36981 # ITB misses +system.cpu.itb.fetch_acv 1089 # ITB acv +system.cpu.itb.fetch_accesses 1342051 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,134 +326,134 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108629038 # number of cpu cycles simulated +system.cpu.numCycles 108723981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28026689 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70680176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13849744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6715106 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13246427 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1984359 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37388108 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32353 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254081 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 294447 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 699 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8549154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266665 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80527554 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221537 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28071835 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70691782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13854129 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6722574 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13248795 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1991444 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37396273 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253900 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 295773 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 814 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8551942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266251 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80590196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67281127 83.55% 83.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 855303 1.06% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1700571 2.11% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 822573 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2750497 3.42% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561265 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645561 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010923 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4899734 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67341401 83.56% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854251 1.06% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1698632 2.11% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 828031 1.03% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750245 3.41% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562298 0.70% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 643304 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1012392 1.26% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4899642 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80527554 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127496 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650656 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29153725 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37057832 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12110647 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962931 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242418 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69379302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129899 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242418 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30276016 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13626490 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19778343 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11345486 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4258799 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65628358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6970 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 508418 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1479478 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43831634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79654682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79176161 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478521 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170118 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5661508 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12113982 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10427074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6890989 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312659 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851378 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58169067 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2051551 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56810875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88738 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6892578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390624 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80527554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366898 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80590196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127425 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650195 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29205934 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37061149 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12112258 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1247803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585584 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42566 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69386312 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128816 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1247803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30327018 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13624252 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19779589 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11347768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4263764 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65637148 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6817 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 509709 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1485643 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43822331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79670452 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79191261 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479191 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38158982 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5663341 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1681975 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239504 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12131366 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10436836 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6902083 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1326454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 859310 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58185317 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56802944 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 107134 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6922426 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389358 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80590196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704837 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365985 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55885936 69.40% 69.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10804988 13.42% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5163321 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3374568 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2652291 3.29% 96.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461239 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 754842 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331822 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 98547 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55946315 69.42% 69.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10805415 13.41% 82.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162410 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3384715 4.20% 93.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645600 3.28% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461420 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 757318 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 330868 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96135 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80527554 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80590196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91181 11.49% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373750 47.11% 58.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328508 41.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91816 11.60% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373288 47.16% 58.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326368 41.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38738406 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38732288 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61693 0.11% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued @@ -481,114 +481,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10344574 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680654 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949005 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10350848 18.22% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6672590 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948996 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56810875 # Type of FU issued -system.cpu.iq.rate 0.522981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 793439 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013966 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194338715 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66791274 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55577661 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692765 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335658 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327829 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57234972 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 601138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56802944 # Type of FU issued +system.cpu.iq.rate 0.522451 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791472 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013934 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194402098 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66835363 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55566146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692591 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327919 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57225685 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 601434 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1337046 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 514312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1348949 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4999 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14153 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 526604 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17961 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173725 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17963 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 174400 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242418 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9954083 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684701 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63749782 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676077 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10427074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6890989 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1807007 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18311 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 203273 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412234 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615507 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56340822 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9981988 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 470052 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1247803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9948703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63760053 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 677795 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10436836 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6902083 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805728 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512612 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14153 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203761 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412011 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615772 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56335729 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9989502 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467214 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3529164 # number of nop insts executed -system.cpu.iew.exec_refs 16609586 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925674 # Number of branches executed -system.cpu.iew.exec_stores 6627598 # Number of stores executed -system.cpu.iew.exec_rate 0.518653 # Inst execution rate -system.cpu.iew.wb_sent 56019458 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55905490 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27772636 # num instructions producing a value -system.cpu.iew.wb_consumers 37602554 # num instructions consuming a value +system.cpu.iew.exec_nop 3524453 # number of nop insts executed +system.cpu.iew.exec_refs 16609334 # number of memory reference insts executed +system.cpu.iew.exec_branches 8926219 # Number of branches executed +system.cpu.iew.exec_stores 6619832 # Number of stores executed +system.cpu.iew.exec_rate 0.518154 # Inst execution rate +system.cpu.iew.wb_sent 56008573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55894065 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27763400 # num instructions producing a value +system.cpu.iew.wb_consumers 37619407 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514646 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738584 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514091 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738007 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7474791 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660927 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568232 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79285136 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637990 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7499464 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660925 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569249 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79342393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.636795 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58523209 73.81% 73.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8600768 10.85% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4599944 5.80% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533685 3.20% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1517149 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 606925 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 524667 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 525488 0.66% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1853301 2.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58576225 73.83% 73.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8604152 10.84% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4604262 5.80% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2532350 3.19% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516866 1.91% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 607587 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 525202 0.66% 97.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528895 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1846854 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79285136 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56157758 # Number of instructions committed -system.cpu.commit.committedOps 56157758 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79342393 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56143434 # Number of instructions committed +system.cpu.commit.committedOps 56143434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15466705 # Number of memory references committed -system.cpu.commit.loads 9090028 # Number of loads committed -system.cpu.commit.membars 226335 # Number of memory barriers committed -system.cpu.commit.branches 8438960 # Number of branches committed +system.cpu.commit.refs 15463366 # Number of memory references committed +system.cpu.commit.loads 9087887 # Number of loads committed +system.cpu.commit.membars 226338 # Number of memory barriers committed +system.cpu.commit.branches 8437404 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52008025 # Number of committed integer instructions. -system.cpu.commit.function_calls 740393 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1853301 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51994306 # Number of committed integer instructions. +system.cpu.commit.function_calls 740223 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1846854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140814788 # The number of ROB reads -system.cpu.rob.rob_writes 128509305 # The number of ROB writes -system.cpu.timesIdled 1177982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28101484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599985419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52967561 # Number of Instructions Simulated -system.cpu.committedOps 52967561 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52967561 # Number of Instructions Simulated -system.cpu.cpi 2.050860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.050860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487600 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73882509 # number of integer regfile reads -system.cpu.int_regfile_writes 40314112 # number of integer regfile writes -system.cpu.fp_regfile_reads 165977 # number of floating regfile reads -system.cpu.fp_regfile_writes 167436 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987247 # number of misc regfile reads -system.cpu.misc_regfile_writes 938923 # number of misc regfile writes +system.cpu.rob.rob_reads 140888897 # The number of ROB reads +system.cpu.rob.rob_writes 128535372 # The number of ROB writes +system.cpu.timesIdled 1178030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28133785 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599901445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52953842 # Number of Instructions Simulated +system.cpu.committedOps 52953842 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52953842 # Number of Instructions Simulated +system.cpu.cpi 2.053184 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.053184 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487048 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487048 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73863718 # number of integer regfile reads +system.cpu.int_regfile_writes 40309148 # number of integer regfile writes +system.cpu.fp_regfile_reads 166055 # number of floating regfile reads +system.cpu.fp_regfile_writes 167445 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987577 # number of misc regfile reads +system.cpu.misc_regfile_writes 938916 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,193 +620,193 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008504 # number of replacements -system.cpu.icache.tagsinuse 510.288693 # Cycle average of tags in use -system.cpu.icache.total_refs 7484267 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.417421 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288693 # Average occupied blocks per requestor +system.cpu.icache.replacements 1008056 # number of replacements +system.cpu.icache.tagsinuse 510.288662 # Cycle average of tags in use +system.cpu.icache.total_refs 7486559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1008564 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.422989 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20267924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288662 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996658 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996658 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7484268 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7484268 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7484268 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7484268 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7484268 # number of overall hits -system.cpu.icache.overall_hits::total 7484268 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064885 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064885 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064885 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064885 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064885 # number of overall misses -system.cpu.icache.overall_misses::total 1064885 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14670837493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14670837493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14670837493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14670837493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14670837493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14670837493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8549153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8549153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8549153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8549153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8549153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8549153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124560 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124560 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124560 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124560 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124560 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124560 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.921915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13776.921915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13776.921915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.921915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13776.921915 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5769 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.935294 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 7486560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7486560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7486560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7486560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7486560 # number of overall hits +system.cpu.icache.overall_hits::total 7486560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065380 # number of overall misses +system.cpu.icache.overall_misses::total 1065380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14692786493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14692786493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14692786493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14692786493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14692786493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14692786493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8551940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8551940 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8551940 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8551940 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8551940 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8551940 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13791.122879 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13791.122879 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13791.122879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13791.122879 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4755 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1956 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.793103 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 489 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55656 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55656 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55656 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55656 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55656 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55656 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009229 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009229 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009229 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009229 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009229 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009229 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12029446495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12029446495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12029446495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12029446495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12029446495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12029446495 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118050 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118050 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118050 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118050 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118050 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118050 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11919.441965 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11919.441965 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11919.441965 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11919.441965 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11919.441965 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11919.441965 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56595 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56595 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56595 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56595 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56595 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56595 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1008785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1008785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1008785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1008785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1008785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12038039995 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12038039995 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12038039995 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12038039995 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12038039995 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12038039995 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117960 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117960 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117960 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11933.206773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11933.206773 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11933.206773 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11933.206773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338273 # number of replacements -system.cpu.l2cache.tagsinuse 65365.869534 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2544201 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403437 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.306315 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 338326 # number of replacements +system.cpu.l2cache.tagsinuse 65364.753625 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2543033 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403496 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.302499 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53972.455267 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5323.078272 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6070.335995 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.823554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081224 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092626 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997404 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994045 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 826710 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1820755 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840363 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840363 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185332 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185332 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994045 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012042 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2006087 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 994045 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012042 # number of overall hits -system.cpu.l2cache.overall_hits::total 2006087 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15071 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273774 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288845 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 37 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 37 # number of UpgradeReq misses +system.cpu.l2cache.occ_blocks::writebacks 54051.179621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5324.310561 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 5989.263443 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.824756 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081243 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.091389 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997387 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 993589 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 826269 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1819858 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840029 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840029 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185368 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185368 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 993589 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1011637 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2005226 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 993589 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1011637 # number of overall hits +system.cpu.l2cache.overall_hits::total 2005226 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15076 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273797 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288873 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 40 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 40 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115394 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115394 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15071 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404239 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15071 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389168 # number of overall misses -system.cpu.l2cache.overall_misses::total 404239 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1036442500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11953176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12989619000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 267000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 267000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7638606500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7638606500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1036442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19591783000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20628225500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1036442500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19591783000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20628225500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109600 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840363 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840363 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300726 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300726 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1009116 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401210 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2410326 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1009116 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401210 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2410326 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014935 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248776 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136919 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.606557 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.606557 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383718 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383718 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014935 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167711 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014935 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167711 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.652246 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43660.743898 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 44970.897886 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7216.216216 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7216.216216 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66195.872402 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66195.872402 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68770.652246 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50342.738869 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51029.775702 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68770.652246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50342.738869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51029.775702 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15076 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389229 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404305 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15076 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389229 # number of overall misses +system.cpu.l2cache.overall_misses::total 404305 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1050370500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11953523500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13003894000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 302500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 302500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7672961500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7672961500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1050370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19626485000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20676855500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1050370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19626485000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20676855500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008665 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100066 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108731 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840029 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840029 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300800 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300800 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1008665 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1400866 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2409531 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1008665 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1400866 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2409531 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014946 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248891 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136989 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.597015 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.597015 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383750 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383750 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277849 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167794 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277849 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167794 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69671.696737 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43658.343590 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 45015.955108 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7562.500000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7562.500000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66471.701954 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66471.701954 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69671.696737 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50424.004892 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51141.725925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69671.696737 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50424.004892 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51141.725925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,80 +815,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75711 # number of writebacks -system.cpu.l2cache.writebacks::total 75711 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75720 # number of writebacks +system.cpu.l2cache.writebacks::total 75720 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15070 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273774 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288844 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15075 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273797 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288872 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 40 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 40 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115394 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115394 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15070 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389168 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404238 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15070 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404238 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 848510264 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8602226741 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9450737005 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 527532 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 527532 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404304 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404304 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 862398247 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8602310526 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9464708773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 569536 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 569536 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6229012981 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6229012981 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 848510264 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14831239722 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15679749986 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 848510264 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14831239722 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15679749986 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333826500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333826500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882595500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882595500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216422000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216422000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248776 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.606557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.606557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383718 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383718 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167711 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167711 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.596151 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.904618 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.173689 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14257.621622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14257.621622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262852352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262852352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 862398247 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14865162878 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15727561125 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 862398247 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14865162878 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15727561125 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333774000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333774000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882495000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882495000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216269000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216269000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.597015 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.597015 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277849 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277849 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57207.180564 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.571153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32764.368900 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14238.400000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14238.400000 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53980.388764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53980.388764 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54255.772680 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54255.772680 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57207.180564 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38191.303521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.335206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57207.180564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38191.303521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.335206 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -896,161 +896,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400618 # number of replacements -system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use -system.cpu.dcache.total_refs 11803573 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401130 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.424324 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1400274 # number of replacements +system.cpu.dcache.tagsinuse 511.995157 # Cycle average of tags in use +system.cpu.dcache.total_refs 11811900 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1400786 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.432337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995157 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7198104 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7198104 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203343 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203343 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186395 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186395 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7207099 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7207099 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203008 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203008 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186038 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186038 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11401447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11401447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11401447 # number of overall hits -system.cpu.dcache.overall_hits::total 11401447 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802656 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802656 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1943125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1943125 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22671 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22671 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745781 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745781 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745781 # number of overall misses -system.cpu.dcache.overall_misses::total 3745781 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33855022500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33855022500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64910918483 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64910918483 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 64000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98765940983 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98765940983 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98765940983 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98765940983 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9000760 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9000760 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146468 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146468 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209066 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209066 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15147228 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15147228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15147228 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15147228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200278 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316137 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316137 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247292 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247292 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18780.633965 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18780.633965 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33405.426045 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33405.426045 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13525.627454 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13525.627454 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26367.249175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26367.249175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2192171 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95789 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.885415 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked +system.cpu.dcache.demand_hits::cpu.data 11410107 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11410107 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11410107 # number of overall hits +system.cpu.dcache.overall_hits::total 11410107 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800868 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800868 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1942264 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1942264 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3743132 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3743132 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3743132 # number of overall misses +system.cpu.dcache.overall_misses::total 3743132 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33858803000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33858803000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 65085084522 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 65085084522 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304812500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 304812500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 37500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 37500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98943887522 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98943887522 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98943887522 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98943887522 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9007967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9007967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6145272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6145272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208781 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208781 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215507 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215507 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15153239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15153239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15153239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15153239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199919 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316058 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316058 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108932 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108932 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247019 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247019 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247019 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247019 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18801.379668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18801.379668 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33509.906234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33509.906234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13402.475487 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13402.475487 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26433.448653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26433.448653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26433.448653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26433.448653 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2202746 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.964647 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840363 # number of writebacks -system.cpu.dcache.writebacks::total 840363 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719064 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 719064 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642999 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642999 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5119 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5119 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362063 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362063 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362063 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362063 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083592 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083592 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300126 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300126 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17552 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17552 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383718 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383718 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383718 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383718 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21332679000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21332679000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9855100772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9855100772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200264000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200264000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 56000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187779772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31187779772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187779772 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31187779772 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423903500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423903500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997763498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997763498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421666998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421666998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091351 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091351 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19687.003042 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19687.003042 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32836.544558 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32836.544558 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11409.753874 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11409.753874 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840029 # number of writebacks +system.cpu.dcache.writebacks::total 840029 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717621 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717621 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642056 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5266 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5266 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359677 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359677 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359677 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359677 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083247 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083247 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300208 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300208 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17477 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17477 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383455 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383455 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21329073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21329073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9889442761 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9889442761 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199091500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199091500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31218515761 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31218515761 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31218515761 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31218515761 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423851000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423851000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997662998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997662998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421513998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421513998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083710 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083710 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091298 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091298 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19689.944214 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19689.944214 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32941.969438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32941.969438 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11391.628998 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11391.628998 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1059,28 +1059,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211000 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182231 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818337876500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63843000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 549015500 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35358867000 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309602000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818345164500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63914000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 557987500 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35348021500 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854315087500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815438 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1119,7 +1119,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175116 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1128,20 +1128,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191960 # number of callpals executed +system.cpu.kern.callpal::total 191959 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326723 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394549 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29457658500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2706866000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822145069500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29469027500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2713167500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822132884500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index d353d9284..ad99994ae 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/projects/pd/randd/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/projects/pd/randd/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -581,7 +581,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -601,7 +601,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -698,6 +698,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -729,7 +730,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index c03321be6..9227d5948 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:38 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 23:27:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second @@ -18,204 +18,207 @@ info: Entering event queue @ 1000000000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 2000000000. Starting simulation... +info: Entering event queue @ 2000003000. Starting simulation... switching cpus -info: Entering event queue @ 2000001000. Starting simulation... +info: Entering event queue @ 2000005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000001000. Starting simulation... -info: Entering event queue @ 3000043000. Starting simulation... +info: Entering event queue @ 3000005500. Starting simulation... switching cpus -info: Entering event queue @ 3000047500. Starting simulation... +info: Entering event queue @ 3000041000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4000047500. Starting simulation... +info: Entering event queue @ 4000041000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5000047500. Starting simulation... +info: Entering event queue @ 5000041000. Starting simulation... +info: Entering event queue @ 5000053000. Starting simulation... switching cpus -info: Entering event queue @ 5000048000. Starting simulation... +info: Entering event queue @ 5000056500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000048000. Starting simulation... -info: Entering event queue @ 7452589500. Starting simulation... -info: Entering event queue @ 7452657000. Starting simulation... +info: Entering event queue @ 6000056500. Starting simulation... +info: Entering event queue @ 7458944500. Starting simulation... +info: Entering event queue @ 7459012000. Starting simulation... switching cpus -info: Entering event queue @ 7452661500. Starting simulation... +info: Entering event queue @ 7459016500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 8452661500. Starting simulation... +info: Entering event queue @ 8459016500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 9452661500. Starting simulation... -info: Entering event queue @ 9452675500. Starting simulation... +info: Entering event queue @ 9459016500. Starting simulation... switching cpus -info: Entering event queue @ 9452679000. Starting simulation... +info: Entering event queue @ 9459024000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 10452679000. Starting simulation... +info: Entering event queue @ 10459024000. Starting simulation... switching cpus -info: Entering event queue @ 10452682000. Starting simulation... +info: Entering event queue @ 10459031500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 11452682000. Starting simulation... +info: Entering event queue @ 11459031500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 12452682000. Starting simulation... -info: Entering event queue @ 12452693500. Starting simulation... +info: Entering event queue @ 12459031500. Starting simulation... +info: Entering event queue @ 12459047000. Starting simulation... switching cpus -info: Entering event queue @ 12452696000. Starting simulation... +info: Entering event queue @ 12459242750. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 13452696000. Starting simulation... +info: Entering event queue @ 13459242750. Starting simulation... +info: Entering event queue @ 13459250250. Starting simulation... +info: Entering event queue @ 13459254000. Starting simulation... switching cpus -info: Entering event queue @ 13452709500. Starting simulation... +info: Entering event queue @ 13459258500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 14452709500. Starting simulation... +info: Entering event queue @ 14459258500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 15452709500. Starting simulation... -info: Entering event queue @ 15452713500. Starting simulation... +info: Entering event queue @ 15459258500. Starting simulation... switching cpus -info: Entering event queue @ 15452714500. Starting simulation... +info: Entering event queue @ 15459266000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 16452714500. Starting simulation... +info: Entering event queue @ 16459266000. Starting simulation... switching cpus -info: Entering event queue @ 16452717000. Starting simulation... +info: Entering event queue @ 16459273500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 17452717000. Starting simulation... +info: Entering event queue @ 17459273500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 18452717000. Starting simulation... -info: Entering event queue @ 18452728500. Starting simulation... +info: Entering event queue @ 18459273500. Starting simulation... +info: Entering event queue @ 18459284000. Starting simulation... switching cpus -info: Entering event queue @ 18452732000. Starting simulation... +info: Entering event queue @ 18459287500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 19452732000. Starting simulation... -info: Entering event queue @ 19452741000. Starting simulation... +info: Entering event queue @ 19459287500. Starting simulation... switching cpus -info: Entering event queue @ 19452745500. Starting simulation... +info: Entering event queue @ 19459295000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 20452745500. Starting simulation... +info: Entering event queue @ 20459295000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 21452745500. Starting simulation... +info: Entering event queue @ 21459295000. Starting simulation... switching cpus -info: Entering event queue @ 21452746000. Starting simulation... +info: Entering event queue @ 21459296000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 22452746000. Starting simulation... +info: Entering event queue @ 22459296000. Starting simulation... switching cpus -info: Entering event queue @ 22452748000. Starting simulation... +info: Entering event queue @ 22459303500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 23452748000. Starting simulation... +info: Entering event queue @ 23459303500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 24452748000. Starting simulation... +info: Entering event queue @ 24459303500. Starting simulation... switching cpus -info: Entering event queue @ 24452750000. Starting simulation... +info: Entering event queue @ 24459311000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 25452750000. Starting simulation... -info: Entering event queue @ 25452773000. Starting simulation... +info: Entering event queue @ 25459311000. Starting simulation... +info: Entering event queue @ 25459330000. Starting simulation... +info: Entering event queue @ 25459339500. Starting simulation... +info: Entering event queue @ 25459344000. Starting simulation... switching cpus -info: Entering event queue @ 25452778500. Starting simulation... +info: Entering event queue @ 25459345000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 26452778500. Starting simulation... +info: Entering event queue @ 26459345000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 27452778500. Starting simulation... -info: Entering event queue @ 27452782500. Starting simulation... +info: Entering event queue @ 27459345000. Starting simulation... +info: Entering event queue @ 27459352500. Starting simulation... switching cpus -info: Entering event queue @ 27452786000. Starting simulation... +info: Entering event queue @ 27459355500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 28452786000. Starting simulation... -info: Entering event queue @ 28452802500. Starting simulation... +info: Entering event queue @ 28459355500. Starting simulation... +info: Entering event queue @ 28459377000. Starting simulation... switching cpus -info: Entering event queue @ 28452808000. Starting simulation... +info: Entering event queue @ 28459573000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 29452808000. Starting simulation... +info: Entering event queue @ 29459573000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 30452808000. Starting simulation... +info: Entering event queue @ 30459573000. Starting simulation... switching cpus -info: Entering event queue @ 30452820500. Starting simulation... +info: Entering event queue @ 30459580500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 31452820500. Starting simulation... +info: Entering event queue @ 31459580500. Starting simulation... +info: Entering event queue @ 31459590000. Starting simulation... switching cpus -info: Entering event queue @ 31452823500. Starting simulation... +info: Entering event queue @ 31459594500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 32452823500. Starting simulation... +info: Entering event queue @ 32459594500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 33452823500. Starting simulation... +info: Entering event queue @ 33459594500. Starting simulation... switching cpus -info: Entering event queue @ 33452824500. Starting simulation... +info: Entering event queue @ 33459602000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 34452824500. Starting simulation... +info: Entering event queue @ 34459602000. Starting simulation... switching cpus -info: Entering event queue @ 34452827500. Starting simulation... +info: Entering event queue @ 34459605000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 35452827500. Starting simulation... +info: Entering event queue @ 35459605000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 36452827500. Starting simulation... +info: Entering event queue @ 36459605000. Starting simulation... switching cpus -info: Entering event queue @ 36452828500. Starting simulation... +info: Entering event queue @ 36459612500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 37452828500. Starting simulation... +info: Entering event queue @ 37459612500. Starting simulation... switching cpus -info: Entering event queue @ 37452831500. Starting simulation... +info: Entering event queue @ 37459615500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 38452831500. Starting simulation... +info: Entering event queue @ 38459615500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 39452831500. Starting simulation... +info: Entering event queue @ 39459615500. Starting simulation... switching cpus -info: Entering event queue @ 39452832500. Starting simulation... +info: Entering event queue @ 39459623000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 40452832500. Starting simulation... +info: Entering event queue @ 40459623000. Starting simulation... switching cpus -info: Entering event queue @ 40452835500. Starting simulation... +info: Entering event queue @ 40459626000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 41452835500. Starting simulation... +info: Entering event queue @ 41459626000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 42452835500. Starting simulation... +info: Entering event queue @ 42459626000. Starting simulation... switching cpus -info: Entering event queue @ 42452836500. Starting simulation... +info: Entering event queue @ 42459633500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 43452836500. Starting simulation... +info: Entering event queue @ 43459633500. Starting simulation... switching cpus info: Entering event queue @ 43945335500. Starting simulation... Switching CPUs... @@ -1088,18 +1091,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 304757835500. Starting simulation... switching cpus -info: Entering event queue @ 304758051500. Starting simulation... +info: Entering event queue @ 304757908000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 305758051500. Starting simulation... +info: Entering event queue @ 305757908000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 306758051500. Starting simulation... +info: Entering event queue @ 306757908000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 307758051500. Starting simulation... +info: Entering event queue @ 307757908000. Starting simulation... switching cpus info: Entering event queue @ 308593773000. Starting simulation... Switching CPUs... @@ -1968,10 +1971,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 568406273000. Starting simulation... switching cpus -info: Entering event queue @ 568406301000. Starting simulation... +info: Entering event queue @ 568406377000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 569406301000. Starting simulation... +info: Entering event queue @ 569406377000. Starting simulation... switching cpus info: Entering event queue @ 570312523000. Starting simulation... Switching CPUs... @@ -2156,18 +2159,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 624093773500. Starting simulation... switching cpus -info: Entering event queue @ 624218766000. Starting simulation... +info: Entering event queue @ 624218753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 625218766000. Starting simulation... +info: Entering event queue @ 625218753000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 626218766000. Starting simulation... +info: Entering event queue @ 626218753000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 627218766000. Starting simulation... +info: Entering event queue @ 627218753000. Starting simulation... switching cpus info: Entering event queue @ 627929709000. Starting simulation... Switching CPUs... @@ -2529,10 +2532,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 735398460500. Starting simulation... switching cpus -info: Entering event queue @ 735398461500. Starting simulation... +info: Entering event queue @ 735398468000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 736398461500. Starting simulation... +info: Entering event queue @ 736398468000. Starting simulation... switching cpus info: Entering event queue @ 737304710500. Starting simulation... Switching CPUs... @@ -2881,10 +2884,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 840867210500. Starting simulation... switching cpus -info: Entering event queue @ 840867211500. Starting simulation... +info: Entering event queue @ 840867218000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 841867211500. Starting simulation... +info: Entering event queue @ 841867218000. Starting simulation... switching cpus info: Entering event queue @ 842773460500. Starting simulation... Switching CPUs... @@ -3233,10 +3236,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 946335960500. Starting simulation... switching cpus -info: Entering event queue @ 946335961500. Starting simulation... +info: Entering event queue @ 946335968000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 947335961500. Starting simulation... +info: Entering event queue @ 947335968000. Starting simulation... switching cpus info: Entering event queue @ 948242210500. Starting simulation... Switching CPUs... @@ -3936,49 +3939,49 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1157273460500. Starting simulation... switching cpus -info: Entering event queue @ 1157273461000. Starting simulation... +info: Entering event queue @ 1157273468000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1158273461000. Starting simulation... +info: Entering event queue @ 1158273468000. Starting simulation... switching cpus -info: Entering event queue @ 1159361004000. Starting simulation... +info: Entering event queue @ 1159362057000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1160361004000. Starting simulation... +info: Entering event queue @ 1160362057000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1161361004000. Starting simulation... +info: Entering event queue @ 1161362057000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1162361004000. Starting simulation... +info: Entering event queue @ 1162362057000. Starting simulation... switching cpus -info: Entering event queue @ 1162361007000. Starting simulation... +info: Entering event queue @ 1162362060000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1163361007000. Starting simulation... +info: Entering event queue @ 1163362060000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1164361007000. Starting simulation... +info: Entering event queue @ 1164362060000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1165361007000. Starting simulation... +info: Entering event queue @ 1165362060000. Starting simulation... switching cpus -info: Entering event queue @ 1165361010000. Starting simulation... +info: Entering event queue @ 1165362063000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1166361010000. Starting simulation... +info: Entering event queue @ 1166362063000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1167361010000. Starting simulation... +info: Entering event queue @ 1167362063000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1168361010000. Starting simulation... +info: Entering event queue @ 1168362063000. Starting simulation... switching cpus info: Entering event queue @ 1168945335500. Starting simulation... Switching CPUs... @@ -5731,10 +5734,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1694382835500. Starting simulation... switching cpus -info: Entering event queue @ 1694382836500. Starting simulation... +info: Entering event queue @ 1694382843000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1695382836500. Starting simulation... +info: Entering event queue @ 1695382843000. Starting simulation... switching cpus info: Entering event queue @ 1696289085500. Starting simulation... Switching CPUs... @@ -5771,10 +5774,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1706101585500. Starting simulation... switching cpus -info: Entering event queue @ 1706101586500. Starting simulation... +info: Entering event queue @ 1706101593000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1707101586500. Starting simulation... +info: Entering event queue @ 1707101593000. Starting simulation... switching cpus info: Entering event queue @ 1708007835500. Starting simulation... Switching CPUs... @@ -5900,11 +5903,12 @@ switching cpus info: Entering event queue @ 1744164085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -switching cpus info: Entering event queue @ 1745164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1745164093000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1746164085500. Starting simulation... +info: Entering event queue @ 1746164093000. Starting simulation... switching cpus info: Entering event queue @ 1747070335500. Starting simulation... Switching CPUs... @@ -5980,10 +5984,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1768601585500. Starting simulation... switching cpus -info: Entering event queue @ 1768601735500. Starting simulation... +info: Entering event queue @ 1768601593000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769601735500. Starting simulation... +info: Entering event queue @ 1769601593000. Starting simulation... switching cpus info: Entering event queue @ 1770507835500. Starting simulation... Switching CPUs... @@ -6011,18 +6015,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1777414085500. Starting simulation... switching cpus -info: Entering event queue @ 1777414674000. Starting simulation... +info: Entering event queue @ 1777415067000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1778414674000. Starting simulation... +info: Entering event queue @ 1778415067000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1779414674000. Starting simulation... +info: Entering event queue @ 1779415067000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1780414674000. Starting simulation... +info: Entering event queue @ 1780415067000. Starting simulation... switching cpus info: Entering event queue @ 1781250023000. Starting simulation... Switching CPUs... @@ -6033,10 +6037,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1783250023000. Starting simulation... switching cpus -info: Entering event queue @ 1783250024000. Starting simulation... +info: Entering event queue @ 1783250030500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1784250024000. Starting simulation... +info: Entering event queue @ 1784250030500. Starting simulation... switching cpus info: Entering event queue @ 1785156273000. Starting simulation... Switching CPUs... @@ -6073,10 +6077,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1794968773000. Starting simulation... switching cpus -info: Entering event queue @ 1794968774000. Starting simulation... +info: Entering event queue @ 1794968780500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1795968774000. Starting simulation... +info: Entering event queue @ 1795968780500. Starting simulation... switching cpus info: Entering event queue @ 1796875023000. Starting simulation... Switching CPUs... @@ -6113,10 +6117,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1806687523000. Starting simulation... switching cpus -info: Entering event queue @ 1806687524000. Starting simulation... +info: Entering event queue @ 1806687530500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1807687524000. Starting simulation... +info: Entering event queue @ 1807687530500. Starting simulation... switching cpus info: Entering event queue @ 1808593773000. Starting simulation... Switching CPUs... @@ -6153,37 +6157,37 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1818406273000. Starting simulation... switching cpus -info: Entering event queue @ 1818406274000. Starting simulation... +info: Entering event queue @ 1818406280500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1819406274000. Starting simulation... +info: Entering event queue @ 1819406280500. Starting simulation... switching cpus -info: Entering event queue @ 1819406403500. Starting simulation... +info: Entering event queue @ 1819406919000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1820406403500. Starting simulation... +info: Entering event queue @ 1820406919000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1821406403500. Starting simulation... +info: Entering event queue @ 1821406919000. Starting simulation... switching cpus -info: Entering event queue @ 1821406404500. Starting simulation... +info: Entering event queue @ 1821406926500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1822406404500. Starting simulation... +info: Entering event queue @ 1822406926500. Starting simulation... switching cpus -info: Entering event queue @ 1822406407500. Starting simulation... +info: Entering event queue @ 1822406934000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1823406407500. Starting simulation... +info: Entering event queue @ 1823406934000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1824406407500. Starting simulation... +info: Entering event queue @ 1824406934000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1825406407500. Starting simulation... +info: Entering event queue @ 1825406934000. Starting simulation... switching cpus info: Entering event queue @ 1826171898000. Starting simulation... Switching CPUs... @@ -6197,21 +6201,22 @@ info: Entering event queue @ 1828171898000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1829171898000. Starting simulation... -info: Entering event queue @ 1829171913500. Starting simulation... +info: Entering event queue @ 1829171905500. Starting simulation... +info: Entering event queue @ 1829171910500. Starting simulation... switching cpus -info: Entering event queue @ 1829171918000. Starting simulation... +info: Entering event queue @ 1829171915000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1830171918000. Starting simulation... +info: Entering event queue @ 1830171915000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1831171918000. Starting simulation... +info: Entering event queue @ 1831171915000. Starting simulation... switching cpus -info: Entering event queue @ 1831171920000. Starting simulation... +info: Entering event queue @ 1831171922500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1832171920000. Starting simulation... +info: Entering event queue @ 1832171922500. Starting simulation... switching cpus info: Entering event queue @ 1833007835500. Starting simulation... Switching CPUs... @@ -6234,16 +6239,16 @@ info: Entering event queue @ 1837914085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1838914085500. Starting simulation... -info: Entering event queue @ 1838914092000. Starting simulation... +info: Entering event queue @ 1838914097000. Starting simulation... switching cpus -info: Entering event queue @ 1838914095500. Starting simulation... +info: Entering event queue @ 1838914100500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839914095500. Starting simulation... -info: Entering event queue @ 1839914105000. Starting simulation... +info: Entering event queue @ 1839914100500. Starting simulation... +info: Entering event queue @ 1839914110000. Starting simulation... switching cpus -info: Entering event queue @ 1839914109500. Starting simulation... +info: Entering event queue @ 1839914114500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1840914109500. Starting simulation... +info: Entering event queue @ 1840914114500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 65a9d1fb5..044f27d13 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685557500 # Number of ticks simulated -final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841723 # Number of seconds simulated +sim_ticks 1841722715000 # Number of ticks simulated +final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257826 # Simulator instruction rate (inst/s) -host_op_rate 257826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6831790357 # Simulator tick rate (ticks/s) -host_mem_usage 316032 # Number of bytes of host memory used -host_seconds 269.58 # Real time elapsed on the host -sim_insts 69503534 # Number of instructions simulated -sim_ops 69503534 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory -system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109963 # Total number of read requests seen -system.physmem.writeReqs 45515 # Total number of write requests seen -system.physmem.cpureqs 155519 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7037632 # Total number of bytes read from memory -system.physmem.bytesWritten 2912960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +host_inst_rate 105391 # Simulator instruction rate (inst/s) +host_op_rate 105391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2775370642 # Simulator tick rate (ticks/s) +host_mem_usage 350548 # Number of bytes of host memory used +host_seconds 663.60 # Real time elapsed on the host +sim_insts 69936964 # Number of instructions simulated +sim_ops 69936964 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109804 # Total number of read requests seen +system.physmem.writeReqs 45341 # Total number of write requests seen +system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7027456 # Total number of bytes read from memory +system.physmem.bytesWritten 2901824 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673470000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840710411000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.readPktSize::6 109804 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45515 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 45341 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1047 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,46 +148,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 2376402250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4386836000 # Sum of mem lat for all requests -system.physmem.totBusLat 549785000 # Total cycles spent in databus access -system.physmem.totBankLat 1460648750 # Total cycles spent in bank access -system.physmem.avgQLat 21612.11 # Average queueing delay per request -system.physmem.avgBankLat 13283.82 # Average bank access latency per request +system.physmem.wrQLenPdf::0 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.totQLat 2345988500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4348949750 # Sum of mem lat for all requests +system.physmem.totBusLat 548995000 # Total cycles spent in databus access +system.physmem.totBankLat 1453966250 # Total cycles spent in bank access +system.physmem.avgQLat 21366.21 # Average queueing delay per request +system.physmem.avgBankLat 13242.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39895.92 # Average memory access latency +system.physmem.avgMemAccLat 39608.28 # Average memory access latency system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s @@ -195,195 +195,195 @@ system.physmem.avgConsumedWrBW 1.58 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.16 # Average write queue length over time -system.physmem.readRowHits 99744 # Number of row buffer hits during reads -system.physmem.writeRowHits 34338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.44 # Row buffer hit rate for writes -system.physmem.avgGap 11838803.37 # Average gap between requests -system.l2c.replacements 337431 # number of replacements -system.l2c.tagsinuse 65421.769821 # Cycle average of tags in use -system.l2c.total_refs 2476371 # Total number of references to valid blocks. -system.l2c.sampled_refs 402593 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.151053 # Average number of references to valid blocks. +system.physmem.avgWrQLen 0.17 # Average write queue length over time +system.physmem.readRowHits 99788 # Number of row buffer hits during reads +system.physmem.writeRowHits 34189 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes +system.physmem.avgGap 11864452.04 # Average gap between requests +system.l2c.replacements 337462 # number of replacements +system.l2c.tagsinuse 65423.385083 # Cycle average of tags in use +system.l2c.total_refs 2475374 # Total number of references to valid blocks. +system.l2c.sampled_refs 402624 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.148103 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 54783.846469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2311.752265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2671.563738 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 585.881665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 667.174389 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2255.430098 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2146.121197 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.835935 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035275 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.040765 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.008940 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.010180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.034415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.032747 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998257 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 514621 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491109 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83687 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 298608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 242406 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757156 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836280 # number of Writeback hits -system.l2c.Writeback_hits::total 836280 # number of Writeback hits +system.l2c.occ_blocks::writebacks 54864.603018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2279.979000 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2628.690447 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 619.088006 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 659.286821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2246.098023 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2125.639768 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.837167 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.034790 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.040111 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.009447 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.010060 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.034273 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.032435 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998282 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 516841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 295482 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 241937 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1756357 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836151 # number of Writeback hits +system.l2c.Writeback_hits::total 836151 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92033 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 27042 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186915 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 514621 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126725 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 298608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 310246 # number of demand (read+write) hits -system.l2c.demand_hits::total 1944071 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 514621 # number of overall hits -system.l2c.overall_hits::cpu0.data 583142 # number of overall hits -system.l2c.overall_hits::cpu1.inst 126725 # number of overall hits -system.l2c.overall_hits::cpu1.data 110729 # number of overall hits -system.l2c.overall_hits::cpu2.inst 298608 # number of overall hits -system.l2c.overall_hits::cpu2.data 310246 # number of overall hits -system.l2c.overall_hits::total 1944071 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7410 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 225248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2345 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 23010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4608 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 24959 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 92117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 27417 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67376 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186910 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 516841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 583720 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 111024 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 295482 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 309313 # number of demand (read+write) hits +system.l2c.demand_hits::total 1943267 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 516841 # number of overall hits +system.l2c.overall_hits::cpu0.data 583720 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126887 # number of overall hits +system.l2c.overall_hits::cpu1.data 111024 # number of overall hits +system.l2c.overall_hits::cpu2.inst 295482 # number of overall hits +system.l2c.overall_hits::cpu2.data 309313 # number of overall hits +system.l2c.overall_hits::total 1943267 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7386 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 225256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2379 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 23009 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4597 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 24998 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287625 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77341 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21020 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17409 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115770 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7410 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 302589 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2345 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 44030 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4608 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 42368 # number of demand (read+write) misses -system.l2c.demand_misses::total 403350 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7410 # number of overall misses -system.l2c.overall_misses::cpu0.data 302589 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2345 # number of overall misses -system.l2c.overall_misses::cpu1.data 44030 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4608 # number of overall misses -system.l2c.overall_misses::cpu2.data 42368 # number of overall misses -system.l2c.overall_misses::total 403350 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 151883500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1053888000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 310106500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1117642500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2633520500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 979969000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1286505500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2266474500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 151883500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2033857000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 310106500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2404148000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4899995000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 151883500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2033857000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 310106500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2404148000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4899995000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 522031 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 716357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 129070 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 106697 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 303216 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 267365 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2044736 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 836280 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 836280 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77538 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 20985 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 17224 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115747 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7386 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 302794 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2379 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 43994 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4597 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 42222 # number of demand (read+write) misses +system.l2c.demand_misses::total 403372 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7386 # number of overall misses +system.l2c.overall_misses::cpu0.data 302794 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2379 # number of overall misses +system.l2c.overall_misses::cpu1.data 43994 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4597 # number of overall misses +system.l2c.overall_misses::cpu2.data 42222 # number of overall misses +system.l2c.overall_misses::total 403372 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 156027500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1047000000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 315202000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1118067500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2636297000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 291000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 973607000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1279851000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2253458000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 156027500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2020607000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 315202000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2397918500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4889755000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 156027500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2020607000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 315202000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2397918500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4889755000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 524227 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 716859 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 129266 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 106616 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 300079 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 266935 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2043982 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 836151 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 836151 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 169374 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48062 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 85249 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302685 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 522031 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 885731 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 129070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 154759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 303216 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 352614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2347421 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 522031 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 885731 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 129070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 154759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 303216 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 352614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2347421 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014195 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.314435 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.215657 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.015197 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.093352 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140644 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 169655 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 48402 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 84600 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302657 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 524227 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 886514 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 155018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 300079 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 351535 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2346639 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 524227 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 886514 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129266 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 155018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 300079 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 351535 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2346639 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014089 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.314226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018404 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215812 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015319 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.093648 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140718 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.714286 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.692308 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.456629 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.437352 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.204214 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382477 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014195 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.341626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.284507 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015197 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.120154 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171827 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014195 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.341626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.284507 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.015197 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.120154 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171827 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64769.083156 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 45801.303781 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67297.417535 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 44779.137786 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9157.523124 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16388.888889 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46620.789724 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73898.874146 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 19577.390516 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12148.245940 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 64769.083156 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46192.527822 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 67297.417535 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 56744.429758 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12148.245940 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.457033 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.433556 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.203593 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382436 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014089 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.341556 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018404 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.283799 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.120108 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171894 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014089 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.341556 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018404 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.283799 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.120108 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171894 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65585.329971 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 45503.933244 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 68566.891451 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 44726.278102 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9165.743590 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24250 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 14550 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46395.377651 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74306.258709 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 19468.824246 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 65585.329971 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 45929.149429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 68566.891451 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 56793.105490 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12122.197376 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 65585.329971 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 45929.149429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 68566.891451 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 56793.105490 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12122.197376 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,97 +392,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75316 # number of writebacks -system.l2c.writebacks::total 75316 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2345 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 23010 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4608 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 24959 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 54922 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21020 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 17409 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 38429 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2345 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 44030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4608 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 42368 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 93351 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2345 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 44030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4608 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 42368 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 93351 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122370842 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 770894982 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 252658268 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 814852254 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1960776346 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 261506 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 261506 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 720185758 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1074026983 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1794212741 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 122370842 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1491080740 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 252658268 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1888879237 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3754989087 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 122370842 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1491080740 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 252658268 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1888879237 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3754989087 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269544000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 323045500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 592589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337247500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 397454500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 734702000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606791500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 720500000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1327291500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.215657 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093352 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.026860 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.714286 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437352 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.204214 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.126960 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.039767 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.284507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.120154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.039767 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33502.606780 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32647.632277 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 35701.109683 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26150.600000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26150.600000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34261.929496 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61693.778103 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 46689.030186 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75151 # number of writebacks +system.l2c.writebacks::total 75151 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2379 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 23009 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4597 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 24998 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 54983 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 20985 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 17224 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 38209 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2379 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 43994 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4597 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 42222 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 93192 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2379 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 43994 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4597 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 42222 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 93192 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 126107876 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 763949732 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 257885507 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 814738055 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1962681170 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 276009 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 276009 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 714531723 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1069638349 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1784170072 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 126107876 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1478481455 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 257885507 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1884376404 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3746851242 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 126107876 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1478481455 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 257885507 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1884376404 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3746851242 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269571500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 330624500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 600196000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 336395500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 405229500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 741625000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605967000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 735854000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1341821000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018404 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.215812 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015319 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093648 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.026900 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.433556 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.203593 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.126245 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.283799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.120108 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.039713 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018404 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.283799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.120108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.039713 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33202.213569 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32592.129570 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 35696.145536 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23000.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23000.750000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34049.641315 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62101.622678 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46695.021382 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33606.433946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53008.775116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33606.433946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 56098.652817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44630.202359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40205.717680 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +494,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255479 # Cycle average of tags in use +system.iocache.tagsinuse 1.255752 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693875860000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255479 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1693877946000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255752 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4305944082 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4305944082 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4315122080 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4315122080 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4315122080 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4315122080 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4282592586 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4282592586 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4291770584 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4291770584 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4291770584 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4291770584 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -536,17 +536,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103627.841789 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103627.841789 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103418.144518 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103418.144518 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103065.859309 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103065.859309 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 102858.492127 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 102858.492127 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 114365 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.414807 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16837 system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433481639 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3433481639 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3439070888 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3439070888 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3439070888 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3439070888 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3410139151 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3410139151 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3415728400 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3415728400 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3415728400 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3415728400 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204763.933624 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204763.933624 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203371.848223 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203371.848223 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4874109 # DTB read hits -system.cpu0.dtb.read_misses 5989 # DTB read misses -system.cpu0.dtb.read_acv 118 # DTB read access violations -system.cpu0.dtb.read_accesses 427176 # DTB read accesses -system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.read_hits 4882466 # DTB read hits +system.cpu0.dtb.read_misses 6004 # DTB read misses +system.cpu0.dtb.read_acv 119 # DTB read access violations +system.cpu0.dtb.read_accesses 427336 # DTB read accesses +system.cpu0.dtb.write_hits 3509197 # DTB write hits system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162885 # DTB write accesses -system.cpu0.dtb.data_hits 8374834 # DTB hits -system.cpu0.dtb.data_misses 6650 # DTB misses -system.cpu0.dtb.data_acv 200 # DTB access violations -system.cpu0.dtb.data_accesses 590061 # DTB accesses -system.cpu0.itb.fetch_hits 2743092 # ITB hits -system.cpu0.itb.fetch_misses 2995 # ITB misses -system.cpu0.itb.fetch_acv 98 # ITB acv -system.cpu0.itb.fetch_accesses 2746087 # ITB accesses +system.cpu0.dtb.write_accesses 162892 # DTB write accesses +system.cpu0.dtb.data_hits 8391663 # DTB hits +system.cpu0.dtb.data_misses 6665 # DTB misses +system.cpu0.dtb.data_acv 201 # DTB access violations +system.cpu0.dtb.data_accesses 590228 # DTB accesses +system.cpu0.itb.fetch_hits 2746663 # ITB hits +system.cpu0.itb.fetch_misses 2999 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2749662 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928539725 # number of cpu cycles simulated +system.cpu0.numCycles 928532780 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32518253 # Number of instructions committed -system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses -system.cpu0.num_func_calls 808172 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30397519 # number of integer instructions -system.cpu0.num_fp_insts 168035 # number of float instructions -system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written -system.cpu0.num_mem_refs 8404498 # number of memory refs -system.cpu0.num_load_insts 4895120 # Number of load instructions -system.cpu0.num_store_insts 3509378 # Number of store instructions -system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles -system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles -system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles +system.cpu0.committedInsts 33005928 # Number of instructions committed +system.cpu0.committedOps 33005928 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30880412 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168592 # Number of float alu accesses +system.cpu0.num_func_calls 809679 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4456286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30880412 # number of integer instructions +system.cpu0.num_fp_insts 168592 # number of float instructions +system.cpu0.num_int_register_reads 43182890 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22546428 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87049 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88627 # number of times the floating registers were written +system.cpu0.num_mem_refs 8421419 # number of memory refs +system.cpu0.num_load_insts 4903545 # Number of load instructions +system.cpu0.num_store_insts 3517874 # Number of store instructions +system.cpu0.num_idle_cycles 214028071508.499786 # Number of idle cycles +system.cpu0.num_busy_cycles -213099538728.499786 # Number of busy cycles +system.cpu0.not_idle_fraction -229.501363 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.501363 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818570193000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39079500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22747610500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841721945500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -709,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -721,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.callpal::total 192207 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29799200000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2569954000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809352787000 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -767,372 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953667 # number of replacements -system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use -system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10246755000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.638706 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 78.351576 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 177.207261 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499294 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.153030 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.346108 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998433 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32003051 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7743805 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2284690 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42031546 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32003051 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7743805 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2284690 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42031546 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32003051 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7743805 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2284690 # number of overall hits -system.cpu0.icache.overall_hits::total 42031546 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 522052 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129070 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320206 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 971328 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 522052 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129070 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320206 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 971328 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 522052 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129070 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320206 # number of overall misses -system.cpu0.icache.overall_misses::total 971328 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813664500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4475771482 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6289435982 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813664500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4475771482 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6289435982 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813664500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4475771482 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6289435982 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32525103 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7872875 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2604896 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43002874 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32525103 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7872875 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2604896 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43002874 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022588 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016051 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016394 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122925 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022588 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14051.789727 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.787680 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6475.089755 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6475.089755 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6475.089755 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4631 # number of cycles access was blocked +system.cpu0.icache.replacements 952928 # number of replacements +system.cpu0.icache.tagsinuse 511.202677 # Cycle average of tags in use +system.cpu0.icache.total_refs 42504111 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 953439 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.579791 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 252.529954 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 82.679092 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 175.993631 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.493223 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.161483 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.343738 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32488547 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7734067 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2281497 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42504111 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32488547 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7734067 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2281497 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42504111 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32488547 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7734067 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2281497 # number of overall hits +system.cpu0.icache.overall_hits::total 42504111 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 524247 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129266 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 316688 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 970201 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 524247 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129266 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 316688 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 970201 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 524247 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129266 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 316688 # number of overall misses +system.cpu0.icache.overall_misses::total 970201 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820027500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4433734984 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6253762484 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1820027500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4433734984 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6253762484 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1820027500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4433734984 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6253762484 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 33012794 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863333 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2598185 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43474312 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 33012794 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7863333 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2598185 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43474312 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 33012794 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7863333 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2598185 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43474312 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015880 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016439 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121888 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015880 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016439 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121888 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015880 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016439 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121888 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14079.707734 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14000.325191 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6445.842134 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6445.842134 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6445.842134 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6047 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 184 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 177 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.168478 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.163842 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16976 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16976 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16976 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16976 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16976 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16976 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129070 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303230 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 432300 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 129070 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 303230 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 432300 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 129070 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 303230 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 432300 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1555524500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3682492984 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5238017484 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1555524500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3682492984 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5238017484 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1555524500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3682492984 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5238017484 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010053 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010053 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016394 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116408 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010053 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12116.626149 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12051.789727 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12144.223804 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12116.626149 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16592 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16592 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16592 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16592 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16592 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16592 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129266 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 300096 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 429362 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129266 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 300096 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 429362 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129266 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 300096 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 429362 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1561495500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3655561484 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5217056984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1561495500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3655561484 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5217056984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1561495500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3655561484 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5217056984 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009876 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016439 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115502 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009876 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.718936 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12079.707734 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12181.306928 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.718936 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1392556 # number of replacements -system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13323345 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1393068 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.564031 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1392518 # number of replacements +system.cpu0.dcache.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13324693 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1393030 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.565259 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 246.086905 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 89.137504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 176.773408 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.480638 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.174097 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.345261 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 242.082942 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 91.912647 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 178.002223 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.472818 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.179517 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.347661 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4052041 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1098209 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2416271 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7566521 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3204724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 859151 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1309317 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5373192 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116570 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19297 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48424 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184291 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125555 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21359 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52366 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7256765 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1957360 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3725588 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12939713 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7256765 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1957360 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3725588 # number of overall hits -system.cpu0.dcache.overall_hits::total 12939713 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 706812 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 104504 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 547702 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1359018 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169385 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 48063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 561193 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 778641 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9545 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2193 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7060 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18798 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4059783 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1097740 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2407711 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7565234 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3212644 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 860147 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1303129 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5375920 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116773 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19259 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48170 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184202 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125878 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21341 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52053 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199272 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7272427 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1957887 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3710840 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12941154 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7272427 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1957887 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3710840 # number of overall hits +system.cpu0.dcache.overall_hits::total 12941154 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 707193 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 104402 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 546003 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1357598 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169666 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 48403 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 557126 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 775195 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9666 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2214 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6955 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18835 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 876197 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 152567 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1108895 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2137659 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 876197 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 152567 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1108895 # number of overall misses -system.cpu0.dcache.overall_misses::total 2137659 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2184733000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9442098000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11626831000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1395266000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14749790240 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16145056240 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29363000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105564500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 134927500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 876859 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 152805 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1103129 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2132793 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 876859 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 152805 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1103129 # number of overall misses +system.cpu0.dcache.overall_misses::total 2132793 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2177012500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9421187500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11598200000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393651000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14650982812 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16044633812 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29146500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103568500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 132715000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3579999000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 24191888240 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27771887240 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3579999000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 24191888240 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27771887240 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4758853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202713 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2963973 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8925539 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3374109 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 907214 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1870510 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151833 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126115 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21490 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55484 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203089 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125555 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21359 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52367 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8132962 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2109927 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4834483 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15077372 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8132962 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2109927 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4834483 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15077372 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148526 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086890 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184786 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152262 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050201 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.052979 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300021 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.126571 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075685 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102047 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.127244 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092560 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu1.data 3570663500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 24072170312 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27642833812 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3570663500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 24072170312 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27642833812 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4766976 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1202142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2953714 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8922832 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3382310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 908550 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1860255 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6151115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126439 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21473 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55125 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203037 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125878 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21341 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52054 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199273 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8149286 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2110692 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4813969 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15073947 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8149286 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2110692 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4813969 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15073947 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148353 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086847 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184853 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152149 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050163 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053275 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.299489 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.126025 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076448 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103106 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.126168 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092766 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107734 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072309 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229372 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.141779 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107734 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072309 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229372 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.141779 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20905.735666 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17239.480593 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8555.317884 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29029.939871 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26282.919138 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20734.916656 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13389.420885 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14952.478754 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7177.758272 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107599 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072396 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229152 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.141489 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107599 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072396 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229152 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.141489 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20852.210686 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17254.827354 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8543.176993 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28792.657480 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26297.431482 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20697.545536 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13164.634146 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14891.229331 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7046.190603 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12991.729382 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23465.094024 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21816.211851 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12991.729382 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 421766 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 16882 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12960.861092 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23367.451981 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21821.718323 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12960.861092 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 423654 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2998 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 16794 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.983177 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 82.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.226509 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 428.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836280 # number of writebacks -system.cpu0.dcache.writebacks::total 836280 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 761827 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 761827 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 761827 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 761827 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104504 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262049 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 366553 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85019 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133082 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 836151 # number of writebacks +system.cpu0.dcache.writebacks::total 836151 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 284315 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 284315 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 472764 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 472764 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1457 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 757079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 757079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 757079 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 757079 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104402 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261688 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366090 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48403 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84362 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 132765 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2214 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7712 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 346050 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 498855 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152805 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 346050 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 498855 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1968208500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4300121500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6268330000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1296845000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131428631 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3428273631 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24718500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69834500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94553000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3265053500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6431550131 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9696603631 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3265053500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6431550131 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9696603631 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287785000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353197500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 640982500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356424500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221793 # DTB read hits -system.cpu1.dtb.read_misses 1550 # DTB read misses -system.cpu1.dtb.read_acv 45 # DTB read access violations -system.cpu1.dtb.read_accesses 143987 # DTB read accesses -system.cpu1.dtb.write_hits 928954 # DTB write hits -system.cpu1.dtb.write_misses 206 # DTB write misses +system.cpu1.dtb.read_hits 1221293 # DTB read hits +system.cpu1.dtb.read_misses 1489 # DTB read misses +system.cpu1.dtb.read_acv 40 # DTB read access violations +system.cpu1.dtb.read_accesses 143781 # DTB read accesses +system.cpu1.dtb.write_hits 930282 # DTB write hits +system.cpu1.dtb.write_misses 202 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60098 # DTB write accesses -system.cpu1.dtb.data_hits 2150747 # DTB hits -system.cpu1.dtb.data_misses 1756 # DTB misses -system.cpu1.dtb.data_acv 69 # DTB access violations -system.cpu1.dtb.data_accesses 204085 # DTB accesses -system.cpu1.itb.fetch_hits 875028 # ITB hits -system.cpu1.itb.fetch_misses 772 # ITB misses -system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875800 # ITB accesses +system.cpu1.dtb.write_accesses 59266 # DTB write accesses +system.cpu1.dtb.data_hits 2151575 # DTB hits +system.cpu1.dtb.data_misses 1691 # DTB misses +system.cpu1.dtb.data_acv 64 # DTB access violations +system.cpu1.dtb.data_accesses 203047 # DTB accesses +system.cpu1.itb.fetch_hits 872259 # ITB hits +system.cpu1.itb.fetch_misses 756 # ITB misses +system.cpu1.itb.fetch_acv 43 # ITB acv +system.cpu1.itb.fetch_accesses 873015 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953543873 # number of cpu cycles simulated +system.cpu1.numCycles 953618286 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7871049 # Number of instructions committed -system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses -system.cpu1.num_func_calls 212361 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7322486 # number of integer instructions -system.cpu1.num_fp_insts 45486 # number of float instructions -system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written -system.cpu1.num_mem_refs 2158619 # number of memory refs -system.cpu1.num_load_insts 1227197 # Number of load instructions -system.cpu1.num_store_insts 931422 # Number of store instructions -system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles -system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles -system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles +system.cpu1.committedInsts 7861577 # Number of instructions committed +system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses +system.cpu1.num_func_calls 212083 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7312995 # number of integer instructions +system.cpu1.num_fp_insts 45507 # number of float instructions +system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written +system.cpu1.num_mem_refs 2159267 # number of memory refs +system.cpu1.num_load_insts 1226545 # Number of load instructions +system.cpu1.num_store_insts 932722 # Number of store instructions +system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles +system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles +system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8388883 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits +system.cpu2.branchPred.lookups 8378030 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3222753 # DTB read hits -system.cpu2.dtb.read_misses 11767 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 216394 # DTB read accesses -system.cpu2.dtb.write_hits 1997746 # DTB write hits -system.cpu2.dtb.write_misses 2597 # DTB write misses -system.cpu2.dtb.write_acv 133 # DTB write access violations -system.cpu2.dtb.write_accesses 81219 # DTB write accesses -system.cpu2.dtb.data_hits 5220499 # DTB hits -system.cpu2.dtb.data_misses 14364 # DTB misses -system.cpu2.dtb.data_acv 247 # DTB access violations -system.cpu2.dtb.data_accesses 297613 # DTB accesses -system.cpu2.itb.fetch_hits 371919 # ITB hits -system.cpu2.itb.fetch_misses 5650 # ITB misses -system.cpu2.itb.fetch_acv 270 # ITB acv -system.cpu2.itb.fetch_accesses 377569 # ITB accesses +system.cpu2.dtb.read_hits 3213070 # DTB read hits +system.cpu2.dtb.read_misses 11858 # DTB read misses +system.cpu2.dtb.read_acv 125 # DTB read access violations +system.cpu2.dtb.read_accesses 216838 # DTB read accesses +system.cpu2.dtb.write_hits 1985729 # DTB write hits +system.cpu2.dtb.write_misses 2626 # DTB write misses +system.cpu2.dtb.write_acv 132 # DTB write access violations +system.cpu2.dtb.write_accesses 82100 # DTB write accesses +system.cpu2.dtb.data_hits 5198799 # DTB hits +system.cpu2.dtb.data_misses 14484 # DTB misses +system.cpu2.dtb.data_acv 257 # DTB access violations +system.cpu2.dtb.data_accesses 298938 # DTB accesses +system.cpu2.itb.fetch_hits 371799 # ITB hits +system.cpu2.itb.fetch_misses 5527 # ITB misses +system.cpu2.itb.fetch_acv 268 # ITB acv +system.cpu2.itb.fetch_accesses 377326 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,270 +1255,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30487191 # number of cpu cycles simulated +system.cpu2.numCycles 30456501 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued -system.cpu2.iq.rate 0.995088 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued +system.cpu2.iq.rate 0.994264 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1285615 # number of nop insts executed -system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6797242 # Number of branches executed -system.cpu2.iew.exec_stores 2004831 # Number of stores executed -system.cpu2.iew.exec_rate 0.989710 # Inst execution rate -system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17352028 # num instructions producing a value -system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value +system.cpu2.iew.exec_nop 1279986 # number of nop insts executed +system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6791959 # Number of branches executed +system.cpu2.iew.exec_stores 1992832 # Number of stores executed +system.cpu2.iew.exec_rate 0.989003 # Inst execution rate +system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17325737 # num instructions producing a value +system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30289973 # Number of instructions committed -system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30241196 # Number of instructions committed +system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4894371 # Number of memory references committed -system.cpu2.commit.loads 2968099 # Number of loads committed -system.cpu2.commit.membars 65019 # Number of memory barriers committed -system.cpu2.commit.branches 6647353 # Number of branches committed -system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. -system.cpu2.commit.function_calls 231619 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4874767 # Number of memory references committed +system.cpu2.commit.loads 2959021 # Number of loads committed +system.cpu2.commit.membars 64729 # Number of memory barriers committed +system.cpu2.commit.branches 6642526 # Number of branches committed +system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions. +system.cpu2.commit.function_calls 230913 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58337288 # The number of ROB reads -system.cpu2.rob.rob_writes 65718838 # The number of ROB writes -system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29114232 # Number of Instructions Simulated -system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated -system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads -system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads -system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes +system.cpu2.rob.rob_reads 58235962 # The number of ROB reads +system.cpu2.rob.rob_writes 65598028 # The number of ROB writes +system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29069459 # Number of Instructions Simulated +system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated +system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads +system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index c2660d718..94883ba6e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index b7a2e0ce5..9c29c3bb4 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -11,24 +11,23 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5720641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5728757500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5763076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5777835500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6298513500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5695245000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5701912500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5710381500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5745167500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5760086500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6281852500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 52553050000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 2291164927000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 52533955500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2291148077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2497502713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2498707539500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2520262039500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2525942762500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2526449392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2527008451000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2527009567500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2527556775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 2483713797000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2498675085000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2519713161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2520226805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2525908166000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2526415429500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2526974192500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2526975291500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 444ce680b..385305309 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 25 2013 18:24:48 -gem5 started Feb 25 2013 22:59:32 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 01:26:55 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533144795000 because m5_exit instruction encountered +Exiting @ tick 2533114761500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5aca0e128..1ccf6887b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,134 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533141 # Number of seconds simulated -sim_ticks 2533140518500 # Number of ticks simulated -final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533115 # Number of seconds simulated +sim_ticks 2533114761500 # Number of ticks simulated +final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42664 # Simulator instruction rate (inst/s) -host_op_rate 54897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1792038006 # Simulator tick rate (ticks/s) -host_mem_usage 435912 # Number of bytes of host memory used -host_seconds 1413.55 # Real time elapsed on the host -sim_insts 60307702 # Number of instructions simulated -sim_ops 77599241 # Number of ops (including micro ops) simulated +host_inst_rate 19921 # Simulator instruction rate (inst/s) +host_op_rate 25633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 836738491 # Simulator tick rate (ticks/s) +host_mem_usage 439300 # Number of bytes of host memory used +host_seconds 3027.37 # Real time elapsed on the host +sim_insts 60307912 # Number of instructions simulated +sim_ops 77599507 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096807 # Total number of read requests seen -system.physmem.writeReqs 813124 # Total number of write requests seen -system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195648 # Total number of bytes read from memory -system.physmem.bytesWritten 52039936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096833 # Total number of read requests seen +system.physmem.writeReqs 813132 # Total number of write requests seen +system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966197312 # Total number of bytes read from memory +system.physmem.bytesWritten 52040448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533139407500 # Total gap between requests +system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533113625500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154563 # Categorize read packet sizes +system.physmem.readPktSize::6 154589 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59106 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59114 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1039924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -139,19 +151,19 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see @@ -162,68 +174,56 @@ system.physmem.wrQLenPdf::19 35353 # Wh system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see -system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see +system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests +system.physmem.totBusLat 75482355000 # Total cycles spent in databus access system.physmem.totBankLat 16909241250 # Total cycles spent in bank access -system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgQLat 26046.04 # Average queueing delay per request system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32164.85 # Average memory access latency -system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 32166.12 # Average memory access latency +system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.32 # Average write queue length over time -system.physmem.readRowHits 15020284 # Number of row buffer hits during reads -system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.50 # Average write queue length over time +system.physmem.readRowHits 15020252 # Number of row buffer hits during reads +system.physmem.writeRowHits 793086 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes -system.physmem.avgGap 159217.50 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159215.54 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14656582 # Number of BP lookups -system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits +system.cpu.branchPred.lookups 14667150 # Number of BP lookups +system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987438 # DTB read hits +system.cpu.checker.dtb.read_hits 14987498 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227743 # DTB write hits +system.cpu.checker.dtb.write_hits 11227787 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -234,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994740 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229932 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994800 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229976 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215181 # DTB hits +system.cpu.checker.dtb.hits 26215285 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224672 # DTB accesses -system.cpu.checker.itb.inst_hits 61481703 # ITB inst hits +system.cpu.checker.dtb.accesses 26224776 # DTB accesses +system.cpu.checker.itb.inst_hits 61481914 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486174 # ITB inst accesses -system.cpu.checker.itb.hits 61481703 # DTB hits +system.cpu.checker.itb.inst_accesses 61486385 # ITB inst accesses +system.cpu.checker.itb.hits 61481914 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486174 # DTB accesses -system.cpu.checker.numCycles 77885049 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486385 # DTB accesses +system.cpu.checker.numCycles 77885316 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51396633 # DTB read hits -system.cpu.dtb.read_misses 64067 # DTB read misses -system.cpu.dtb.write_hits 11699653 # DTB write hits -system.cpu.dtb.write_misses 15746 # DTB write misses +system.cpu.dtb.read_hits 51396830 # DTB read hits +system.cpu.dtb.read_misses 64077 # DTB read misses +system.cpu.dtb.write_hits 11700143 # DTB write hits +system.cpu.dtb.write_misses 15896 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51460700 # DTB read accesses -system.cpu.dtb.write_accesses 11715399 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460907 # DTB read accesses +system.cpu.dtb.write_accesses 11716039 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096286 # DTB hits -system.cpu.dtb.misses 79813 # DTB misses -system.cpu.dtb.accesses 63176099 # DTB accesses -system.cpu.itb.inst_hits 12325480 # ITB inst hits -system.cpu.itb.inst_misses 11172 # ITB inst misses +system.cpu.dtb.hits 63096973 # DTB hits +system.cpu.dtb.misses 79973 # DTB misses +system.cpu.dtb.accesses 63176946 # DTB accesses +system.cpu.itb.inst_hits 12326910 # ITB inst hits +system.cpu.itb.inst_misses 11389 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,518 +295,518 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4964 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12336652 # ITB inst accesses -system.cpu.itb.hits 12325480 # DTB hits -system.cpu.itb.misses 11172 # DTB misses -system.cpu.itb.accesses 12336652 # DTB accesses -system.cpu.numCycles 471810648 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12338299 # ITB inst accesses +system.cpu.itb.hits 12326910 # DTB hits +system.cpu.itb.misses 11389 # DTB misses +system.cpu.itb.accesses 12338299 # DTB accesses +system.cpu.numCycles 471812928 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535276 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued -system.cpu.iq.rate 0.263438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued +system.cpu.iq.rate 0.263458 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221429 # number of nop insts executed -system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed -system.cpu.iew.exec_branches 11545908 # Number of branches executed -system.cpu.iew.exec_stores 12211356 # Number of stores executed -system.cpu.iew.exec_rate 0.257527 # Inst execution rate -system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47220023 # num instructions producing a value -system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value +system.cpu.iew.exec_nop 221256 # number of nop insts executed +system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed +system.cpu.iew.exec_branches 11548935 # Number of branches executed +system.cpu.iew.exec_stores 12211863 # Number of stores executed +system.cpu.iew.exec_rate 0.257542 # Inst execution rate +system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47248906 # num instructions producing a value +system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458083 # Number of instructions committed -system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147854976 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458293 # Number of instructions committed +system.cpu.commit.committedOps 77749888 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386631 # Number of memory references committed -system.cpu.commit.loads 15654552 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961338 # Number of branches committed +system.cpu.commit.refs 27386737 # Number of memory references committed +system.cpu.commit.loads 15654612 # Number of loads committed +system.cpu.commit.membars 403603 # Number of memory barriers committed +system.cpu.commit.branches 9961369 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854854 # Number of committed integer instructions. -system.cpu.commit.function_calls 991262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855092 # Number of committed integer instructions. +system.cpu.commit.function_calls 991267 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2901187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242306963 # The number of ROB reads -system.cpu.rob.rob_writes 201917005 # The number of ROB writes -system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307702 # Number of Instructions Simulated -system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated -system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 242290263 # The number of ROB reads +system.cpu.rob.rob_writes 201932483 # The number of ROB writes +system.cpu.timesIdled 1770811 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320491858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594333550 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307912 # Number of Instructions Simulated +system.cpu.committedOps 77599507 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307912 # Number of Instructions Simulated +system.cpu.cpi 7.823400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823400 # CPI: Total CPI of All Threads system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550141266 # number of integer regfile reads -system.cpu.int_regfile_writes 88418140 # number of integer regfile writes -system.cpu.fp_regfile_reads 8398 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979850 # number of replacements -system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use -system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits -system.cpu.icache.overall_hits::total 11261998 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses -system.cpu.icache.overall_misses::total 1059902 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.int_regfile_reads 550176561 # number of integer regfile reads +system.cpu.int_regfile_writes 88426578 # number of integer regfile writes +system.cpu.fp_regfile_reads 8298 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 30118912 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980182 # number of replacements +system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use +system.cpu.icache.total_refs 11263184 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980694 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.484912 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.616610 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11263184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11263184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11263184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11263184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11263184 # number of overall hits +system.cpu.icache.overall_hits::total 11263184 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060219 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060219 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060219 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060219 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060219 # number of overall misses +system.cpu.icache.overall_misses::total 1060219 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14018220995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14018220995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14018220995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14018220995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14018220995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14018220995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12323403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12323403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12323403 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12323403 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12323403 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12323403 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086033 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086033 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086033 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086033 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086033 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13222.005072 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13222.005072 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13222.005072 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13222.005072 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4586 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.286667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79506 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79506 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79506 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79506 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79506 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79506 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980396 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980396 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980396 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980396 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980396 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980396 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379943495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11379943495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379943495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11379943495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379943495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79489 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79489 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79489 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79489 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79489 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79489 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980730 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980730 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980730 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980730 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980730 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980730 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11392389495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11392389495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11392389495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11392389495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11392389495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11392389495 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079565 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079583 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079583 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079583 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11616.234331 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11616.234331 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64334 # number of replacements -system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003890 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8157.503084 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6228.405939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64360 # number of replacements +system.cpu.l2cache.tagsinuse 51336.859008 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885213 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129758 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.528684 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2523139048000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36935.695243 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 23.234452 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003892 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8162.031134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6215.894286 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563594 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000355 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124474 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783491 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416202 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607769 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607769 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112939 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112939 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500020 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529141 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10206 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966908 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500020 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529141 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094847 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783338 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52172 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967239 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 386976 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416862 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607588 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607588 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112931 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112931 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52172 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967239 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499907 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529793 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52172 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10475 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967239 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499907 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529793 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 36 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12331 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23084 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10700 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133206 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133206 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 36 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12331 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12355 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143906 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156300 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 36 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12331 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143895 # number of overall misses -system.cpu.l2cache.overall_misses::total 156270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2874000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 694978000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 630766499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1328805499 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 455500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732631500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6732631500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2874000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 694978000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7363397999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8061436999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2874000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 694978000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7363397999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8061436999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979239 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1439286 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52048 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10209 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643915 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1685411 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52048 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10209 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1685411 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000788 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012592 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016039 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986815 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986815 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541132 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541132 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000788 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012592 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223469 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092719 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000788 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012592 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223469 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092719 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70097.560976 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56360.230314 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58900.597535 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57563.918688 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 156.046591 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 156.046591 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50550.594657 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50550.594657 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51586.593710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51586.593710 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12355 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143906 # number of overall misses +system.cpu.l2cache.overall_misses::total 156300 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 186500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 703826000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 629251500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1335748000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 410500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6753390000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6753390000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 186500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 703826000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7382641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8089138000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 186500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 703826000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7382641500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8089138000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52208 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10478 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979594 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397676 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439956 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607588 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607588 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52208 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10478 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979594 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643813 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686093 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52208 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10478 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979594 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643813 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686093 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000690 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000286 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016038 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985820 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985820 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541186 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541186 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000690 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223521 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092700 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000690 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223521 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092700 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62166.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56966.895994 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58808.551402 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57839.612020 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.582192 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.582192 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50698.842394 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50698.842394 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51753.921945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51753.921945 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,109 +815,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59106 # number of writebacks -system.cpu.l2cache.writebacks::total 59106 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59114 # number of writebacks +system.cpu.l2cache.writebacks::total 59114 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 36 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12319 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10648 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23011 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2919 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2919 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23022 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133206 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133206 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 36 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143834 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156197 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 36 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12319 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143834 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156197 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2360290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2033785 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541016289 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 495761741 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1039287822 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29192919 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29192919 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 549600048 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 494356239 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1046139574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072671631 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072671631 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2360290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5093264625 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5093264625 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2033785 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549600048 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587620864 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6139404199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2033785 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549600048 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587620864 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6139404199 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002364267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007445097 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26884342911 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26884342911 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193891788008 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026755 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985820 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985820 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541186 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541186 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44527.266305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.052538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45440.864130 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38236.000068 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38236.000068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643403 # number of replacements +system.cpu.dcache.replacements 643301 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.total_refs 21506564 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643813 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.404986 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits -system.cpu.dcache.overall_hits::total 21013434 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737092 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737092 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962848 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962848 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13493 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13493 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses -system.cpu.dcache.overall_misses::total 3699940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13753913 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753913 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259030 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242896 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242896 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247606 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247606 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012943 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012943 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012943 # number of overall hits +system.cpu.dcache.overall_hits::total 21012943 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737130 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963360 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963360 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13521 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13521 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700490 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700490 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700490 # number of overall misses +system.cpu.dcache.overall_misses::total 3700490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9747104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9747104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104655662232 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104655662232 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180718000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180718000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114402766232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114402766232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114402766232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114402766232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491043 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491043 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222390 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222390 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256417 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256417 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713433 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713433 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713433 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713433 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050868 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050868 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289889 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289889 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30915.572325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30915.572325 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18747 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2620 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.825573 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 74.689243 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks -system.cpu.dcache.writebacks::total 607769 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607588 # number of writebacks +system.cpu.dcache.writebacks::total 607588 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714338 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714338 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065882 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065882 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385586 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385586 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12167 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12167 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634608 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8203666916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8203666916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141299500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141299500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13006963416 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13006963416 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13006963416 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13006963416 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36699724336 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36699724336 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 053c6a286..7b8c607e4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 8d856e1ed..8073ce535 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 25 2013 18:24:48 -gem5 started Feb 25 2013 23:05:46 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:41:12 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1102934903000 because m5_exit instruction encountered +Exiting @ tick 2602778916500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ee857cd58..5f98a27d9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102937 # Number of seconds simulated -sim_ticks 1102936899000 # Number of ticks simulated -final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.602779 # Number of seconds simulated +sim_ticks 2602778916500 # Number of ticks simulated +final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56405 # Simulator instruction rate (inst/s) -host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010130266 # Simulator tick rate (ticks/s) -host_mem_usage 440004 # Number of bytes of host memory used -host_seconds 1091.88 # Real time elapsed on the host -sim_insts 61587196 # Number of instructions simulated -sim_ops 79280303 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +host_inst_rate 24161 # Simulator instruction rate (inst/s) +host_op_rate 31106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1001764915 # Simulator tick rate (ticks/s) +host_mem_usage 444424 # Number of bytes of host memory used +host_seconds 2598.19 # Real time elapsed on the host +sim_insts 62774383 # Number of instructions simulated +sim_ops 80820330 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4382196 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory -system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 426624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5245232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131562340 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4273600 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7302736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68544 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81983 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302224 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66775 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257533 # Total number of read requests seen -system.physmem.writeReqs 823123 # Total number of write requests seen -system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400482112 # Total number of bytes read from memory -system.physmem.bytesWritten 52679872 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824059 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46531239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1683660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2015243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50546875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163911 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1641937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1157277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2805746 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1641937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46531239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1690192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3172520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53352621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302224 # Total number of read requests seen +system.physmem.writeReqs 824059 # Total number of write requests seen +system.physmem.cpureqs 244149 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979342336 # Total number of bytes read from memory +system.physmem.bytesWritten 52739776 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131562340 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7302736 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 337 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14071 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 956452 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50985 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51782 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51930 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102935703000 # Total gap between requests +system.physmem.numWrRetry 32645 # Number of times wr buffer was full causing retry +system.physmem.totGap 2602777722500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes +system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162580 # Categorize read packet sizes +system.physmem.readPktSize::6 163303 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::2 757284 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66287 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66775 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1059619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3596573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2710922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2723432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2682017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 62131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 159682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,322 +178,304 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see -system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests -system.physmem.totBusLat 31287030000 # Total cycles spent in databus access -system.physmem.totBankLat 8542957500 # Total cycles spent in bank access -system.physmem.avgQLat 31847.29 # Average queueing delay per request -system.physmem.avgBankLat 1365.26 # Average bank access latency per request +system.physmem.wrQLenPdf::4 3062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32658 # What write queue length does an incoming req see +system.physmem.totQLat 398163291750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 491955679250 # Sum of mem lat for all requests +system.physmem.totBusLat 76509435000 # Total cycles spent in databus access +system.physmem.totBankLat 17282952500 # Total cycles spent in bank access +system.physmem.avgQLat 26020.54 # Average queueing delay per request +system.physmem.avgBankLat 1129.47 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38212.55 # Average memory access latency -system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 32150.00 # Average memory access latency +system.physmem.avgRdBW 376.27 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.55 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 11.59 # Average write queue length over time -system.physmem.readRowHits 6213376 # Number of row buffer hits during reads -system.physmem.writeRowHits 799550 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.56 # Average write queue length over time +system.physmem.readRowHits 15222567 # Number of row buffer hits during reads +system.physmem.writeRowHits 800487 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes -system.physmem.avgGap 155767.45 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72282 # number of replacements -system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use -system.l2c.total_refs 1841477 # Total number of references to valid blocks. -system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. +system.physmem.avgGap 161399.73 # Average gap between requests +system.l2c.replacements 73011 # number of replacements +system.l2c.tagsinuse 53067.424425 # Cycle average of tags in use +system.l2c.total_refs 1872250 # Total number of references to valid blocks. +system.l2c.sampled_refs 138181 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.549258 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3804.384047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600767 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061085 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043038 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056839 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058050 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820073 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22824 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4741 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386299 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 167150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5232 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197825 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1404314 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581284 # number of Writeback hits -system.l2c.Writeback_hits::total 581284 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1196 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 780 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1976 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48442 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58735 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107177 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22824 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4741 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386299 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 215592 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30426 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5232 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256560 # number of demand (read+write) hits -system.l2c.demand_hits::total 1511491 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22824 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4741 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386299 # number of overall hits -system.l2c.overall_hits::cpu0.data 215592 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30426 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5232 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589817 # number of overall hits -system.l2c.overall_hits::cpu1.data 256560 # number of overall hits -system.l2c.overall_hits::total 1511491 # number of overall hits +system.l2c.occ_blocks::writebacks 37745.757624 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.485079 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4193.697813 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2948.995369 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 14.004673 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.955179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4039.578813 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4118.949534 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575955 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.063991 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.044998 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061639 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062850 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809745 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 23032 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 392957 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 32830 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5777 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 607042 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201661 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1433502 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 582954 # number of Writeback hits +system.l2c.Writeback_hits::total 582954 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1024 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 725 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1749 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47437 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59291 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106728 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 23032 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 392957 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 213148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 32830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5777 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 607042 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260952 # number of demand (read+write) hits +system.l2c.demand_hits::total 1540230 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 23032 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4492 # number of overall hits +system.l2c.overall_hits::cpu0.inst 392957 # number of overall hits +system.l2c.overall_hits::cpu0.data 213148 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 32830 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5777 # number of overall hits +system.l2c.overall_hits::cpu1.inst 607042 # number of overall hits +system.l2c.overall_hits::cpu1.data 260952 # number of overall hits +system.l2c.overall_hits::total 1540230 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6269 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6424 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6061 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6334 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6316 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6288 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25333 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5101 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8883 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63146 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76636 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139782 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6630 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6368 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25427 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5641 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4355 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9996 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 765 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 590 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1355 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140503 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6269 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69570 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6061 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69960 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6316 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 82924 # number of demand (read+write) misses -system.l2c.demand_misses::total 165115 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6630 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83245 # number of demand (read+write) misses +system.l2c.demand_misses::total 165930 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6269 # number of overall misses -system.l2c.overall_misses::cpu0.data 69570 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6061 # number of overall misses +system.l2c.overall_misses::cpu0.data 69960 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6316 # number of overall misses -system.l2c.overall_misses::cpu1.data 82924 # number of overall misses -system.l2c.overall_misses::total 165115 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 933000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 347054000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 368774499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1319000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6630 # number of overall misses +system.l2c.overall_misses::cpu1.data 83245 # number of overall misses +system.l2c.overall_misses::total 165930 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 934000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 341015500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 362076499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1414500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 385195500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 391956499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1495556498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8608988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11814499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20423487 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3438000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3130357988 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4120844492 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7251202480 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 933000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 347054000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3499132487 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1319000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 395474000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 399545499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1500646498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8933491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12111000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21044491 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 544500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3029499 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3573999 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3156158498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4120290994 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7276449492 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 934000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 341015500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3518234997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1414500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 385195500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4512800991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8746758978 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 933000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 347054000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3499132487 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1319000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 395474000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4519836493 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8777095990 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 934000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 341015500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3518234997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1414500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 385195500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4512800991 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8746758978 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22838 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173574 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30443 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5233 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204113 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1429647 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581284 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581284 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6297 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4562 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10859 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1402 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111588 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135371 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246959 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22838 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 285162 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30443 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5233 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596133 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339484 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1676606 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22838 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 285162 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30443 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5233 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596133 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339484 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1676606 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000843 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015969 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037010 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010595 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017720 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.810068 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829022 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818031 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764497 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737882 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.753923 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.565885 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.566118 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566013 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000843 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015969 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.243967 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010595 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244265 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098482 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000843 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015969 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.243967 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010595 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244265 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098482 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55360.344553 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57405.743929 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 395474000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4519836493 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8777095990 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 23046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4494 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 399018 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172045 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 32847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5778 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 613672 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 208029 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458929 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 582954 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 582954 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6665 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5080 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11745 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 972 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 750 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111063 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 136168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247231 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 23046 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4494 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 399018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 283108 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 32847 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5778 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 613672 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 344197 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1706160 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 23046 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4494 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 399018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 283108 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 32847 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5778 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 613672 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 344197 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1706160 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000445 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015190 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000173 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010804 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030611 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017429 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846362 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.857283 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.851086 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787037 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.786876 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.572882 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.564575 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568307 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000445 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.247114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000173 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010804 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241853 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097253 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000445 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.247114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000173 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010804 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241853 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097253 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 56263.900346 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57163.956268 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60987.254592 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62334.048823 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59035.901709 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1687.705940 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3123.875992 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2299.165485 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 915.634675 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6925.790754 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.601703 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49573.337789 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53771.654210 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51875.080339 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59649.170437 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 62742.697707 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59017.835293 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1583.671512 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2780.941447 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2105.291216 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 711.764706 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5134.744068 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2637.637638 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49604.854902 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53595.886858 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51788.570294 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 56263.900346 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50289.236664 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52973.739382 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 59649.170437 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54295.591243 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52896.377930 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 56263.900346 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50289.236664 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52973.739382 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 59649.170437 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54295.591243 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52896.377930 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,180 +484,180 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66287 # number of writebacks -system.l2c.writebacks::total 66287 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66775 # number of writebacks +system.l2c.writebacks::total 66775 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6265 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6387 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6056 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6297 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6309 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6264 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25261 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5101 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8883 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63146 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76636 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139782 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6623 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6342 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25352 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5641 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4355 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9996 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 765 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 590 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1355 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63626 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76877 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140503 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6265 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69533 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6056 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69923 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6309 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 82900 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165043 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6623 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83219 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165855 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6265 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69533 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6056 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69923 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6309 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 82900 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165043 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6623 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83219 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165855 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 760014 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268851852 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 287876545 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 265447152 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 281377954 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 306166045 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312367924 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1177390401 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51308459 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38489213 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89797672 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6525620 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4130906 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10656526 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2347754082 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3162202952 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5509957034 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 312696352 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 319251979 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1180884969 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 56679510 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44248783 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 100928293 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7679249 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5912584 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 13591833 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2367645075 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3158595985 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5526241060 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 760014 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 268851852 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2635630627 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 265447152 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2649023029 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 306166045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3474570876 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6687347435 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 312696352 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3477847964 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6707126029 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 760014 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 268851852 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2635630627 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 265447152 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2649023029 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 306166045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3474570876 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6687347435 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5300585 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408061544 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154666775744 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167082238155 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050331237 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25987896299 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 27038227536 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5300585 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458392781 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180654672043 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194120465691 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036797 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030689 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017669 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810068 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829022 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818031 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764497 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737882 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753923 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.565885 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566118 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566013 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098439 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098439 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 312696352 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3477847964 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6707126029 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5286835 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335434047 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1838032 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154945975242 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167288534156 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1114449737 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25984901303 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 27099351040 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5286835 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13449883784 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180930876545 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194387885196 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036601 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030486 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017377 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846362 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857283 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.851086 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787037 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786876 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572882 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564575 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568307 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097210 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097210 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45072.263191 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44684.445609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49867.165390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46609.017893 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10058.509900 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10176.946854 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10108.935270 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10101.578947 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.866180 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10081.859981 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37179.775156 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41262.630513 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39418.215750 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50339.321823 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46579.558575 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.776990 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.455339 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.868047 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.233987 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.328814 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10030.873063 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37211.911404 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41086.358534 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39331.836758 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6001640 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits +system.cpu0.branchPred.lookups 6065134 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4623218 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295247 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3783915 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2943990 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.802752 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 682666 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28697 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8910999 # DTB read hits -system.cpu0.dtb.read_misses 29151 # DTB read misses -system.cpu0.dtb.write_hits 5140269 # DTB write hits -system.cpu0.dtb.write_misses 5702 # DTB write misses +system.cpu0.dtb.read_hits 8964880 # DTB read hits +system.cpu0.dtb.read_misses 29505 # DTB read misses +system.cpu0.dtb.write_hits 5211507 # DTB write hits +system.cpu0.dtb.write_misses 5768 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1820 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1111 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 256 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8940150 # DTB read accesses -system.cpu0.dtb.write_accesses 5145971 # DTB write accesses +system.cpu0.dtb.perms_faults 587 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8994385 # DTB read accesses +system.cpu0.dtb.write_accesses 5217275 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051268 # DTB hits -system.cpu0.dtb.misses 34853 # DTB misses -system.cpu0.dtb.accesses 14086121 # DTB accesses -system.cpu0.itb.inst_hits 4221147 # ITB inst hits -system.cpu0.itb.inst_misses 5166 # ITB inst misses +system.cpu0.dtb.hits 14176387 # DTB hits +system.cpu0.dtb.misses 35273 # DTB misses +system.cpu0.dtb.accesses 14211660 # DTB accesses +system.cpu0.itb.inst_hits 4271941 # ITB inst hits +system.cpu0.itb.inst_misses 5082 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,534 +718,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1340 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1395 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses -system.cpu0.itb.hits 4221147 # DTB hits -system.cpu0.itb.misses 5166 # DTB misses -system.cpu0.itb.accesses 4226313 # DTB accesses -system.cpu0.numCycles 67826289 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4277023 # ITB inst accesses +system.cpu0.itb.hits 4271941 # DTB hits +system.cpu0.itb.misses 5082 # DTB misses +system.cpu0.itb.accesses 4277023 # DTB accesses +system.cpu0.numCycles 68310391 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11985780 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32442629 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6065134 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3626656 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7605462 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460769 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 62659 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21080761 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46842 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 87230 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4270468 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157226 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2109 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41924364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.999512 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.380874 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34326103 81.88% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 570380 1.36% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 823787 1.96% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686899 1.64% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 778226 1.86% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 563231 1.34% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 676382 1.61% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356953 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3142403 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41924364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088788 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.474930 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12503811 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21012915 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6898585 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 522974 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 986079 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 948336 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64663 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40543036 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 211520 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 986079 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13078116 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5721380 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13152385 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6797650 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2188754 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39433741 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1845 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 443177 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1244404 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39808870 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178177695 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178143549 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34146 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31430562 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8378307 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 419823 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 376669 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5441918 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7757618 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5774212 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139116 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1209168 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37348543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 904610 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37701629 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81879 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6330369 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13296779 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257143 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41924364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.899277 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.510411 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26590532 63.43% 63.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5818938 13.88% 77.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3210799 7.66% 84.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2498063 5.96% 90.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2114705 5.04% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 942628 2.25% 98.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502674 1.20% 99.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 189300 0.45% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56725 0.14% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41924364 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26752 2.49% 2.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 840001 78.12% 80.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208012 19.35% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22644819 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48004 0.13% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9425277 25.00% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5530613 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued -system.cpu0.iq.rate 0.549158 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37701629 # Type of FU issued +system.cpu0.iq.rate 0.551916 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1075225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028519 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118511451 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44591434 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34839098 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8242 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3868 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38720352 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4288 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316630 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1380313 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2666 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13062 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544614 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149563 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5584 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 986079 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4106132 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100687 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38371433 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85430 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7757618 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5774212 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 577195 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40897 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3001 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13062 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150158 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117749 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267907 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37323557 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9281925 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378072 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118142 # number of nop insts executed -system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4856874 # Number of branches executed -system.cpu0.iew.exec_stores 5400115 # Number of stores executed -system.cpu0.iew.exec_rate 0.543622 # Inst execution rate -system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18291021 # num instructions producing a value -system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value +system.cpu0.iew.exec_nop 118280 # number of nop insts executed +system.cpu0.iew.exec_refs 14765828 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4915455 # Number of branches executed +system.cpu0.iew.exec_stores 5483903 # Number of stores executed +system.cpu0.iew.exec_rate 0.546382 # Inst execution rate +system.cpu0.iew.wb_sent 37128467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34842966 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18565053 # num instructions producing a value +system.cpu0.iew.wb_consumers 35706535 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.510068 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519934 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6140110 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 647467 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231710 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40938285 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775989 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.737548 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29080513 71.04% 71.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5796475 14.16% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1964427 4.80% 89.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 998229 2.44% 92.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 793584 1.94% 94.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 517255 1.26% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395614 0.97% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 224138 0.55% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1168050 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23681661 # Number of instructions committed -system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40938285 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24057849 # Number of instructions committed +system.cpu0.commit.committedOps 31767677 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11429428 # Number of memory references committed -system.cpu0.commit.loads 6277820 # Number of loads committed -system.cpu0.commit.membars 229679 # Number of memory barriers committed -system.cpu0.commit.branches 4245347 # Number of branches committed +system.cpu0.commit.refs 11606903 # Number of memory references committed +system.cpu0.commit.loads 6377305 # Number of loads committed +system.cpu0.commit.membars 231785 # Number of memory barriers committed +system.cpu0.commit.branches 4305044 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489379 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28078801 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498475 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1168050 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75580359 # The number of ROB reads -system.cpu0.rob.rob_writes 75767781 # The number of ROB writes -system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23600919 # Number of Instructions Simulated -system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated -system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads -system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 872 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes -system.cpu0.icache.replacements 392591 # number of replacements -system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use -system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits -system.cpu0.icache.overall_hits::total 3795579 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses -system.cpu0.icache.overall_misses::total 423854 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked +system.cpu0.rob.rob_reads 76811981 # The number of ROB reads +system.cpu0.rob.rob_writes 76803371 # The number of ROB writes +system.cpu0.timesIdled 362519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26386027 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5137205074 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23977107 # Number of Instructions Simulated +system.cpu0.committedOps 31686935 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23977107 # Number of Instructions Simulated +system.cpu0.cpi 2.848984 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.848984 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.351002 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.351002 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174070948 # number of integer regfile reads +system.cpu0.int_regfile_writes 34592870 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3226 # number of floating regfile reads +system.cpu0.fp_regfile_writes 898 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13195358 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457522 # number of misc regfile writes +system.cpu0.icache.replacements 399011 # number of replacements +system.cpu0.icache.tagsinuse 511.581015 # Cycle average of tags in use +system.cpu0.icache.total_refs 3839482 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399523 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.610165 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.581015 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999182 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3839482 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3839482 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3839482 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3839482 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3839482 # number of overall hits +system.cpu0.icache.overall_hits::total 3839482 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430854 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430854 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430854 # number of overall misses +system.cpu0.icache.overall_misses::total 430854 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5887932497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5887932497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5887932497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5887932497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5887932497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5887932497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4270336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4270336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4270336 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4270336 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4270336 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4270336 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100895 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100895 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100895 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100895 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100895 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100895 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13665.725506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13665.725506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13665.725506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13665.725506 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2816 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.649007 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31313 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31313 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31313 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31313 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31313 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31313 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399541 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399541 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399541 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399541 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399541 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399541 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811758497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811758497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811758497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4811758497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093562 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093562 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093562 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12043.215833 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276649 # number of replacements -system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137052 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8942989 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8942989 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8942989 # number of overall hits -system.cpu0.dcache.overall_hits::total 8942989 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394048 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394048 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1583429 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1583429 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8774 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8774 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1977477 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1977477 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1977477 # number of overall misses -system.cpu0.dcache.overall_misses::total 1977477 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5492603000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5492603000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60464990363 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60464990363 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87990000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87990000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46572500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46572500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 65957593363 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 65957593363 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 65957593363 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 65957593363 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176129 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6176129 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744337 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744337 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147872 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147872 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144541 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144541 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10920466 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10920466 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10920466 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10920466 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063802 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063802 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333751 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333751 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059335 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059335 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051812 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051812 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181080 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181080 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181080 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181080 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.918609 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.918609 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38186.107721 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38186.107721 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10028.493276 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10028.493276 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6218.787555 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6218.787555 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33354.417454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33354.417454 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8825 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4351 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.152012 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 54.387500 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 274797 # number of replacements +system.cpu0.dcache.tagsinuse 481.556098 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9422136 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275309 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.223858 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 481.556098 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.940539 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.940539 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5871189 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5871189 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3228929 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3228929 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139484 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139484 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137178 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137178 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9100118 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9100118 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9100118 # number of overall hits +system.cpu0.dcache.overall_hits::total 9100118 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393197 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393197 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1579789 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1579789 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8860 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8860 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1972986 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1972986 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1972986 # number of overall misses +system.cpu0.dcache.overall_misses::total 1972986 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5458812500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5458812500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60787010865 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60787010865 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88634000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88634000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50172500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50172500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66245823365 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66245823365 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66245823365 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66245823365 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6264386 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6264386 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4808718 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4808718 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148344 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148344 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11073104 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11073104 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11073104 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11073104 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062767 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062767 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328526 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.328526 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059726 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059726 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053501 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053501 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178178 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178178 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178178 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178178 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13883.148905 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13883.148905 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38477.930195 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38477.930195 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10003.837472 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10003.837472 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6470.531339 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6470.531339 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33576.428502 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33576.428502 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33576.428502 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33576.428502 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8479 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4081 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 642 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.207165 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 51.658228 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 257146 # number of writebacks -system.cpu0.dcache.writebacks::total 257146 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204997 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204997 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453030 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1453030 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 464 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 464 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658027 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1658027 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658027 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1658027 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189051 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189051 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130399 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130399 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319450 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319450 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2382504500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2382504500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4025705992 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4025705992 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66268000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66268000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 255199 # number of writebacks +system.cpu0.dcache.writebacks::total 255199 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204311 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204311 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449026 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1449026 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 480 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 480 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653337 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1653337 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653337 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1653337 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188886 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188886 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130763 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130763 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8380 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319649 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319649 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319649 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319649 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2359118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4052722492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4052722492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66818500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66818500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34670500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34670500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6411840492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6411840492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6411840492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6411840492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13437088000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13437088000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251489878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251489878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688577878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688577878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027193 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027193 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056490 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056490 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053487 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053487 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.639253 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.639253 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30992.884012 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30992.884012 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7973.568019 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7973.568019 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4472.458720 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4472.458720 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1253,38 +1253,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9057370 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits +system.cpu1.branchPred.lookups 9260108 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7598823 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 418413 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6211409 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5330705 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.821188 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 799378 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 44339 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42905047 # DTB read hits -system.cpu1.dtb.read_misses 36603 # DTB read misses -system.cpu1.dtb.write_hits 6822006 # DTB write hits -system.cpu1.dtb.write_misses 10721 # DTB write misses +system.cpu1.dtb.read_hits 43181625 # DTB read hits +system.cpu1.dtb.read_misses 38342 # DTB read misses +system.cpu1.dtb.write_hits 6975478 # DTB write hits +system.cpu1.dtb.write_misses 10879 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3080 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42941650 # DTB read accesses -system.cpu1.dtb.write_accesses 6832727 # DTB write accesses +system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43219967 # DTB read accesses +system.cpu1.dtb.write_accesses 6986357 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49727053 # DTB hits -system.cpu1.dtb.misses 47324 # DTB misses -system.cpu1.dtb.accesses 49774377 # DTB accesses -system.cpu1.itb.inst_hits 8402267 # ITB inst hits -system.cpu1.itb.inst_misses 5496 # ITB inst misses +system.cpu1.dtb.hits 50157103 # DTB hits +system.cpu1.dtb.misses 49221 # DTB misses +system.cpu1.dtb.accesses 50206324 # DTB accesses +system.cpu1.itb.inst_hits 8542294 # ITB inst hits +system.cpu1.itb.inst_misses 5605 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1293,534 +1293,530 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1533 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1566 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses -system.cpu1.itb.hits 8402267 # DTB hits -system.cpu1.itb.misses 5496 # DTB misses -system.cpu1.itb.accesses 8407763 # DTB accesses -system.cpu1.numCycles 408754758 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8547899 # ITB inst accesses +system.cpu1.itb.hits 8542294 # DTB hits +system.cpu1.itb.misses 5605 # DTB misses +system.cpu1.itb.accesses 8547899 # DTB accesses +system.cpu1.numCycles 410577330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 20304470 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 67058817 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9260108 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6130083 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14383842 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4002399 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71431 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77735291 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42666 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133916 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8540383 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 747213 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115405308 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.704397 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.049572 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101028811 87.54% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 815655 0.71% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 964627 0.84% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1914792 1.66% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1533608 1.33% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 591916 0.51% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2159319 1.87% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 420670 0.36% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5975910 5.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115405308 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022554 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.163328 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21846277 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77383941 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13006148 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 540398 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2628544 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1139252 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100555 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 76481536 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 334945 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2628544 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23246660 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32001614 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41094778 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12051133 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4382579 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 70980554 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18812 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 684543 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3106754 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 398 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 74967908 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 326797465 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 326738119 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59346 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50107015 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24860893 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 461639 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 401710 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8025653 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13466262 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8327830 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1061558 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1475331 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 64680036 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1175419 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90315471 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95817 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16379719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 46059622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276388 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115405308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.782594 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520017 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84537407 73.25% 73.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8582035 7.44% 80.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4411988 3.82% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3834760 3.32% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10634435 9.21% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1994605 1.73% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1053936 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 278337 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 77805 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115405308 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32501 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 990 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572486 95.74% 96.16% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 303829 3.84% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38327866 42.44% 42.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61115 0.07% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1704 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44265466 49.01% 91.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7345367 8.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued -system.cpu1.iq.rate 0.217993 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90315471 # Type of FU issued +system.cpu1.iq.rate 0.219972 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7909806 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087580 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 304076071 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 82244261 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54749584 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14863 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6852 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97903555 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7790 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 356637 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3487877 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17725 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1325961 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31951985 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 889967 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2628544 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24227901 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361425 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 65958607 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113659 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13466262 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8327830 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 878933 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66066 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3533 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17725 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 207255 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158224 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 365479 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87865625 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43564360 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2449846 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104097 # number of nop insts executed -system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6984824 # Number of branches executed -system.cpu1.iew.exec_stores 7107734 # Number of stores executed -system.cpu1.iew.exec_rate 0.212002 # Inst execution rate -system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29912489 # num instructions producing a value -system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value +system.cpu1.iew.exec_nop 103152 # number of nop insts executed +system.cpu1.iew.exec_refs 50845626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7156733 # Number of branches executed +system.cpu1.iew.exec_stores 7281266 # Number of stores executed +system.cpu1.iew.exec_rate 0.214005 # Inst execution rate +system.cpu1.iew.wb_sent 86881552 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54756436 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30516075 # num instructions producing a value +system.cpu1.iew.wb_consumers 54547350 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133364 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559442 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16276380 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899031 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 319402 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112776764 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.436287 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.405749 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95648521 84.81% 84.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8417489 7.46% 92.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2180084 1.93% 94.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1287029 1.14% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1270394 1.13% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 584036 0.52% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1018862 0.90% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 513430 0.46% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1856919 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38055916 # Number of instructions committed -system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112776764 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38866915 # Number of instructions committed +system.cpu1.commit.committedOps 49203034 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16587382 # Number of memory references committed -system.cpu1.commit.loads 9750804 # Number of loads committed -system.cpu1.commit.membars 190065 # Number of memory barriers committed -system.cpu1.commit.branches 5966253 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534450 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16980254 # Number of memory references committed +system.cpu1.commit.loads 9978385 # Number of loads committed +system.cpu1.commit.membars 195514 # Number of memory barriers committed +system.cpu1.commit.branches 6118836 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43616937 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553185 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1856919 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172894643 # The number of ROB reads -system.cpu1.rob.rob_writes 131171187 # The number of ROB writes -system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37986277 # Number of Instructions Simulated -system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated -system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads -system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes -system.cpu1.icache.replacements 596198 # number of replacements -system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use -system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits -system.cpu1.icache.overall_hits::total 7759207 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses -system.cpu1.icache.overall_misses::total 641153 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 175333256 # The number of ROB reads +system.cpu1.rob.rob_writes 133679925 # The number of ROB writes +system.cpu1.timesIdled 1420320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295172022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4794342654 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38797276 # Number of Instructions Simulated +system.cpu1.committedOps 49133395 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38797276 # Number of Instructions Simulated +system.cpu1.cpi 10.582633 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.582633 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.094494 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.094494 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393458890 # number of integer regfile reads +system.cpu1.int_regfile_writes 57301820 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18908919 # number of misc regfile reads +system.cpu1.misc_regfile_writes 419175 # number of misc regfile writes +system.cpu1.icache.replacements 613709 # number of replacements +system.cpu1.icache.tagsinuse 498.827741 # Cycle average of tags in use +system.cpu1.icache.total_refs 7879826 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 614221 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.828975 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74226336500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.827741 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974273 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974273 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7879826 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7879826 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7879826 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7879826 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7879826 # number of overall hits +system.cpu1.icache.overall_hits::total 7879826 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 660506 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 660506 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 660506 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 660506 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 660506 # number of overall misses +system.cpu1.icache.overall_misses::total 660506 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8908973494 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8908973494 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8908973494 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8908973494 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8908973494 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8908973494 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8540332 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8540332 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8540332 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8540332 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8540332 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8540332 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077340 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.077340 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077340 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.077340 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077340 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.077340 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.103808 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13488.103808 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13488.103808 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13488.103808 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2847 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 181 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.729282 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1026 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46258 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46258 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46258 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46258 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46258 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46258 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614248 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 614248 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 614248 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 614248 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 614248 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 614248 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7279881995 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7279881995 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7279881995 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7279881995 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7279881995 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7279881995 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071923 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071923 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071923 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.698329 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 359991 # number of replacements -system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97526 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94815 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94815 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12442182 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12442182 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12442182 # number of overall hits -system.cpu1.dcache.overall_hits::total 12442182 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 400057 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 400057 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1554920 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1554920 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13970 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13970 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10628 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10628 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954977 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954977 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954977 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954977 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6105054500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6105054500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61696466986 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61696466986 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129466000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129466000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53986500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53986500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67801521486 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67801521486 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67801521486 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67801521486 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703919 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8703919 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693240 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5693240 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111496 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39678.225880 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9267.430208 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9267.430208 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.648099 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.648099 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34681.493177 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34681.493177 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 24449 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13557 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3317 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.370817 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 83.685185 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 363224 # number of replacements +system.cpu1.dcache.tagsinuse 486.354105 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13022243 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363588 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.815932 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70357393000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.354105 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.949910 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.949910 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8515751 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8515751 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4271525 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4271525 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100014 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100014 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97065 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97065 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12787276 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12787276 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12787276 # number of overall hits +system.cpu1.dcache.overall_hits::total 12787276 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 404538 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 404538 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1563969 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1563969 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14182 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10922 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10922 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1968507 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1968507 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1968507 # number of overall misses +system.cpu1.dcache.overall_misses::total 1968507 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6180682000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6180682000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61609358019 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61609358019 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131994000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131994000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58853500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58853500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67790040019 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67790040019 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67790040019 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67790040019 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8920289 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8920289 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5835494 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5835494 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 114196 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 114196 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14755783 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14755783 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14755783 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14755783 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045350 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045350 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268010 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268010 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124190 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124190 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101142 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101142 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133406 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133406 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133406 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133406 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15278.371871 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15278.371871 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39392.953453 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39392.953453 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9307.149908 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9307.149908 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5388.527742 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5388.527742 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34437.286745 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34437.286745 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29332 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 12945 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3336 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.792566 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 78.932927 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks -system.cpu1.dcache.writebacks::total 324138 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327755 # number of writebacks +system.cpu1.dcache.writebacks::total 327755 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 173193 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 173193 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400907 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1400907 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1451 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1451 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574100 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1574100 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574100 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1574100 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231345 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231345 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163062 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163062 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10917 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10917 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394407 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394407 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394407 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394407 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2902469000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2902469000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5146576709 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5146576709 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90486500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90486500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37019500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37019500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049045709 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8049045709 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049045709 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8049045709 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298073000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298073000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35738645182 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35738645182 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 205036718182 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 205036718182 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025935 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101096 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101096 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026729 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026729 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12546.063239 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12546.063239 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31562.085029 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31562.085029 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7107.572068 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7107.572068 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3390.995695 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3390.995695 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1842,18 +1838,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1245278858614 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1245278858614 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42369 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50346 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index faf182914..dbb753c24 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 59b881f50..8f8bfd301 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 25 2013 18:24:48 -gem5 started Feb 25 2013 22:58:34 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:43:56 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533144795000 because m5_exit instruction encountered +Exiting @ tick 2533114761500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 3671417ef..7887e140b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533141 # Number of seconds simulated -sim_ticks 2533140518500 # Number of ticks simulated -final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533115 # Number of seconds simulated +sim_ticks 2533114761500 # Number of ticks simulated +final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41838 # Simulator instruction rate (inst/s) -host_op_rate 53833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1757330352 # Simulator tick rate (ticks/s) -host_mem_usage 435908 # Number of bytes of host memory used -host_seconds 1441.47 # Real time elapsed on the host -sim_insts 60307702 # Number of instructions simulated -sim_ops 77599241 # Number of ops (including micro ops) simulated +host_inst_rate 24105 # Simulator instruction rate (inst/s) +host_op_rate 31016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1012479744 # Simulator tick rate (ticks/s) +host_mem_usage 439308 # Number of bytes of host memory used +host_seconds 2501.89 # Real time elapsed on the host +sim_insts 60307912 # Number of instructions simulated +sim_ops 77599507 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -24,123 +24,123 @@ system.realview.nvmem.bw_inst_read::total 25 # I system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096807 # Total number of read requests seen -system.physmem.writeReqs 813124 # Total number of write requests seen -system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195648 # Total number of bytes read from memory -system.physmem.bytesWritten 52039936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096833 # Total number of read requests seen +system.physmem.writeReqs 813132 # Total number of write requests seen +system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966197312 # Total number of bytes read from memory +system.physmem.bytesWritten 52040448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533139407500 # Total gap between requests +system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533113625500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154563 # Categorize read packet sizes +system.physmem.readPktSize::6 154589 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59106 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59114 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1039924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -151,19 +151,19 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see @@ -174,74 +174,74 @@ system.physmem.wrQLenPdf::19 35353 # Wh system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see -system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see +system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests +system.physmem.totBusLat 75482355000 # Total cycles spent in databus access system.physmem.totBankLat 16909241250 # Total cycles spent in bank access -system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgQLat 26046.04 # Average queueing delay per request system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32164.85 # Average memory access latency -system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 32166.12 # Average memory access latency +system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.32 # Average write queue length over time -system.physmem.readRowHits 15020284 # Number of row buffer hits during reads -system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.50 # Average write queue length over time +system.physmem.readRowHits 15020252 # Number of row buffer hits during reads +system.physmem.writeRowHits 793086 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes -system.physmem.avgGap 159217.50 # Average gap between requests +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159215.54 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14656582 # Number of BP lookups -system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits +system.cpu.branchPred.lookups 14667150 # Number of BP lookups +system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51396633 # DTB read hits -system.cpu.dtb.read_misses 64067 # DTB read misses -system.cpu.dtb.write_hits 11699653 # DTB write hits -system.cpu.dtb.write_misses 15746 # DTB write misses +system.cpu.dtb.read_hits 51396830 # DTB read hits +system.cpu.dtb.read_misses 64077 # DTB read misses +system.cpu.dtb.write_hits 11700143 # DTB write hits +system.cpu.dtb.write_misses 15896 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51460700 # DTB read accesses -system.cpu.dtb.write_accesses 11715399 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460907 # DTB read accesses +system.cpu.dtb.write_accesses 11716039 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096286 # DTB hits -system.cpu.dtb.misses 79813 # DTB misses -system.cpu.dtb.accesses 63176099 # DTB accesses -system.cpu.itb.inst_hits 12325480 # ITB inst hits -system.cpu.itb.inst_misses 11172 # ITB inst misses +system.cpu.dtb.hits 63096973 # DTB hits +system.cpu.dtb.misses 79973 # DTB misses +system.cpu.dtb.accesses 63176946 # DTB accesses +system.cpu.itb.inst_hits 12326910 # ITB inst hits +system.cpu.itb.inst_misses 11389 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,518 +250,518 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2484 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12336652 # ITB inst accesses -system.cpu.itb.hits 12325480 # DTB hits -system.cpu.itb.misses 11172 # DTB misses -system.cpu.itb.accesses 12336652 # DTB accesses -system.cpu.numCycles 471810648 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12338299 # ITB inst accesses +system.cpu.itb.hits 12326910 # DTB hits +system.cpu.itb.misses 11389 # DTB misses +system.cpu.itb.accesses 12338299 # DTB accesses +system.cpu.numCycles 471812928 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535276 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued -system.cpu.iq.rate 0.263438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued +system.cpu.iq.rate 0.263458 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221429 # number of nop insts executed -system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed -system.cpu.iew.exec_branches 11545908 # Number of branches executed -system.cpu.iew.exec_stores 12211356 # Number of stores executed -system.cpu.iew.exec_rate 0.257527 # Inst execution rate -system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47220023 # num instructions producing a value -system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value +system.cpu.iew.exec_nop 221256 # number of nop insts executed +system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed +system.cpu.iew.exec_branches 11548935 # Number of branches executed +system.cpu.iew.exec_stores 12211863 # Number of stores executed +system.cpu.iew.exec_rate 0.257542 # Inst execution rate +system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47248906 # num instructions producing a value +system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458083 # Number of instructions committed -system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147854976 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458293 # Number of instructions committed +system.cpu.commit.committedOps 77749888 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386631 # Number of memory references committed -system.cpu.commit.loads 15654552 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961338 # Number of branches committed +system.cpu.commit.refs 27386737 # Number of memory references committed +system.cpu.commit.loads 15654612 # Number of loads committed +system.cpu.commit.membars 403603 # Number of memory barriers committed +system.cpu.commit.branches 9961369 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854854 # Number of committed integer instructions. -system.cpu.commit.function_calls 991262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855092 # Number of committed integer instructions. +system.cpu.commit.function_calls 991267 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2901187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242306963 # The number of ROB reads -system.cpu.rob.rob_writes 201917005 # The number of ROB writes -system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307702 # Number of Instructions Simulated -system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated -system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 242290263 # The number of ROB reads +system.cpu.rob.rob_writes 201932483 # The number of ROB writes +system.cpu.timesIdled 1770811 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320491858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594333550 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307912 # Number of Instructions Simulated +system.cpu.committedOps 77599507 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307912 # Number of Instructions Simulated +system.cpu.cpi 7.823400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823400 # CPI: Total CPI of All Threads system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550141263 # number of integer regfile reads -system.cpu.int_regfile_writes 88418139 # number of integer regfile writes -system.cpu.fp_regfile_reads 8398 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979850 # number of replacements -system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use -system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits -system.cpu.icache.overall_hits::total 11261998 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses -system.cpu.icache.overall_misses::total 1059902 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.int_regfile_reads 550176555 # number of integer regfile reads +system.cpu.int_regfile_writes 88426576 # number of integer regfile writes +system.cpu.fp_regfile_reads 8298 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 30118912 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980182 # number of replacements +system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use +system.cpu.icache.total_refs 11263184 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980694 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.484912 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.616610 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11263184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11263184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11263184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11263184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11263184 # number of overall hits +system.cpu.icache.overall_hits::total 11263184 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060219 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060219 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060219 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060219 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060219 # number of overall misses +system.cpu.icache.overall_misses::total 1060219 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14018220995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14018220995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14018220995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14018220995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14018220995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14018220995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12323403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12323403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12323403 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12323403 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12323403 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12323403 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086033 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086033 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086033 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086033 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086033 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13222.005072 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13222.005072 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13222.005072 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13222.005072 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4586 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.286667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79506 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79506 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79506 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79506 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79506 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79506 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980396 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980396 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980396 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980396 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980396 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980396 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379943495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11379943495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379943495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11379943495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379943495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79489 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79489 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79489 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79489 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79489 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79489 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980730 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980730 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980730 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980730 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980730 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980730 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11392389495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11392389495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11392389495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11392389495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11392389495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11392389495 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079565 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079583 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079583 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079583 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11616.234331 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11616.234331 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64334 # number of replacements -system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003890 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8157.503084 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6228.405939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64360 # number of replacements +system.cpu.l2cache.tagsinuse 51336.859008 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885213 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129758 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.528684 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2523139048000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36935.695243 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 23.234452 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003892 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8162.031134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6215.894286 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563594 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000355 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124474 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783491 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416202 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607769 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607769 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112939 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112939 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500020 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529141 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10206 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966908 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500020 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529141 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094847 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783338 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52172 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967239 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 386976 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416862 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607588 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607588 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112931 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112931 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52172 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967239 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499907 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529793 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52172 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10475 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967239 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499907 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529793 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 36 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12331 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23084 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10700 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133206 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133206 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 36 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12331 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12355 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143906 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156300 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 36 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12331 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143895 # number of overall misses -system.cpu.l2cache.overall_misses::total 156270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2874000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 694978000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 630766499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1328805499 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 455500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732631500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6732631500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2874000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 694978000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7363397999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8061436999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2874000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 694978000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7363397999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8061436999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979239 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1439286 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246125 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52048 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10209 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643915 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1685411 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52048 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10209 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1685411 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000788 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012592 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016039 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986815 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986815 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541132 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541132 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000788 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012592 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223469 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092719 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000788 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012592 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223469 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092719 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70097.560976 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56360.230314 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58900.597535 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57563.918688 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 156.046591 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 156.046591 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50550.594657 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50550.594657 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51586.593710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51586.593710 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12355 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143906 # number of overall misses +system.cpu.l2cache.overall_misses::total 156300 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 186500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 703826000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 629251500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1335748000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 410500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6753390000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6753390000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 186500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 703826000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7382641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8089138000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 186500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 703826000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7382641500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8089138000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52208 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10478 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979594 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397676 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439956 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607588 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607588 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52208 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10478 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979594 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643813 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686093 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52208 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10478 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979594 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643813 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686093 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000690 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000286 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016038 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985820 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985820 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541186 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541186 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000690 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223521 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092700 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000690 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223521 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092700 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62166.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56966.895994 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58808.551402 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57839.612020 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.582192 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.582192 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50698.842394 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50698.842394 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51753.921945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51753.921945 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,109 +770,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59106 # number of writebacks -system.cpu.l2cache.writebacks::total 59106 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59114 # number of writebacks +system.cpu.l2cache.writebacks::total 59114 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 36 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12319 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10648 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23011 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2919 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2919 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23022 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133206 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133206 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 36 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143834 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156197 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 36 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12319 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143834 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156197 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2360290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2033785 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541016289 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 495761741 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1039287822 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29192919 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29192919 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 549600048 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 494356239 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1046139574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072671631 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072671631 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2360290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5093264625 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5093264625 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2033785 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549600048 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587620864 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6139404199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2033785 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549600048 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587620864 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6139404199 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002364267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007445097 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26884342911 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26884342911 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193891788008 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026755 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985820 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985820 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541186 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541186 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44527.266305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.052538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45440.864130 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38236.000068 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38236.000068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643403 # number of replacements +system.cpu.dcache.replacements 643301 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.total_refs 21506564 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643813 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.404986 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits -system.cpu.dcache.overall_hits::total 21013434 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737092 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737092 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962848 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962848 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13493 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13493 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses -system.cpu.dcache.overall_misses::total 3699940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13753913 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753913 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259030 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242896 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242896 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247606 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247606 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012943 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012943 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012943 # number of overall hits +system.cpu.dcache.overall_hits::total 21012943 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737130 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963360 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963360 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13521 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13521 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700490 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700490 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700490 # number of overall misses +system.cpu.dcache.overall_misses::total 3700490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9747104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9747104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104655662232 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104655662232 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180718000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180718000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114402766232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114402766232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114402766232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114402766232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491043 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491043 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222390 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222390 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256417 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256417 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713433 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713433 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713433 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713433 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050868 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050868 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289889 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289889 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30915.572325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30915.572325 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18747 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2620 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.825573 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 74.689243 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks -system.cpu.dcache.writebacks::total 607769 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607588 # number of writebacks +system.cpu.dcache.writebacks::total 607588 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714338 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714338 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065882 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065882 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385586 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385586 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12167 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12167 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634608 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8203666916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8203666916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141299500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141299500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13006963416 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13006963416 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13006963416 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13006963416 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36699724336 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36699724336 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 22443d9d9..3a9f6f104 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 151c69fa7..b4a6065b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -22,5 +23,7 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed. -Program aborted at cycle 2395768530500 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 527d0013c..1c8a8dfdd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:03:06 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:07:42 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second @@ -33,4104 +33,4056 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 5000004000. Starting simulation... switching cpus -info: Entering event queue @ 5000004500. Starting simulation... +info: Entering event queue @ 5000005000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000004500. Starting simulation... +info: Entering event queue @ 6000005000. Starting simulation... switching cpus -info: Entering event queue @ 6000011000. Starting simulation... +info: Entering event queue @ 6000010500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 7000011000. Starting simulation... +info: Entering event queue @ 7000010500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 8000011000. Starting simulation... +info: Entering event queue @ 8000010500. Starting simulation... switching cpus -info: Entering event queue @ 8000065000. Starting simulation... +info: Entering event queue @ 8000121000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000065000. Starting simulation... -info: Entering event queue @ 9000075500. Starting simulation... +info: Entering event queue @ 9000121000. Starting simulation... switching cpus -info: Entering event queue @ 9000080000. Starting simulation... +info: Entering event queue @ 9000131500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 10000080000. Starting simulation... switching cpus -info: Entering event queue @ 10000082500. Starting simulation... +info: Entering event queue @ 10000131500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 11000082500. Starting simulation... +info: Entering event queue @ 11000131500. Starting simulation... switching cpus -info: Entering event queue @ 11000084500. Starting simulation... +info: Entering event queue @ 11000132500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 12000084500. Starting simulation... +info: Entering event queue @ 12000132500. Starting simulation... switching cpus -info: Entering event queue @ 12000089500. Starting simulation... +info: Entering event queue @ 12000140500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 13000140500. Starting simulation... switching cpus -info: Entering event queue @ 13000089500. Starting simulation... +info: Entering event queue @ 13000141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 14000089500. Starting simulation... +info: Entering event queue @ 14000141500. Starting simulation... switching cpus -info: Entering event queue @ 14000090500. Starting simulation... +info: Entering event queue @ 14000161500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 15000090500. Starting simulation... +info: Entering event queue @ 15000161500. Starting simulation... switching cpus -info: Entering event queue @ 15000095000. Starting simulation... +info: Entering event queue @ 15000173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 16000095000. Starting simulation... +info: Entering event queue @ 16000173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 17000095000. Starting simulation... +info: Entering event queue @ 17000173500. Starting simulation... switching cpus -info: Entering event queue @ 17000096000. Starting simulation... +info: Entering event queue @ 17000181000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 18000096000. Starting simulation... -info: Entering event queue @ 26044720500. Starting simulation... -info: Entering event queue @ 26044727000. Starting simulation... +info: Entering event queue @ 18000181000. Starting simulation... +info: Entering event queue @ 26044694500. Starting simulation... +info: Entering event queue @ 26044701500. Starting simulation... switching cpus -info: Entering event queue @ 26044727500. Starting simulation... +info: Entering event queue @ 26044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 27044727500. Starting simulation... +info: Entering event queue @ 27044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 28044727500. Starting simulation... +info: Entering event queue @ 28044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 29044727500. Starting simulation... -info: Entering event queue @ 36044720500. Starting simulation... -info: Entering event queue @ 36044727000. Starting simulation... +info: Entering event queue @ 29044706000. Starting simulation... +info: Entering event queue @ 36044694500. Starting simulation... +info: Entering event queue @ 36044701500. Starting simulation... switching cpus -info: Entering event queue @ 36044727500. Starting simulation... +info: Entering event queue @ 36044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 37044727500. Starting simulation... +info: Entering event queue @ 37044706000. Starting simulation... switching cpus -info: Entering event queue @ 37044728000. Starting simulation... +info: Entering event queue @ 37044706500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 38044728000. Starting simulation... -info: Entering event queue @ 38044743500. Starting simulation... +info: Entering event queue @ 38044706500. Starting simulation... +info: Entering event queue @ 38044722500. Starting simulation... switching cpus -info: Entering event queue @ 38044784500. Starting simulation... +info: Entering event queue @ 38044806000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 39044784500. Starting simulation... +info: Entering event queue @ 39044806000. Starting simulation... switching cpus -info: Entering event queue @ 39044856000. Starting simulation... +info: Entering event queue @ 39044813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 40044856000. Starting simulation... +info: Entering event queue @ 40044813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 41044856000. Starting simulation... +info: Entering event queue @ 41044813500. Starting simulation... switching cpus -info: Entering event queue @ 41044857500. Starting simulation... +info: Entering event queue @ 41044821000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 42044857500. Starting simulation... +info: Entering event queue @ 42044821000. Starting simulation... switching cpus -info: Entering event queue @ 42045164500. Starting simulation... +info: Entering event queue @ 42045002500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 43045164500. Starting simulation... switching cpus -info: Entering event queue @ 43045165500. Starting simulation... +info: Entering event queue @ 43045002500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 44045165500. Starting simulation... +info: Entering event queue @ 44045002500. Starting simulation... switching cpus -info: Entering event queue @ 44045166000. Starting simulation... +info: Entering event queue @ 44045003500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 45045166000. Starting simulation... +info: Entering event queue @ 45045003500. Starting simulation... switching cpus -info: Entering event queue @ 45045171000. Starting simulation... +info: Entering event queue @ 45045006000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 46045171000. Starting simulation... +info: Entering event queue @ 46045006000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 47045171000. Starting simulation... +info: Entering event queue @ 47045006000. Starting simulation... switching cpus -info: Entering event queue @ 47045181500. Starting simulation... +info: Entering event queue @ 47045010000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 48045181500. Starting simulation... +info: Entering event queue @ 48045010000. Starting simulation... switching cpus -info: Entering event queue @ 48045187000. Starting simulation... +info: Entering event queue @ 48045031000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 49045187000. Starting simulation... +info: Entering event queue @ 49045031000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 50045031000. Starting simulation... switching cpus -info: Entering event queue @ 50045187000. Starting simulation... +info: Entering event queue @ 50045038500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 51045187000. Starting simulation... -info: Entering event queue @ 56044720500. Starting simulation... -info: Entering event queue @ 56044727000. Starting simulation... +info: Entering event queue @ 51045038500. Starting simulation... +info: Entering event queue @ 56044694500. Starting simulation... +info: Entering event queue @ 56044701500. Starting simulation... switching cpus -info: Entering event queue @ 56044727500. Starting simulation... +info: Entering event queue @ 56044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 57044727500. Starting simulation... +info: Entering event queue @ 57044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 58044727500. Starting simulation... +info: Entering event queue @ 58044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 59044727500. Starting simulation... -info: Entering event queue @ 66044720500. Starting simulation... -info: Entering event queue @ 66044727000. Starting simulation... +info: Entering event queue @ 59044706000. Starting simulation... +info: Entering event queue @ 66044694500. Starting simulation... +info: Entering event queue @ 66044701500. Starting simulation... switching cpus -info: Entering event queue @ 66044727500. Starting simulation... +info: Entering event queue @ 66044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 67044727500. Starting simulation... +info: Entering event queue @ 67044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 68044727500. Starting simulation... +info: Entering event queue @ 68044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 69044727500. Starting simulation... -info: Entering event queue @ 76044720500. Starting simulation... -info: Entering event queue @ 76044727000. Starting simulation... +info: Entering event queue @ 69044706000. Starting simulation... +info: Entering event queue @ 76044694500. Starting simulation... +info: Entering event queue @ 76044701500. Starting simulation... switching cpus -info: Entering event queue @ 76044727500. Starting simulation... +info: Entering event queue @ 76044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 77044727500. Starting simulation... +info: Entering event queue @ 77044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 78044727500. Starting simulation... +info: Entering event queue @ 78044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 79044727500. Starting simulation... -info: Entering event queue @ 86044720500. Starting simulation... -info: Entering event queue @ 86044727000. Starting simulation... +info: Entering event queue @ 79044706000. Starting simulation... +info: Entering event queue @ 86044694500. Starting simulation... +info: Entering event queue @ 86044701000. Starting simulation... switching cpus -info: Entering event queue @ 86044727500. Starting simulation... +info: Entering event queue @ 86044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 87044727500. Starting simulation... +info: Entering event queue @ 87044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 88044727500. Starting simulation... +info: Entering event queue @ 88044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 89044727500. Starting simulation... -info: Entering event queue @ 96044720500. Starting simulation... -info: Entering event queue @ 96044727000. Starting simulation... +info: Entering event queue @ 89044701500. Starting simulation... +info: Entering event queue @ 96044694500. Starting simulation... +info: Entering event queue @ 96044701500. Starting simulation... switching cpus -info: Entering event queue @ 96044727500. Starting simulation... +info: Entering event queue @ 96044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 97044727500. Starting simulation... +info: Entering event queue @ 97044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 98044727500. Starting simulation... +info: Entering event queue @ 98044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 99044727500. Starting simulation... -info: Entering event queue @ 106044720500. Starting simulation... -info: Entering event queue @ 106044727000. Starting simulation... +info: Entering event queue @ 99044706000. Starting simulation... +info: Entering event queue @ 106044694500. Starting simulation... +info: Entering event queue @ 106044701500. Starting simulation... switching cpus -info: Entering event queue @ 106044727500. Starting simulation... +info: Entering event queue @ 106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 107044727500. Starting simulation... +info: Entering event queue @ 107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 108044727500. Starting simulation... +info: Entering event queue @ 108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 109044727500. Starting simulation... -info: Entering event queue @ 116044720500. Starting simulation... -info: Entering event queue @ 116044727000. Starting simulation... +info: Entering event queue @ 109044706000. Starting simulation... +info: Entering event queue @ 116044694500. Starting simulation... +info: Entering event queue @ 116044701500. Starting simulation... switching cpus -info: Entering event queue @ 116044727500. Starting simulation... +info: Entering event queue @ 116044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 117044727500. Starting simulation... +info: Entering event queue @ 117044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 118044727500. Starting simulation... +info: Entering event queue @ 118044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 119044727500. Starting simulation... -info: Entering event queue @ 126044720500. Starting simulation... -info: Entering event queue @ 126044727000. Starting simulation... +info: Entering event queue @ 119044706000. Starting simulation... +info: Entering event queue @ 126044695500. Starting simulation... +info: Entering event queue @ 126044702000. Starting simulation... switching cpus -info: Entering event queue @ 126044727500. Starting simulation... +info: Entering event queue @ 126044702500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 127044727500. Starting simulation... +info: Entering event queue @ 127044702500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 128044727500. Starting simulation... +info: Entering event queue @ 128044702500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 129044727500. Starting simulation... -info: Entering event queue @ 136044720500. Starting simulation... -info: Entering event queue @ 136044727000. Starting simulation... +info: Entering event queue @ 129044702500. Starting simulation... +info: Entering event queue @ 136044694500. Starting simulation... +info: Entering event queue @ 136044701000. Starting simulation... switching cpus -info: Entering event queue @ 136044727500. Starting simulation... +info: Entering event queue @ 136044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 137044727500. Starting simulation... +info: Entering event queue @ 137044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 138044727500. Starting simulation... +info: Entering event queue @ 138044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 139044727500. Starting simulation... -info: Entering event queue @ 146044720500. Starting simulation... -info: Entering event queue @ 146044727000. Starting simulation... +info: Entering event queue @ 139044701500. Starting simulation... +info: Entering event queue @ 146044694500. Starting simulation... +info: Entering event queue @ 146044701500. Starting simulation... switching cpus -info: Entering event queue @ 146044727500. Starting simulation... +info: Entering event queue @ 146044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 147044727500. Starting simulation... +info: Entering event queue @ 147044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 148044727500. Starting simulation... +info: Entering event queue @ 148044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 149044727500. Starting simulation... -info: Entering event queue @ 156044720500. Starting simulation... -info: Entering event queue @ 156044727000. Starting simulation... +info: Entering event queue @ 149044706000. Starting simulation... +info: Entering event queue @ 156044694500. Starting simulation... +info: Entering event queue @ 156044701500. Starting simulation... switching cpus -info: Entering event queue @ 156044727500. Starting simulation... +info: Entering event queue @ 156044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 157044727500. Starting simulation... +info: Entering event queue @ 157044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 158044727500. Starting simulation... +info: Entering event queue @ 158044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 159044727500. Starting simulation... -info: Entering event queue @ 166044720500. Starting simulation... -info: Entering event queue @ 166044727000. Starting simulation... +info: Entering event queue @ 159044706000. Starting simulation... +info: Entering event queue @ 166044694500. Starting simulation... +info: Entering event queue @ 166044701500. Starting simulation... switching cpus -info: Entering event queue @ 166044727500. Starting simulation... +info: Entering event queue @ 166044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 167044727500. Starting simulation... +info: Entering event queue @ 167044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 168044727500. Starting simulation... +info: Entering event queue @ 168044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 169044727500. Starting simulation... -info: Entering event queue @ 176044720500. Starting simulation... -info: Entering event queue @ 176044727000. Starting simulation... +info: Entering event queue @ 169044706000. Starting simulation... +info: Entering event queue @ 176044694500. Starting simulation... +info: Entering event queue @ 176044701500. Starting simulation... switching cpus -info: Entering event queue @ 176044727500. Starting simulation... +info: Entering event queue @ 176044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 177044727500. Starting simulation... +info: Entering event queue @ 177044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 178044727500. Starting simulation... +info: Entering event queue @ 178044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 179044727500. Starting simulation... -info: Entering event queue @ 186044720500. Starting simulation... -info: Entering event queue @ 186044727000. Starting simulation... +info: Entering event queue @ 179044706000. Starting simulation... +info: Entering event queue @ 186044694500. Starting simulation... +info: Entering event queue @ 186044701500. Starting simulation... switching cpus -info: Entering event queue @ 186044727500. Starting simulation... +info: Entering event queue @ 186044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 187044727500. Starting simulation... +info: Entering event queue @ 187044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 188044727500. Starting simulation... +info: Entering event queue @ 188044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 189044727500. Starting simulation... -info: Entering event queue @ 196044720500. Starting simulation... -info: Entering event queue @ 196044727000. Starting simulation... +info: Entering event queue @ 189044706000. Starting simulation... +info: Entering event queue @ 196044695500. Starting simulation... +info: Entering event queue @ 196044702500. Starting simulation... switching cpus -info: Entering event queue @ 196044727500. Starting simulation... +info: Entering event queue @ 196044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 197044727500. Starting simulation... +info: Entering event queue @ 197044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 198044727500. Starting simulation... +info: Entering event queue @ 198044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 199044727500. Starting simulation... -info: Entering event queue @ 206044720500. Starting simulation... -info: Entering event queue @ 206044727000. Starting simulation... +info: Entering event queue @ 199044707000. Starting simulation... +info: Entering event queue @ 206044695500. Starting simulation... +info: Entering event queue @ 206044702500. Starting simulation... switching cpus -info: Entering event queue @ 206044727500. Starting simulation... +info: Entering event queue @ 206044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 207044727500. Starting simulation... +info: Entering event queue @ 207044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 208044727500. Starting simulation... +info: Entering event queue @ 208044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 209044727500. Starting simulation... -info: Entering event queue @ 216044720500. Starting simulation... -info: Entering event queue @ 216044727000. Starting simulation... +info: Entering event queue @ 209044707000. Starting simulation... +info: Entering event queue @ 216044694500. Starting simulation... +info: Entering event queue @ 216044701500. Starting simulation... switching cpus -info: Entering event queue @ 216044727500. Starting simulation... +info: Entering event queue @ 216044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 217044727500. Starting simulation... +info: Entering event queue @ 217044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 218044727500. Starting simulation... +info: Entering event queue @ 218044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 219044727500. Starting simulation... -info: Entering event queue @ 226044720500. Starting simulation... -info: Entering event queue @ 226044727000. Starting simulation... +info: Entering event queue @ 219044706000. Starting simulation... +info: Entering event queue @ 226044694500. Starting simulation... +info: Entering event queue @ 226044701500. Starting simulation... switching cpus -info: Entering event queue @ 226044727500. Starting simulation... +info: Entering event queue @ 226044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 227044727500. Starting simulation... +info: Entering event queue @ 227044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 228044727500. Starting simulation... +info: Entering event queue @ 228044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 229044727500. Starting simulation... -info: Entering event queue @ 236044720500. Starting simulation... -info: Entering event queue @ 236044727000. Starting simulation... +info: Entering event queue @ 229044706000. Starting simulation... +info: Entering event queue @ 236044694500. Starting simulation... +info: Entering event queue @ 236044701500. Starting simulation... switching cpus -info: Entering event queue @ 236044727500. Starting simulation... +info: Entering event queue @ 236044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 237044727500. Starting simulation... +info: Entering event queue @ 237044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 238044727500. Starting simulation... +info: Entering event queue @ 238044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 239044727500. Starting simulation... -info: Entering event queue @ 246044720500. Starting simulation... -info: Entering event queue @ 246044727000. Starting simulation... +info: Entering event queue @ 239044706000. Starting simulation... +info: Entering event queue @ 246044694500. Starting simulation... +info: Entering event queue @ 246044701000. Starting simulation... switching cpus -info: Entering event queue @ 246044727500. Starting simulation... +info: Entering event queue @ 246044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 247044727500. Starting simulation... +info: Entering event queue @ 247044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 248044727500. Starting simulation... +info: Entering event queue @ 248044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 249044727500. Starting simulation... -info: Entering event queue @ 256044720500. Starting simulation... -info: Entering event queue @ 256044727000. Starting simulation... +info: Entering event queue @ 249044701500. Starting simulation... +info: Entering event queue @ 256044694500. Starting simulation... +info: Entering event queue @ 256044701500. Starting simulation... switching cpus -info: Entering event queue @ 256044727500. Starting simulation... +info: Entering event queue @ 256044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 257044727500. Starting simulation... +info: Entering event queue @ 257044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 258044727500. Starting simulation... +info: Entering event queue @ 258044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 259044727500. Starting simulation... -info: Entering event queue @ 266044720500. Starting simulation... -info: Entering event queue @ 266847937000. Starting simulation... +info: Entering event queue @ 259044706000. Starting simulation... +info: Entering event queue @ 266044694500. Starting simulation... +info: Entering event queue @ 266911751000. Starting simulation... switching cpus -info: Entering event queue @ 266847939000. Starting simulation... +info: Entering event queue @ 266911753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 267847939000. Starting simulation... +info: Entering event queue @ 267911753000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 268847939000. Starting simulation... +info: Entering event queue @ 268911753000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 269847939000. Starting simulation... -info: Entering event queue @ 276044720500. Starting simulation... -info: Entering event queue @ 276044727000. Starting simulation... +info: Entering event queue @ 269911753000. Starting simulation... +info: Entering event queue @ 276044694500. Starting simulation... +info: Entering event queue @ 276044701500. Starting simulation... switching cpus -info: Entering event queue @ 276044727500. Starting simulation... +info: Entering event queue @ 276044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 277044727500. Starting simulation... +info: Entering event queue @ 277044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 278044727500. Starting simulation... +info: Entering event queue @ 278044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 279044727500. Starting simulation... -info: Entering event queue @ 286044720500. Starting simulation... -info: Entering event queue @ 286044727000. Starting simulation... +info: Entering event queue @ 279044706000. Starting simulation... +info: Entering event queue @ 286044695500. Starting simulation... +info: Entering event queue @ 286044702500. Starting simulation... switching cpus -info: Entering event queue @ 286044727500. Starting simulation... +info: Entering event queue @ 286044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 287044727500. Starting simulation... +info: Entering event queue @ 287044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 288044727500. Starting simulation... +info: Entering event queue @ 288044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 289044727500. Starting simulation... -info: Entering event queue @ 296044720500. Starting simulation... -info: Entering event queue @ 296044727000. Starting simulation... +info: Entering event queue @ 289044707000. Starting simulation... +info: Entering event queue @ 296044694500. Starting simulation... +info: Entering event queue @ 296044701000. Starting simulation... switching cpus -info: Entering event queue @ 296044727500. Starting simulation... +info: Entering event queue @ 296044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 297044727500. Starting simulation... +info: Entering event queue @ 297044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 298044727500. Starting simulation... -info: Entering event queue @ 299584231000. Starting simulation... +info: Entering event queue @ 298044701500. Starting simulation... +info: Entering event queue @ 299648351000. Starting simulation... switching cpus -info: Entering event queue @ 299584233000. Starting simulation... +info: Entering event queue @ 299648353000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 300584233000. Starting simulation... -info: Entering event queue @ 306044720500. Starting simulation... -info: Entering event queue @ 306044727000. Starting simulation... +info: Entering event queue @ 300648353000. Starting simulation... +info: Entering event queue @ 306044694500. Starting simulation... +info: Entering event queue @ 306044701500. Starting simulation... switching cpus -info: Entering event queue @ 306044727500. Starting simulation... +info: Entering event queue @ 306044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 307044727500. Starting simulation... +info: Entering event queue @ 307044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 308044727500. Starting simulation... +info: Entering event queue @ 308044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 309044727500. Starting simulation... -info: Entering event queue @ 316044720500. Starting simulation... -info: Entering event queue @ 316044727000. Starting simulation... +info: Entering event queue @ 309044706000. Starting simulation... +info: Entering event queue @ 316044694500. Starting simulation... +info: Entering event queue @ 316044701500. Starting simulation... switching cpus -info: Entering event queue @ 316044727500. Starting simulation... +info: Entering event queue @ 316044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 317044727500. Starting simulation... +info: Entering event queue @ 317044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 318044727500. Starting simulation... +info: Entering event queue @ 318044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 319044727500. Starting simulation... -info: Entering event queue @ 326044720500. Starting simulation... -info: Entering event queue @ 326044727000. Starting simulation... +info: Entering event queue @ 319044706000. Starting simulation... +info: Entering event queue @ 326044694500. Starting simulation... +info: Entering event queue @ 326044701500. Starting simulation... switching cpus -info: Entering event queue @ 326044727500. Starting simulation... +info: Entering event queue @ 326044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 327044727500. Starting simulation... +info: Entering event queue @ 327044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 328044727500. Starting simulation... +info: Entering event queue @ 328044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 329044727500. Starting simulation... -info: Entering event queue @ 336044720500. Starting simulation... -info: Entering event queue @ 336044727000. Starting simulation... +info: Entering event queue @ 329044706000. Starting simulation... +info: Entering event queue @ 336044694500. Starting simulation... +info: Entering event queue @ 336044701500. Starting simulation... switching cpus -info: Entering event queue @ 336044727500. Starting simulation... +info: Entering event queue @ 336044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 337044727500. Starting simulation... +info: Entering event queue @ 337044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 338044727500. Starting simulation... +info: Entering event queue @ 338044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 339044727500. Starting simulation... -info: Entering event queue @ 346044720500. Starting simulation... -info: Entering event queue @ 346044727000. Starting simulation... +info: Entering event queue @ 339044706000. Starting simulation... +info: Entering event queue @ 346044694500. Starting simulation... +info: Entering event queue @ 346044701500. Starting simulation... switching cpus -info: Entering event queue @ 346044727500. Starting simulation... +info: Entering event queue @ 346044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 347044727500. Starting simulation... +info: Entering event queue @ 347044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 348044727500. Starting simulation... +info: Entering event queue @ 348044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 349044727500. Starting simulation... -info: Entering event queue @ 356044720500. Starting simulation... -info: Entering event queue @ 356044727000. Starting simulation... +info: Entering event queue @ 349044706000. Starting simulation... +info: Entering event queue @ 356044695500. Starting simulation... +info: Entering event queue @ 356044702500. Starting simulation... switching cpus -info: Entering event queue @ 356044727500. Starting simulation... +info: Entering event queue @ 356044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 357044727500. Starting simulation... +info: Entering event queue @ 357044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 358044727500. Starting simulation... +info: Entering event queue @ 358044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 359044727500. Starting simulation... -info: Entering event queue @ 366044720500. Starting simulation... -info: Entering event queue @ 366044727000. Starting simulation... +info: Entering event queue @ 359044707000. Starting simulation... +info: Entering event queue @ 366044695500. Starting simulation... +info: Entering event queue @ 366044702500. Starting simulation... switching cpus -info: Entering event queue @ 366044727500. Starting simulation... +info: Entering event queue @ 366044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 367044727500. Starting simulation... +info: Entering event queue @ 367044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 368044727500. Starting simulation... +info: Entering event queue @ 368044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 369044727500. Starting simulation... -info: Entering event queue @ 376044720500. Starting simulation... -info: Entering event queue @ 376044727000. Starting simulation... +info: Entering event queue @ 369044707000. Starting simulation... +info: Entering event queue @ 376044695500. Starting simulation... +info: Entering event queue @ 376044703500. Starting simulation... switching cpus -info: Entering event queue @ 376044727500. Starting simulation... +info: Entering event queue @ 376044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 377044727500. Starting simulation... +info: Entering event queue @ 377044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 378044727500. Starting simulation... +info: Entering event queue @ 378044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 379044727500. Starting simulation... -info: Entering event queue @ 386044720500. Starting simulation... -info: Entering event queue @ 386044727000. Starting simulation... +info: Entering event queue @ 379044708000. Starting simulation... +info: Entering event queue @ 386044695500. Starting simulation... +info: Entering event queue @ 386044703500. Starting simulation... switching cpus -info: Entering event queue @ 386044727500. Starting simulation... +info: Entering event queue @ 386044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 387044727500. Starting simulation... +info: Entering event queue @ 387044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 388044727500. Starting simulation... +info: Entering event queue @ 388044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 389044727500. Starting simulation... -info: Entering event queue @ 396044720500. Starting simulation... -info: Entering event queue @ 396044727000. Starting simulation... +info: Entering event queue @ 389044704000. Starting simulation... +info: Entering event queue @ 396044695500. Starting simulation... +info: Entering event queue @ 396044703500. Starting simulation... switching cpus -info: Entering event queue @ 396044727500. Starting simulation... +info: Entering event queue @ 396044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 397044727500. Starting simulation... +info: Entering event queue @ 397044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 398044727500. Starting simulation... +info: Entering event queue @ 398044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 399044727500. Starting simulation... -info: Entering event queue @ 406044720500. Starting simulation... -info: Entering event queue @ 406044727000. Starting simulation... +info: Entering event queue @ 399044708000. Starting simulation... +info: Entering event queue @ 406044694500. Starting simulation... +info: Entering event queue @ 406044701000. Starting simulation... switching cpus -info: Entering event queue @ 406044727500. Starting simulation... +info: Entering event queue @ 406044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 407044727500. Starting simulation... +info: Entering event queue @ 407044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 408044727500. Starting simulation... +info: Entering event queue @ 408044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 409044727500. Starting simulation... -info: Entering event queue @ 416044720500. Starting simulation... -info: Entering event queue @ 416044727000. Starting simulation... +info: Entering event queue @ 409044701500. Starting simulation... +info: Entering event queue @ 416044694500. Starting simulation... +info: Entering event queue @ 416044701500. Starting simulation... switching cpus -info: Entering event queue @ 416044727500. Starting simulation... +info: Entering event queue @ 416044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 417044727500. Starting simulation... +info: Entering event queue @ 417044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 418044727500. Starting simulation... +info: Entering event queue @ 418044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 419044727500. Starting simulation... -info: Entering event queue @ 426044720500. Starting simulation... -info: Entering event queue @ 426044727000. Starting simulation... +info: Entering event queue @ 419044706000. Starting simulation... +info: Entering event queue @ 426044695500. Starting simulation... +info: Entering event queue @ 426044703500. Starting simulation... switching cpus -info: Entering event queue @ 426044727500. Starting simulation... +info: Entering event queue @ 426044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 427044727500. Starting simulation... +info: Entering event queue @ 427044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 428044727500. Starting simulation... +info: Entering event queue @ 428044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 429044727500. Starting simulation... -info: Entering event queue @ 436044720500. Starting simulation... -info: Entering event queue @ 436044727000. Starting simulation... +info: Entering event queue @ 429044708000. Starting simulation... +info: Entering event queue @ 436044694500. Starting simulation... +info: Entering event queue @ 436044701500. Starting simulation... switching cpus -info: Entering event queue @ 436044727500. Starting simulation... +info: Entering event queue @ 436044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 437044727500. Starting simulation... +info: Entering event queue @ 437044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 438044727500. Starting simulation... +info: Entering event queue @ 438044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 439044727500. Starting simulation... -info: Entering event queue @ 446044720500. Starting simulation... -info: Entering event queue @ 446044727000. Starting simulation... +info: Entering event queue @ 439044706000. Starting simulation... +info: Entering event queue @ 446044695500. Starting simulation... +info: Entering event queue @ 446044702500. Starting simulation... switching cpus -info: Entering event queue @ 446044727500. Starting simulation... +info: Entering event queue @ 446044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 447044727500. Starting simulation... +info: Entering event queue @ 447044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 448044727500. Starting simulation... +info: Entering event queue @ 448044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 449044727500. Starting simulation... -info: Entering event queue @ 456044720500. Starting simulation... -info: Entering event queue @ 456044727000. Starting simulation... +info: Entering event queue @ 449044707000. Starting simulation... +info: Entering event queue @ 456044694500. Starting simulation... +info: Entering event queue @ 456044701000. Starting simulation... switching cpus -info: Entering event queue @ 456044727500. Starting simulation... +info: Entering event queue @ 456044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 457044727500. Starting simulation... +info: Entering event queue @ 457044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 458044727500. Starting simulation... +info: Entering event queue @ 458044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 459044727500. Starting simulation... -info: Entering event queue @ 466044720500. Starting simulation... -info: Entering event queue @ 466044727000. Starting simulation... +info: Entering event queue @ 459044701500. Starting simulation... +info: Entering event queue @ 466044694500. Starting simulation... +info: Entering event queue @ 466044701500. Starting simulation... switching cpus -info: Entering event queue @ 466044727500. Starting simulation... +info: Entering event queue @ 466044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 467044727500. Starting simulation... +info: Entering event queue @ 467044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 468044727500. Starting simulation... +info: Entering event queue @ 468044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 469044727500. Starting simulation... -info: Entering event queue @ 476044720500. Starting simulation... -info: Entering event queue @ 476044727000. Starting simulation... +info: Entering event queue @ 469044706000. Starting simulation... +info: Entering event queue @ 476044694500. Starting simulation... +info: Entering event queue @ 476044701500. Starting simulation... switching cpus -info: Entering event queue @ 476044727500. Starting simulation... +info: Entering event queue @ 476044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 477044727500. Starting simulation... +info: Entering event queue @ 477044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 478044727500. Starting simulation... +info: Entering event queue @ 478044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 479044727500. Starting simulation... -info: Entering event queue @ 486044720500. Starting simulation... -info: Entering event queue @ 486044727000. Starting simulation... +info: Entering event queue @ 479044706000. Starting simulation... +info: Entering event queue @ 486044694500. Starting simulation... +info: Entering event queue @ 486044701500. Starting simulation... switching cpus -info: Entering event queue @ 486044727500. Starting simulation... +info: Entering event queue @ 486044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 487044727500. Starting simulation... +info: Entering event queue @ 487044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 488044727500. Starting simulation... +info: Entering event queue @ 488044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 489044727500. Starting simulation... -info: Entering event queue @ 496044720500. Starting simulation... -info: Entering event queue @ 496044727000. Starting simulation... +info: Entering event queue @ 489044706000. Starting simulation... +info: Entering event queue @ 496044694500. Starting simulation... +info: Entering event queue @ 496065726000. Starting simulation... switching cpus -info: Entering event queue @ 496044727500. Starting simulation... +info: Entering event queue @ 496065728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 497044727500. Starting simulation... +info: Entering event queue @ 497065728000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 498044727500. Starting simulation... +info: Entering event queue @ 498065728000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 499044727500. Starting simulation... -info: Entering event queue @ 506044720500. Starting simulation... -info: Entering event queue @ 506044727000. Starting simulation... +info: Entering event queue @ 499065728000. Starting simulation... +info: Entering event queue @ 506044695500. Starting simulation... +info: Entering event queue @ 506044703500. Starting simulation... switching cpus -info: Entering event queue @ 506044727500. Starting simulation... +info: Entering event queue @ 506044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 507044727500. Starting simulation... +info: Entering event queue @ 507044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 508044727500. Starting simulation... +info: Entering event queue @ 508044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 509044727500. Starting simulation... -info: Entering event queue @ 516044720500. Starting simulation... -info: Entering event queue @ 516044727000. Starting simulation... +info: Entering event queue @ 509044708000. Starting simulation... +info: Entering event queue @ 516044695500. Starting simulation... +info: Entering event queue @ 516044703000. Starting simulation... switching cpus -info: Entering event queue @ 516044727500. Starting simulation... +info: Entering event queue @ 516044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 517044727500. Starting simulation... +info: Entering event queue @ 517044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 518044727500. Starting simulation... +info: Entering event queue @ 518044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 519044727500. Starting simulation... -info: Entering event queue @ 526044720500. Starting simulation... -info: Entering event queue @ 526044727000. Starting simulation... +info: Entering event queue @ 519044703500. Starting simulation... switching cpus -info: Entering event queue @ 526044727500. Starting simulation... +info: Entering event queue @ 526044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 527044727500. Starting simulation... +info: Entering event queue @ 527044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 528044727500. Starting simulation... -info: Entering event queue @ 528737989000. Starting simulation... +info: Entering event queue @ 528044695500. Starting simulation... +info: Entering event queue @ 528802326000. Starting simulation... switching cpus -info: Entering event queue @ 528737991000. Starting simulation... +info: Entering event queue @ 528802328000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 529737991000. Starting simulation... -info: Entering event queue @ 536044720500. Starting simulation... -info: Entering event queue @ 536044727000. Starting simulation... +info: Entering event queue @ 529802328000. Starting simulation... switching cpus -info: Entering event queue @ 536044727500. Starting simulation... +info: Entering event queue @ 536044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 537044727500. Starting simulation... +info: Entering event queue @ 537044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 538044727500. Starting simulation... +info: Entering event queue @ 538044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 539044727500. Starting simulation... -info: Entering event queue @ 546044720500. Starting simulation... -info: Entering event queue @ 546044727000. Starting simulation... +info: Entering event queue @ 539044695500. Starting simulation... +info: Entering event queue @ 546044694500. Starting simulation... +info: Entering event queue @ 546044701500. Starting simulation... switching cpus -info: Entering event queue @ 546044727500. Starting simulation... +info: Entering event queue @ 546044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 547044727500. Starting simulation... +info: Entering event queue @ 547044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 548044727500. Starting simulation... +info: Entering event queue @ 548044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 549044727500. Starting simulation... -info: Entering event queue @ 556044720500. Starting simulation... -info: Entering event queue @ 556044727000. Starting simulation... +info: Entering event queue @ 549044706000. Starting simulation... +info: Entering event queue @ 556044695500. Starting simulation... +info: Entering event queue @ 556044703500. Starting simulation... switching cpus -info: Entering event queue @ 556044727500. Starting simulation... +info: Entering event queue @ 556044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 557044727500. Starting simulation... +info: Entering event queue @ 557044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 558044727500. Starting simulation... +info: Entering event queue @ 558044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 559044727500. Starting simulation... -info: Entering event queue @ 566044720500. Starting simulation... -info: Entering event queue @ 566044727000. Starting simulation... +info: Entering event queue @ 559044708000. Starting simulation... +info: Entering event queue @ 566044694500. Starting simulation... +info: Entering event queue @ 566044701000. Starting simulation... switching cpus -info: Entering event queue @ 566044727500. Starting simulation... +info: Entering event queue @ 566044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 567044727500. Starting simulation... +info: Entering event queue @ 567044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 568044727500. Starting simulation... +info: Entering event queue @ 568044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 569044727500. Starting simulation... -info: Entering event queue @ 576044720500. Starting simulation... -info: Entering event queue @ 576044727000. Starting simulation... +info: Entering event queue @ 569044701500. Starting simulation... +info: Entering event queue @ 576044694500. Starting simulation... +info: Entering event queue @ 576044701500. Starting simulation... switching cpus -info: Entering event queue @ 576044727500. Starting simulation... +info: Entering event queue @ 576044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 577044727500. Starting simulation... +info: Entering event queue @ 577044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 578044727500. Starting simulation... +info: Entering event queue @ 578044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 579044727500. Starting simulation... -info: Entering event queue @ 586044720500. Starting simulation... -info: Entering event queue @ 586044727000. Starting simulation... +info: Entering event queue @ 579044706000. Starting simulation... switching cpus -info: Entering event queue @ 586044727500. Starting simulation... +info: Entering event queue @ 586044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 587044727500. Starting simulation... +info: Entering event queue @ 587044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 588044727500. Starting simulation... +info: Entering event queue @ 588044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 589044727500. Starting simulation... -info: Entering event queue @ 596044720500. Starting simulation... -info: Entering event queue @ 596044727000. Starting simulation... +info: Entering event queue @ 589044695500. Starting simulation... switching cpus -info: Entering event queue @ 596044727500. Starting simulation... +info: Entering event queue @ 596044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 597044727500. Starting simulation... +info: Entering event queue @ 597044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 598044727500. Starting simulation... +info: Entering event queue @ 598044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 599044727500. Starting simulation... -info: Entering event queue @ 606044720500. Starting simulation... -info: Entering event queue @ 606044727000. Starting simulation... +info: Entering event queue @ 599044695500. Starting simulation... +info: Entering event queue @ 606044695500. Starting simulation... +info: Entering event queue @ 606044702500. Starting simulation... switching cpus -info: Entering event queue @ 606044727500. Starting simulation... +info: Entering event queue @ 606044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 607044727500. Starting simulation... +info: Entering event queue @ 607044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 608044727500. Starting simulation... +info: Entering event queue @ 608044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 609044727500. Starting simulation... -info: Entering event queue @ 616044720500. Starting simulation... -info: Entering event queue @ 616044727000. Starting simulation... +info: Entering event queue @ 609044707000. Starting simulation... +info: Entering event queue @ 616044694500. Starting simulation... +info: Entering event queue @ 616044701500. Starting simulation... switching cpus -info: Entering event queue @ 616044727500. Starting simulation... +info: Entering event queue @ 616044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 617044727500. Starting simulation... +info: Entering event queue @ 617044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 618044727500. Starting simulation... +info: Entering event queue @ 618044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 619044727500. Starting simulation... -info: Entering event queue @ 626044720500. Starting simulation... -info: Entering event queue @ 626946715000. Starting simulation... +info: Entering event queue @ 619044706000. Starting simulation... +info: Entering event queue @ 626044694500. Starting simulation... +info: Entering event queue @ 627010955000. Starting simulation... switching cpus -info: Entering event queue @ 626946717000. Starting simulation... +info: Entering event queue @ 627010957000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 627946717000. Starting simulation... +info: Entering event queue @ 628010957000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 628946717000. Starting simulation... +info: Entering event queue @ 629010957000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 629946717000. Starting simulation... -info: Entering event queue @ 636044720500. Starting simulation... -info: Entering event queue @ 636044727000. Starting simulation... +info: Entering event queue @ 630010957000. Starting simulation... +info: Entering event queue @ 636044694500. Starting simulation... +info: Entering event queue @ 636044701500. Starting simulation... switching cpus -info: Entering event queue @ 636044727500. Starting simulation... +info: Entering event queue @ 636044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 637044727500. Starting simulation... +info: Entering event queue @ 637044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 638044727500. Starting simulation... +info: Entering event queue @ 638044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 639044727500. Starting simulation... -info: Entering event queue @ 646044720500. Starting simulation... -info: Entering event queue @ 646044727000. Starting simulation... +info: Entering event queue @ 639044706000. Starting simulation... +info: Entering event queue @ 646044694500. Starting simulation... +info: Entering event queue @ 646044701500. Starting simulation... switching cpus -info: Entering event queue @ 646044727500. Starting simulation... +info: Entering event queue @ 646044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 647044727500. Starting simulation... +info: Entering event queue @ 647044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 648044727500. Starting simulation... +info: Entering event queue @ 648044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 649044727500. Starting simulation... -info: Entering event queue @ 656044720500. Starting simulation... -info: Entering event queue @ 656044727000. Starting simulation... +info: Entering event queue @ 649044706000. Starting simulation... +info: Entering event queue @ 656044695500. Starting simulation... +info: Entering event queue @ 656044702500. Starting simulation... switching cpus -info: Entering event queue @ 656044727500. Starting simulation... +info: Entering event queue @ 656044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 657044727500. Starting simulation... +info: Entering event queue @ 657044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 658044727500. Starting simulation... -info: Entering event queue @ 659682856000. Starting simulation... +info: Entering event queue @ 658044707000. Starting simulation... +info: Entering event queue @ 659746543000. Starting simulation... switching cpus -info: Entering event queue @ 659682858000. Starting simulation... +info: Entering event queue @ 659746545000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 660682858000. Starting simulation... -info: Entering event queue @ 666044720500. Starting simulation... -info: Entering event queue @ 666044727000. Starting simulation... +info: Entering event queue @ 660746545000. Starting simulation... +info: Entering event queue @ 666044694500. Starting simulation... +info: Entering event queue @ 666044701500. Starting simulation... switching cpus -info: Entering event queue @ 666044727500. Starting simulation... +info: Entering event queue @ 666044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 667044727500. Starting simulation... +info: Entering event queue @ 667044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 668044727500. Starting simulation... +info: Entering event queue @ 668044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 669044727500. Starting simulation... -info: Entering event queue @ 676044720500. Starting simulation... -info: Entering event queue @ 676044727000. Starting simulation... +info: Entering event queue @ 669044706000. Starting simulation... +info: Entering event queue @ 676044694500. Starting simulation... +info: Entering event queue @ 676044701500. Starting simulation... switching cpus -info: Entering event queue @ 676044727500. Starting simulation... +info: Entering event queue @ 676044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 677044727500. Starting simulation... +info: Entering event queue @ 677044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 678044727500. Starting simulation... +info: Entering event queue @ 678044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 679044727500. Starting simulation... -info: Entering event queue @ 686044720500. Starting simulation... -info: Entering event queue @ 686044727000. Starting simulation... +info: Entering event queue @ 679044706000. Starting simulation... +info: Entering event queue @ 686044694500. Starting simulation... +info: Entering event queue @ 686044701500. Starting simulation... switching cpus -info: Entering event queue @ 686044727500. Starting simulation... +info: Entering event queue @ 686044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 687044727500. Starting simulation... +info: Entering event queue @ 687044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 688044727500. Starting simulation... +info: Entering event queue @ 688044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 689044727500. Starting simulation... -info: Entering event queue @ 696044720500. Starting simulation... -info: Entering event queue @ 696044727000. Starting simulation... +info: Entering event queue @ 689044706000. Starting simulation... +info: Entering event queue @ 696044694500. Starting simulation... +info: Entering event queue @ 696044701500. Starting simulation... switching cpus -info: Entering event queue @ 696044727500. Starting simulation... +info: Entering event queue @ 696044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 697044727500. Starting simulation... +info: Entering event queue @ 697044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 698044727500. Starting simulation... +info: Entering event queue @ 698044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 699044727500. Starting simulation... -info: Entering event queue @ 706044720500. Starting simulation... -info: Entering event queue @ 706044727000. Starting simulation... +info: Entering event queue @ 699044706000. Starting simulation... +info: Entering event queue @ 706044695500. Starting simulation... +info: Entering event queue @ 706044702500. Starting simulation... switching cpus -info: Entering event queue @ 706044727500. Starting simulation... +info: Entering event queue @ 706044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 707044727500. Starting simulation... +info: Entering event queue @ 707044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 708044727500. Starting simulation... +info: Entering event queue @ 708044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 709044727500. Starting simulation... -info: Entering event queue @ 716044720500. Starting simulation... -info: Entering event queue @ 716044727000. Starting simulation... +info: Entering event queue @ 709044707000. Starting simulation... +info: Entering event queue @ 716044694500. Starting simulation... +info: Entering event queue @ 716044701500. Starting simulation... switching cpus -info: Entering event queue @ 716044727500. Starting simulation... +info: Entering event queue @ 716044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 717044727500. Starting simulation... +info: Entering event queue @ 717044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 718044727500. Starting simulation... +info: Entering event queue @ 718044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 719044727500. Starting simulation... -info: Entering event queue @ 726044720500. Starting simulation... -info: Entering event queue @ 726044727000. Starting simulation... +info: Entering event queue @ 719044706000. Starting simulation... +info: Entering event queue @ 726044694500. Starting simulation... +info: Entering event queue @ 726044701500. Starting simulation... switching cpus -info: Entering event queue @ 726044727500. Starting simulation... +info: Entering event queue @ 726044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 727044727500. Starting simulation... +info: Entering event queue @ 727044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 728044727500. Starting simulation... +info: Entering event queue @ 728044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 729044727500. Starting simulation... -info: Entering event queue @ 736044720500. Starting simulation... -info: Entering event queue @ 736044727000. Starting simulation... +info: Entering event queue @ 729044706000. Starting simulation... +info: Entering event queue @ 736044694500. Starting simulation... +info: Entering event queue @ 736044701000. Starting simulation... switching cpus -info: Entering event queue @ 736044727500. Starting simulation... +info: Entering event queue @ 736044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 737044727500. Starting simulation... +info: Entering event queue @ 737044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 738044727500. Starting simulation... +info: Entering event queue @ 738044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 739044727500. Starting simulation... -info: Entering event queue @ 746044720500. Starting simulation... -info: Entering event queue @ 746044727000. Starting simulation... +info: Entering event queue @ 739044701500. Starting simulation... +info: Entering event queue @ 746044694500. Starting simulation... +info: Entering event queue @ 746044701500. Starting simulation... switching cpus -info: Entering event queue @ 746044727500. Starting simulation... +info: Entering event queue @ 746044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 747044727500. Starting simulation... +info: Entering event queue @ 747044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 748044727500. Starting simulation... +info: Entering event queue @ 748044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 749044727500. Starting simulation... -info: Entering event queue @ 756044720500. Starting simulation... -info: Entering event queue @ 756044727000. Starting simulation... +info: Entering event queue @ 749044706000. Starting simulation... +info: Entering event queue @ 756044694500. Starting simulation... +info: Entering event queue @ 756044701500. Starting simulation... switching cpus -info: Entering event queue @ 756044727500. Starting simulation... +info: Entering event queue @ 756044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 757044727500. Starting simulation... +info: Entering event queue @ 757044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 758044727500. Starting simulation... +info: Entering event queue @ 758044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 759044727500. Starting simulation... -info: Entering event queue @ 766044720500. Starting simulation... -info: Entering event queue @ 766044727000. Starting simulation... +info: Entering event queue @ 759044706000. Starting simulation... +info: Entering event queue @ 766044695500. Starting simulation... +info: Entering event queue @ 766044762000. Starting simulation... switching cpus -info: Entering event queue @ 766044727500. Starting simulation... +info: Entering event queue @ 766044766500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 767044727500. Starting simulation... +info: Entering event queue @ 767044766500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 768044727500. Starting simulation... +info: Entering event queue @ 768044766500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 769044727500. Starting simulation... -info: Entering event queue @ 776044720500. Starting simulation... -info: Entering event queue @ 776044727000. Starting simulation... +info: Entering event queue @ 769044766500. Starting simulation... +info: Entering event queue @ 776044694500. Starting simulation... +info: Entering event queue @ 776044701500. Starting simulation... switching cpus -info: Entering event queue @ 776044727500. Starting simulation... +info: Entering event queue @ 776044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 777044727500. Starting simulation... +info: Entering event queue @ 777044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 778044727500. Starting simulation... +info: Entering event queue @ 778044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 779044727500. Starting simulation... -info: Entering event queue @ 786044720500. Starting simulation... -info: Entering event queue @ 786044727000. Starting simulation... +info: Entering event queue @ 779044706000. Starting simulation... +info: Entering event queue @ 786044694500. Starting simulation... +info: Entering event queue @ 786044701000. Starting simulation... switching cpus -info: Entering event queue @ 786044727500. Starting simulation... +info: Entering event queue @ 786044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 787044727500. Starting simulation... +info: Entering event queue @ 787044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 788044727500. Starting simulation... +info: Entering event queue @ 788044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 789044727500. Starting simulation... -info: Entering event queue @ 796044720500. Starting simulation... -info: Entering event queue @ 796044727000. Starting simulation... +info: Entering event queue @ 789044701500. Starting simulation... +info: Entering event queue @ 796044694500. Starting simulation... +info: Entering event queue @ 796044701500. Starting simulation... switching cpus -info: Entering event queue @ 796044727500. Starting simulation... +info: Entering event queue @ 796044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 797044727500. Starting simulation... +info: Entering event queue @ 797044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 798044727500. Starting simulation... +info: Entering event queue @ 798044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 799044727500. Starting simulation... -info: Entering event queue @ 806044720500. Starting simulation... -info: Entering event queue @ 806044727000. Starting simulation... +info: Entering event queue @ 799044706000. Starting simulation... +info: Entering event queue @ 806044694500. Starting simulation... +info: Entering event queue @ 806044701500. Starting simulation... switching cpus -info: Entering event queue @ 806044727500. Starting simulation... +info: Entering event queue @ 806044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 807044727500. Starting simulation... +info: Entering event queue @ 807044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 808044727500. Starting simulation... +info: Entering event queue @ 808044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 809044727500. Starting simulation... -info: Entering event queue @ 816044720500. Starting simulation... -info: Entering event queue @ 816044727000. Starting simulation... +info: Entering event queue @ 809044706000. Starting simulation... +info: Entering event queue @ 816044694500. Starting simulation... +info: Entering event queue @ 816044701500. Starting simulation... switching cpus -info: Entering event queue @ 816044727500. Starting simulation... +info: Entering event queue @ 816044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 817044727500. Starting simulation... +info: Entering event queue @ 817044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 818044727500. Starting simulation... +info: Entering event queue @ 818044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 819044727500. Starting simulation... -info: Entering event queue @ 826044720500. Starting simulation... -info: Entering event queue @ 826044727000. Starting simulation... +info: Entering event queue @ 819044706000. Starting simulation... +info: Entering event queue @ 826044694500. Starting simulation... +info: Entering event queue @ 826044701500. Starting simulation... switching cpus -info: Entering event queue @ 826044727500. Starting simulation... +info: Entering event queue @ 826044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 827044727500. Starting simulation... +info: Entering event queue @ 827044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 828044727500. Starting simulation... +info: Entering event queue @ 828044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 829044727500. Starting simulation... -info: Entering event queue @ 836044720500. Starting simulation... -info: Entering event queue @ 836044727000. Starting simulation... +info: Entering event queue @ 829044706000. Starting simulation... +info: Entering event queue @ 836044695500. Starting simulation... +info: Entering event queue @ 836044702500. Starting simulation... switching cpus -info: Entering event queue @ 836044727500. Starting simulation... +info: Entering event queue @ 836044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 837044727500. Starting simulation... +info: Entering event queue @ 837044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 838044727500. Starting simulation... +info: Entering event queue @ 838044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 839044727500. Starting simulation... -info: Entering event queue @ 846044720500. Starting simulation... -info: Entering event queue @ 846044727000. Starting simulation... +info: Entering event queue @ 839044707000. Starting simulation... +info: Entering event queue @ 846044695500. Starting simulation... +info: Entering event queue @ 846044703000. Starting simulation... switching cpus -info: Entering event queue @ 846044727500. Starting simulation... +info: Entering event queue @ 846044707500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 847044727500. Starting simulation... +info: Entering event queue @ 847044707500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 848044727500. Starting simulation... +info: Entering event queue @ 848044707500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 849044727500. Starting simulation... -info: Entering event queue @ 856044720500. Starting simulation... -info: Entering event queue @ 856100473000. Starting simulation... +info: Entering event queue @ 849044707500. Starting simulation... +info: Entering event queue @ 856044694500. Starting simulation... +info: Entering event queue @ 856163939000. Starting simulation... switching cpus -info: Entering event queue @ 856100475000. Starting simulation... +info: Entering event queue @ 856163941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 857100475000. Starting simulation... +info: Entering event queue @ 857163941000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 858100475000. Starting simulation... +info: Entering event queue @ 858163941000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 859100475000. Starting simulation... -info: Entering event queue @ 866044720500. Starting simulation... -info: Entering event queue @ 866044727000. Starting simulation... +info: Entering event queue @ 859163941000. Starting simulation... +info: Entering event queue @ 866044695500. Starting simulation... +info: Entering event queue @ 866044702500. Starting simulation... switching cpus -info: Entering event queue @ 866044727500. Starting simulation... +info: Entering event queue @ 866044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 867044727500. Starting simulation... +info: Entering event queue @ 867044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 868044727500. Starting simulation... +info: Entering event queue @ 868044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 869044727500. Starting simulation... -info: Entering event queue @ 876044720500. Starting simulation... -info: Entering event queue @ 876044727000. Starting simulation... +info: Entering event queue @ 869044707000. Starting simulation... +info: Entering event queue @ 876044694500. Starting simulation... +info: Entering event queue @ 876044701500. Starting simulation... switching cpus -info: Entering event queue @ 876044727500. Starting simulation... +info: Entering event queue @ 876044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 877044727500. Starting simulation... +info: Entering event queue @ 877044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 878044727500. Starting simulation... +info: Entering event queue @ 878044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 879044727500. Starting simulation... -info: Entering event queue @ 886044720500. Starting simulation... -info: Entering event queue @ 886044727000. Starting simulation... +info: Entering event queue @ 879044706000. Starting simulation... +info: Entering event queue @ 886044695500. Starting simulation... +info: Entering event queue @ 886044703500. Starting simulation... switching cpus -info: Entering event queue @ 886044727500. Starting simulation... +info: Entering event queue @ 886044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 887044727500. Starting simulation... +info: Entering event queue @ 887044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 888044727500. Starting simulation... -info: Entering event queue @ 888837073000. Starting simulation... +info: Entering event queue @ 888044708000. Starting simulation... +info: Entering event queue @ 888900518000. Starting simulation... switching cpus -info: Entering event queue @ 888837075000. Starting simulation... +info: Entering event queue @ 888900520000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 889837075000. Starting simulation... -info: Entering event queue @ 896044720500. Starting simulation... -info: Entering event queue @ 896044727000. Starting simulation... +info: Entering event queue @ 889900520000. Starting simulation... +info: Entering event queue @ 896044694500. Starting simulation... +info: Entering event queue @ 896044701000. Starting simulation... switching cpus -info: Entering event queue @ 896044727500. Starting simulation... +info: Entering event queue @ 896044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 897044727500. Starting simulation... +info: Entering event queue @ 897044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 898044727500. Starting simulation... +info: Entering event queue @ 898044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 899044727500. Starting simulation... -info: Entering event queue @ 906044720500. Starting simulation... -info: Entering event queue @ 906044727000. Starting simulation... +info: Entering event queue @ 899044701500. Starting simulation... +info: Entering event queue @ 906044694500. Starting simulation... +info: Entering event queue @ 906044701500. Starting simulation... switching cpus -info: Entering event queue @ 906044727500. Starting simulation... +info: Entering event queue @ 906044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 907044727500. Starting simulation... +info: Entering event queue @ 907044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 908044727500. Starting simulation... +info: Entering event queue @ 908044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 909044727500. Starting simulation... -info: Entering event queue @ 916044720500. Starting simulation... -info: Entering event queue @ 916044727000. Starting simulation... +info: Entering event queue @ 909044706000. Starting simulation... +info: Entering event queue @ 916044694500. Starting simulation... +info: Entering event queue @ 916044701500. Starting simulation... switching cpus -info: Entering event queue @ 916044727500. Starting simulation... +info: Entering event queue @ 916044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 917044727500. Starting simulation... +info: Entering event queue @ 917044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 918044727500. Starting simulation... +info: Entering event queue @ 918044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 919044727500. Starting simulation... -info: Entering event queue @ 926044720500. Starting simulation... -info: Entering event queue @ 926044727000. Starting simulation... +info: Entering event queue @ 919044706000. Starting simulation... +info: Entering event queue @ 926044695500. Starting simulation... +info: Entering event queue @ 926044703500. Starting simulation... switching cpus -info: Entering event queue @ 926044727500. Starting simulation... +info: Entering event queue @ 926044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 927044727500. Starting simulation... +info: Entering event queue @ 927044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 928044727500. Starting simulation... +info: Entering event queue @ 928044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 929044727500. Starting simulation... -info: Entering event queue @ 936044720500. Starting simulation... -info: Entering event queue @ 936044727000. Starting simulation... +info: Entering event queue @ 929044708000. Starting simulation... +info: Entering event queue @ 936044694500. Starting simulation... +info: Entering event queue @ 936044701500. Starting simulation... switching cpus -info: Entering event queue @ 936044727500. Starting simulation... +info: Entering event queue @ 936044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 937044727500. Starting simulation... +info: Entering event queue @ 937044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 938044727500. Starting simulation... +info: Entering event queue @ 938044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 939044727500. Starting simulation... -info: Entering event queue @ 946044720500. Starting simulation... -info: Entering event queue @ 946044727000. Starting simulation... +info: Entering event queue @ 939044706000. Starting simulation... +info: Entering event queue @ 946044694500. Starting simulation... +info: Entering event queue @ 946044701000. Starting simulation... switching cpus -info: Entering event queue @ 946044727500. Starting simulation... +info: Entering event queue @ 946044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 947044727500. Starting simulation... +info: Entering event queue @ 947044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 948044727500. Starting simulation... +info: Entering event queue @ 948044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 949044727500. Starting simulation... -info: Entering event queue @ 956044720500. Starting simulation... -info: Entering event queue @ 956044727000. Starting simulation... +info: Entering event queue @ 949044701500. Starting simulation... +info: Entering event queue @ 956044694500. Starting simulation... +info: Entering event queue @ 956044701500. Starting simulation... switching cpus -info: Entering event queue @ 956044727500. Starting simulation... +info: Entering event queue @ 956044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 957044727500. Starting simulation... +info: Entering event queue @ 957044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 958044727500. Starting simulation... +info: Entering event queue @ 958044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 959044727500. Starting simulation... -info: Entering event queue @ 966044720500. Starting simulation... -info: Entering event queue @ 966044727000. Starting simulation... +info: Entering event queue @ 959044706000. Starting simulation... +info: Entering event queue @ 966044695500. Starting simulation... +info: Entering event queue @ 966044703500. Starting simulation... switching cpus -info: Entering event queue @ 966044727500. Starting simulation... +info: Entering event queue @ 966044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 967044727500. Starting simulation... +info: Entering event queue @ 967044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 968044727500. Starting simulation... +info: Entering event queue @ 968044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 969044727500. Starting simulation... -info: Entering event queue @ 976044720500. Starting simulation... -info: Entering event queue @ 976044727000. Starting simulation... +info: Entering event queue @ 969044704000. Starting simulation... +info: Entering event queue @ 976044695500. Starting simulation... +info: Entering event queue @ 976044703500. Starting simulation... switching cpus -info: Entering event queue @ 976044727500. Starting simulation... +info: Entering event queue @ 976044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 977044727500. Starting simulation... +info: Entering event queue @ 977044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 978044727500. Starting simulation... +info: Entering event queue @ 978044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 979044727500. Starting simulation... -info: Entering event queue @ 986044720500. Starting simulation... -info: Entering event queue @ 987045796000. Starting simulation... +info: Entering event queue @ 979044704000. Starting simulation... +info: Entering event queue @ 986044694500. Starting simulation... +info: Entering event queue @ 987109151000. Starting simulation... switching cpus -info: Entering event queue @ 987045798000. Starting simulation... +info: Entering event queue @ 987109153000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 988045798000. Starting simulation... +info: Entering event queue @ 988109153000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 989045798000. Starting simulation... +info: Entering event queue @ 989109153000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 990045798000. Starting simulation... -info: Entering event queue @ 996044720500. Starting simulation... -info: Entering event queue @ 996044727000. Starting simulation... +info: Entering event queue @ 990109153000. Starting simulation... +info: Entering event queue @ 996044695500. Starting simulation... +info: Entering event queue @ 996044702500. Starting simulation... switching cpus -info: Entering event queue @ 996044727500. Starting simulation... +info: Entering event queue @ 996044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 997044727500. Starting simulation... +info: Entering event queue @ 997044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 998044727500. Starting simulation... +info: Entering event queue @ 998044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 999044727500. Starting simulation... -info: Entering event queue @ 1006044720500. Starting simulation... -info: Entering event queue @ 1006044727000. Starting simulation... +info: Entering event queue @ 999044707000. Starting simulation... switching cpus -info: Entering event queue @ 1006044727500. Starting simulation... +info: Entering event queue @ 1006044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1007044727500. Starting simulation... +info: Entering event queue @ 1007044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1008044727500. Starting simulation... +info: Entering event queue @ 1008044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1009044727500. Starting simulation... -info: Entering event queue @ 1016044720500. Starting simulation... -info: Entering event queue @ 1016044727000. Starting simulation... +info: Entering event queue @ 1009044695500. Starting simulation... +info: Entering event queue @ 1016044694500. Starting simulation... +info: Entering event queue @ 1016044701500. Starting simulation... switching cpus -info: Entering event queue @ 1016044727500. Starting simulation... +info: Entering event queue @ 1016044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1017044727500. Starting simulation... +info: Entering event queue @ 1017044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1018044727500. Starting simulation... +info: Entering event queue @ 1018044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1019044727500. Starting simulation... -info: Entering event queue @ 1026044720500. Starting simulation... -info: Entering event queue @ 1026044727000. Starting simulation... +info: Entering event queue @ 1019044706000. Starting simulation... +info: Entering event queue @ 1026044695500. Starting simulation... +info: Entering event queue @ 1026044703500. Starting simulation... switching cpus -info: Entering event queue @ 1026044727500. Starting simulation... +info: Entering event queue @ 1026044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1027044727500. Starting simulation... +info: Entering event queue @ 1027044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1028044727500. Starting simulation... +info: Entering event queue @ 1028044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1029044727500. Starting simulation... -info: Entering event queue @ 1036044720500. Starting simulation... -info: Entering event queue @ 1036044727000. Starting simulation... +info: Entering event queue @ 1029044708000. Starting simulation... switching cpus -info: Entering event queue @ 1036044727500. Starting simulation... +info: Entering event queue @ 1036044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1037044727500. Starting simulation... +info: Entering event queue @ 1037044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1038044727500. Starting simulation... +info: Entering event queue @ 1038044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1039044727500. Starting simulation... -info: Entering event queue @ 1046044720500. Starting simulation... -info: Entering event queue @ 1046044727000. Starting simulation... +info: Entering event queue @ 1039044695500. Starting simulation... +info: Entering event queue @ 1046044694500. Starting simulation... +info: Entering event queue @ 1046044701500. Starting simulation... switching cpus -info: Entering event queue @ 1046044727500. Starting simulation... +info: Entering event queue @ 1046044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1047044727500. Starting simulation... +info: Entering event queue @ 1047044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1048044727500. Starting simulation... +info: Entering event queue @ 1048044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1049044727500. Starting simulation... -info: Entering event queue @ 1056044720500. Starting simulation... -info: Entering event queue @ 1056044727000. Starting simulation... +info: Entering event queue @ 1049044706000. Starting simulation... +info: Entering event queue @ 1056044694500. Starting simulation... +info: Entering event queue @ 1056044701500. Starting simulation... switching cpus -info: Entering event queue @ 1056044727500. Starting simulation... +info: Entering event queue @ 1056044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1057044727500. Starting simulation... +info: Entering event queue @ 1057044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1058044727500. Starting simulation... +info: Entering event queue @ 1058044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1059044727500. Starting simulation... -info: Entering event queue @ 1066044720500. Starting simulation... -info: Entering event queue @ 1066044727000. Starting simulation... +info: Entering event queue @ 1059044706000. Starting simulation... +info: Entering event queue @ 1066044694500. Starting simulation... +info: Entering event queue @ 1066044701000. Starting simulation... switching cpus -info: Entering event queue @ 1066044727500. Starting simulation... +info: Entering event queue @ 1066044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1067044727500. Starting simulation... +info: Entering event queue @ 1067044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1068044727500. Starting simulation... +info: Entering event queue @ 1068044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1069044727500. Starting simulation... -info: Entering event queue @ 1076044720500. Starting simulation... -info: Entering event queue @ 1076044727000. Starting simulation... +info: Entering event queue @ 1069044701500. Starting simulation... +info: Entering event queue @ 1076044694500. Starting simulation... +info: Entering event queue @ 1076044701500. Starting simulation... switching cpus -info: Entering event queue @ 1076044727500. Starting simulation... +info: Entering event queue @ 1076044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1077044727500. Starting simulation... +info: Entering event queue @ 1077044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1078044727500. Starting simulation... +info: Entering event queue @ 1078044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1079044727500. Starting simulation... -info: Entering event queue @ 1086044720500. Starting simulation... -info: Entering event queue @ 1086044727000. Starting simulation... +info: Entering event queue @ 1079044706000. Starting simulation... +info: Entering event queue @ 1086044694500. Starting simulation... +info: Entering event queue @ 1086044701500. Starting simulation... switching cpus -info: Entering event queue @ 1086044727500. Starting simulation... +info: Entering event queue @ 1086044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1087044727500. Starting simulation... +info: Entering event queue @ 1087044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1088044727500. Starting simulation... +info: Entering event queue @ 1088044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1089044727500. Starting simulation... -info: Entering event queue @ 1096044720500. Starting simulation... -info: Entering event queue @ 1096044727000. Starting simulation... +info: Entering event queue @ 1089044706000. Starting simulation... +info: Entering event queue @ 1096044695500. Starting simulation... +info: Entering event queue @ 1096044703500. Starting simulation... switching cpus -info: Entering event queue @ 1096044727500. Starting simulation... +info: Entering event queue @ 1096044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1097044727500. Starting simulation... +info: Entering event queue @ 1097044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1098044727500. Starting simulation... +info: Entering event queue @ 1098044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1099044727500. Starting simulation... -info: Entering event queue @ 1106044720500. Starting simulation... -info: Entering event queue @ 1106044727000. Starting simulation... +info: Entering event queue @ 1099044708000. Starting simulation... +info: Entering event queue @ 1106044694500. Starting simulation... +info: Entering event queue @ 1106044701500. Starting simulation... switching cpus -info: Entering event queue @ 1106044727500. Starting simulation... +info: Entering event queue @ 1106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1107044727500. Starting simulation... +info: Entering event queue @ 1107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1108044727500. Starting simulation... +info: Entering event queue @ 1108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1109044727500. Starting simulation... -info: Entering event queue @ 1116044720500. Starting simulation... -info: Entering event queue @ 1116044727000. Starting simulation... +info: Entering event queue @ 1109044706000. Starting simulation... +info: Entering event queue @ 1116044694500. Starting simulation... +info: Entering event queue @ 1116044701000. Starting simulation... switching cpus -info: Entering event queue @ 1116044727500. Starting simulation... +info: Entering event queue @ 1116044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1117044727500. Starting simulation... +info: Entering event queue @ 1117044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1118044727500. Starting simulation... +info: Entering event queue @ 1118044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1119044727500. Starting simulation... -info: Entering event queue @ 1126044720500. Starting simulation... -info: Entering event queue @ 1126044727000. Starting simulation... +info: Entering event queue @ 1119044701500. Starting simulation... +info: Entering event queue @ 1126044694500. Starting simulation... +info: Entering event queue @ 1126044701500. Starting simulation... switching cpus -info: Entering event queue @ 1126044727500. Starting simulation... +info: Entering event queue @ 1126044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1127044727500. Starting simulation... +info: Entering event queue @ 1127044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1128044727500. Starting simulation... +info: Entering event queue @ 1128044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1129044727500. Starting simulation... -info: Entering event queue @ 1136044720500. Starting simulation... -info: Entering event queue @ 1136044727000. Starting simulation... +info: Entering event queue @ 1129044706000. Starting simulation... +info: Entering event queue @ 1136044695500. Starting simulation... +info: Entering event queue @ 1136044702500. Starting simulation... switching cpus -info: Entering event queue @ 1136044727500. Starting simulation... +info: Entering event queue @ 1136044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1137044727500. Starting simulation... +info: Entering event queue @ 1137044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1138044727500. Starting simulation... +info: Entering event queue @ 1138044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1139044727500. Starting simulation... -info: Entering event queue @ 1146044720500. Starting simulation... -info: Entering event queue @ 1146044727000. Starting simulation... +info: Entering event queue @ 1139044707000. Starting simulation... +info: Entering event queue @ 1146044694500. Starting simulation... +info: Entering event queue @ 1146044701500. Starting simulation... switching cpus -info: Entering event queue @ 1146044727500. Starting simulation... +info: Entering event queue @ 1146044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1147044727500. Starting simulation... +info: Entering event queue @ 1147044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1148044727500. Starting simulation... +info: Entering event queue @ 1148044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1149044727500. Starting simulation... -info: Entering event queue @ 1156044720500. Starting simulation... -info: Entering event queue @ 1156044727000. Starting simulation... +info: Entering event queue @ 1149044706000. Starting simulation... +info: Entering event queue @ 1156044694500. Starting simulation... +info: Entering event queue @ 1156044701500. Starting simulation... switching cpus -info: Entering event queue @ 1156044727500. Starting simulation... +info: Entering event queue @ 1156044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1157044727500. Starting simulation... +info: Entering event queue @ 1157044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1158044727500. Starting simulation... +info: Entering event queue @ 1158044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1159044727500. Starting simulation... -info: Entering event queue @ 1166044720500. Starting simulation... -info: Entering event queue @ 1166044727000. Starting simulation... +info: Entering event queue @ 1159044706000. Starting simulation... +info: Entering event queue @ 1166044695500. Starting simulation... +info: Entering event queue @ 1166044704000. Starting simulation... switching cpus -info: Entering event queue @ 1166044727500. Starting simulation... +info: Entering event queue @ 1166044708500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1167044727500. Starting simulation... +info: Entering event queue @ 1167044708500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1168044727500. Starting simulation... +info: Entering event queue @ 1168044708500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1169044727500. Starting simulation... -info: Entering event queue @ 1176044720500. Starting simulation... -info: Entering event queue @ 1176044727000. Starting simulation... +info: Entering event queue @ 1169044708500. Starting simulation... switching cpus -info: Entering event queue @ 1176044727500. Starting simulation... +info: Entering event queue @ 1176044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1177044727500. Starting simulation... +info: Entering event queue @ 1177044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1178044727500. Starting simulation... +info: Entering event queue @ 1178044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1179044727500. Starting simulation... -info: Entering event queue @ 1186044720500. Starting simulation... -info: Entering event queue @ 1186044727000. Starting simulation... +info: Entering event queue @ 1179044695500. Starting simulation... switching cpus -info: Entering event queue @ 1186044727500. Starting simulation... +info: Entering event queue @ 1186044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1187044727500. Starting simulation... +info: Entering event queue @ 1187044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1188044727500. Starting simulation... +info: Entering event queue @ 1188044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1189044727500. Starting simulation... -info: Entering event queue @ 1196044720500. Starting simulation... -info: Entering event queue @ 1196044727000. Starting simulation... +info: Entering event queue @ 1189044695500. Starting simulation... switching cpus -info: Entering event queue @ 1196044727500. Starting simulation... +info: Entering event queue @ 1196044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1197044727500. Starting simulation... +info: Entering event queue @ 1197044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1198044727500. Starting simulation... +info: Entering event queue @ 1198044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1199044727500. Starting simulation... -info: Entering event queue @ 1206044720500. Starting simulation... -info: Entering event queue @ 1206044727000. Starting simulation... +info: Entering event queue @ 1199044695500. Starting simulation... +info: Entering event queue @ 1206044694500. Starting simulation... +info: Entering event queue @ 1206044701500. Starting simulation... switching cpus -info: Entering event queue @ 1206044727500. Starting simulation... +info: Entering event queue @ 1206044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1207044727500. Starting simulation... +info: Entering event queue @ 1207044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1208044727500. Starting simulation... +info: Entering event queue @ 1208044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1209044727500. Starting simulation... -info: Entering event queue @ 1216044720500. Starting simulation... -info: Entering event queue @ 1216199554000. Starting simulation... +info: Entering event queue @ 1209044706000. Starting simulation... +info: Entering event queue @ 1216044695500. Starting simulation... +info: Entering event queue @ 1216263126000. Starting simulation... switching cpus -info: Entering event queue @ 1216199556000. Starting simulation... +info: Entering event queue @ 1216263128000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1217199556000. Starting simulation... +info: Entering event queue @ 1217263128000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1218199556000. Starting simulation... +info: Entering event queue @ 1218263128000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1219199556000. Starting simulation... -info: Entering event queue @ 1226044720500. Starting simulation... -info: Entering event queue @ 1226044727000. Starting simulation... +info: Entering event queue @ 1219263128000. Starting simulation... +info: Entering event queue @ 1226044694500. Starting simulation... +info: Entering event queue @ 1226044701000. Starting simulation... switching cpus -info: Entering event queue @ 1226044727500. Starting simulation... +info: Entering event queue @ 1226044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1227044727500. Starting simulation... +info: Entering event queue @ 1227044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1228044727500. Starting simulation... +info: Entering event queue @ 1228044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1229044727500. Starting simulation... -info: Entering event queue @ 1236044720500. Starting simulation... -info: Entering event queue @ 1236044727000. Starting simulation... +info: Entering event queue @ 1229044701500. Starting simulation... +info: Entering event queue @ 1236044694500. Starting simulation... +info: Entering event queue @ 1236044701500. Starting simulation... switching cpus -info: Entering event queue @ 1236044727500. Starting simulation... +info: Entering event queue @ 1236044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1237044727500. Starting simulation... +info: Entering event queue @ 1237044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1238044727500. Starting simulation... +info: Entering event queue @ 1238044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1239044727500. Starting simulation... -info: Entering event queue @ 1246044720500. Starting simulation... -info: Entering event queue @ 1246044727000. Starting simulation... +info: Entering event queue @ 1239044706000. Starting simulation... +info: Entering event queue @ 1246044694500. Starting simulation... +info: Entering event queue @ 1246044701500. Starting simulation... switching cpus -info: Entering event queue @ 1246044727500. Starting simulation... +info: Entering event queue @ 1246044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1247044727500. Starting simulation... +info: Entering event queue @ 1247044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1248044727500. Starting simulation... -info: Entering event queue @ 1248935845000. Starting simulation... +info: Entering event queue @ 1248044706000. Starting simulation... +info: Entering event queue @ 1248999726000. Starting simulation... switching cpus -info: Entering event queue @ 1248935847000. Starting simulation... +info: Entering event queue @ 1248999728000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1249935847000. Starting simulation... -info: Entering event queue @ 1256044720500. Starting simulation... -info: Entering event queue @ 1256044727000. Starting simulation... +info: Entering event queue @ 1249999728000. Starting simulation... +info: Entering event queue @ 1256044695500. Starting simulation... +info: Entering event queue @ 1256044703500. Starting simulation... switching cpus -info: Entering event queue @ 1256044727500. Starting simulation... +info: Entering event queue @ 1256044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1257044727500. Starting simulation... +info: Entering event queue @ 1257044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1258044727500. Starting simulation... +info: Entering event queue @ 1258044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1259044727500. Starting simulation... -info: Entering event queue @ 1266044720500. Starting simulation... -info: Entering event queue @ 1266044727000. Starting simulation... +info: Entering event queue @ 1259044708000. Starting simulation... +info: Entering event queue @ 1266044694500. Starting simulation... +info: Entering event queue @ 1266044701500. Starting simulation... switching cpus -info: Entering event queue @ 1266044727500. Starting simulation... +info: Entering event queue @ 1266044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1267044727500. Starting simulation... +info: Entering event queue @ 1267044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1268044727500. Starting simulation... +info: Entering event queue @ 1268044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1269044727500. Starting simulation... -info: Entering event queue @ 1276044720500. Starting simulation... -info: Entering event queue @ 1276044727000. Starting simulation... +info: Entering event queue @ 1269044706000. Starting simulation... +info: Entering event queue @ 1276044694500. Starting simulation... +info: Entering event queue @ 1276044701000. Starting simulation... switching cpus -info: Entering event queue @ 1276044727500. Starting simulation... +info: Entering event queue @ 1276044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1277044727500. Starting simulation... +info: Entering event queue @ 1277044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1278044727500. Starting simulation... +info: Entering event queue @ 1278044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1279044727500. Starting simulation... -info: Entering event queue @ 1286044720500. Starting simulation... -info: Entering event queue @ 1286044727000. Starting simulation... +info: Entering event queue @ 1279044701500. Starting simulation... +info: Entering event queue @ 1286044694500. Starting simulation... +info: Entering event queue @ 1286044701500. Starting simulation... switching cpus -info: Entering event queue @ 1286044727500. Starting simulation... +info: Entering event queue @ 1286044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1287044727500. Starting simulation... +info: Entering event queue @ 1287044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1288044727500. Starting simulation... +info: Entering event queue @ 1288044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1289044727500. Starting simulation... -info: Entering event queue @ 1296044720500. Starting simulation... -info: Entering event queue @ 1296044727000. Starting simulation... +info: Entering event queue @ 1289044706000. Starting simulation... +info: Entering event queue @ 1296044695500. Starting simulation... +info: Entering event queue @ 1296044702500. Starting simulation... switching cpus -info: Entering event queue @ 1296044727500. Starting simulation... +info: Entering event queue @ 1296044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1297044727500. Starting simulation... +info: Entering event queue @ 1297044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1298044727500. Starting simulation... +info: Entering event queue @ 1298044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1299044727500. Starting simulation... -info: Entering event queue @ 1306044720500. Starting simulation... -info: Entering event queue @ 1306044727000. Starting simulation... +info: Entering event queue @ 1299044707000. Starting simulation... +info: Entering event queue @ 1306044694500. Starting simulation... +info: Entering event queue @ 1306044701500. Starting simulation... switching cpus -info: Entering event queue @ 1306044727500. Starting simulation... +info: Entering event queue @ 1306044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1307044727500. Starting simulation... +info: Entering event queue @ 1307044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1308044727500. Starting simulation... +info: Entering event queue @ 1308044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1309044727500. Starting simulation... -info: Entering event queue @ 1316044720500. Starting simulation... -info: Entering event queue @ 1316044727000. Starting simulation... +info: Entering event queue @ 1309044706000. Starting simulation... +info: Entering event queue @ 1316044694500. Starting simulation... +info: Entering event queue @ 1316044701500. Starting simulation... switching cpus -info: Entering event queue @ 1316044727500. Starting simulation... +info: Entering event queue @ 1316044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1317044727500. Starting simulation... +info: Entering event queue @ 1317044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1318044727500. Starting simulation... +info: Entering event queue @ 1318044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1319044727500. Starting simulation... -info: Entering event queue @ 1326044720500. Starting simulation... -info: Entering event queue @ 1326044727000. Starting simulation... +info: Entering event queue @ 1319044706000. Starting simulation... +info: Entering event queue @ 1326044695500. Starting simulation... +info: Entering event queue @ 1326044702500. Starting simulation... switching cpus -info: Entering event queue @ 1326044727500. Starting simulation... +info: Entering event queue @ 1326044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1327044727500. Starting simulation... +info: Entering event queue @ 1327044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1328044727500. Starting simulation... +info: Entering event queue @ 1328044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1329044727500. Starting simulation... -info: Entering event queue @ 1336044720500. Starting simulation... -info: Entering event queue @ 1336044727000. Starting simulation... +info: Entering event queue @ 1329044707000. Starting simulation... +info: Entering event queue @ 1336044695500. Starting simulation... +info: Entering event queue @ 1336044702500. Starting simulation... switching cpus -info: Entering event queue @ 1336044727500. Starting simulation... +info: Entering event queue @ 1336044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1337044727500. Starting simulation... +info: Entering event queue @ 1337044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1338044727500. Starting simulation... +info: Entering event queue @ 1338044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1339044727500. Starting simulation... -info: Entering event queue @ 1346044720500. Starting simulation... -info: Entering event queue @ 1347144421000. Starting simulation... +info: Entering event queue @ 1339044707000. Starting simulation... +info: Entering event queue @ 1346044695500. Starting simulation... +info: Entering event queue @ 1347208355000. Starting simulation... switching cpus -info: Entering event queue @ 1347144423000. Starting simulation... +info: Entering event queue @ 1347208357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1348144423000. Starting simulation... +info: Entering event queue @ 1348208357000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1349144423000. Starting simulation... +info: Entering event queue @ 1349208357000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1350144423000. Starting simulation... -info: Entering event queue @ 1356044720500. Starting simulation... -info: Entering event queue @ 1356044727000. Starting simulation... +info: Entering event queue @ 1350208357000. Starting simulation... switching cpus -info: Entering event queue @ 1356044727500. Starting simulation... +info: Entering event queue @ 1356044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1357044727500. Starting simulation... +info: Entering event queue @ 1357044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1358044727500. Starting simulation... +info: Entering event queue @ 1358044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1359044727500. Starting simulation... -info: Entering event queue @ 1366044720500. Starting simulation... -info: Entering event queue @ 1366044727000. Starting simulation... +info: Entering event queue @ 1359044695500. Starting simulation... +info: Entering event queue @ 1366044694500. Starting simulation... +info: Entering event queue @ 1366044701500. Starting simulation... switching cpus -info: Entering event queue @ 1366044727500. Starting simulation... +info: Entering event queue @ 1366044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1367044727500. Starting simulation... +info: Entering event queue @ 1367044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1368044727500. Starting simulation... +info: Entering event queue @ 1368044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1369044727500. Starting simulation... -info: Entering event queue @ 1376044720500. Starting simulation... -info: Entering event queue @ 1376044727000. Starting simulation... +info: Entering event queue @ 1369044706000. Starting simulation... +info: Entering event queue @ 1376044695500. Starting simulation... +info: Entering event queue @ 1376044703500. Starting simulation... switching cpus -info: Entering event queue @ 1376044727500. Starting simulation... +info: Entering event queue @ 1376044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1377044727500. Starting simulation... +info: Entering event queue @ 1377044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1378044727500. Starting simulation... +info: Entering event queue @ 1378044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1379044727500. Starting simulation... -info: Entering event queue @ 1386044720500. Starting simulation... -info: Entering event queue @ 1386044727000. Starting simulation... +info: Entering event queue @ 1379044708000. Starting simulation... +info: Entering event queue @ 1386044694500. Starting simulation... +info: Entering event queue @ 1386044701000. Starting simulation... switching cpus -info: Entering event queue @ 1386044727500. Starting simulation... +info: Entering event queue @ 1386044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1387044727500. Starting simulation... +info: Entering event queue @ 1387044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1388044727500. Starting simulation... +info: Entering event queue @ 1388044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1389044727500. Starting simulation... -info: Entering event queue @ 1396044720500. Starting simulation... -info: Entering event queue @ 1396044727000. Starting simulation... +info: Entering event queue @ 1389044701500. Starting simulation... +info: Entering event queue @ 1396044694500. Starting simulation... +info: Entering event queue @ 1396044701500. Starting simulation... switching cpus -info: Entering event queue @ 1396044727500. Starting simulation... +info: Entering event queue @ 1396044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1397044727500. Starting simulation... +info: Entering event queue @ 1397044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1398044727500. Starting simulation... +info: Entering event queue @ 1398044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1399044727500. Starting simulation... -info: Entering event queue @ 1406044720500. Starting simulation... -info: Entering event queue @ 1406044727000. Starting simulation... +info: Entering event queue @ 1399044706000. Starting simulation... switching cpus -info: Entering event queue @ 1406044727500. Starting simulation... +info: Entering event queue @ 1406044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1407044727500. Starting simulation... +info: Entering event queue @ 1407044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1408044727500. Starting simulation... +info: Entering event queue @ 1408044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1409044727500. Starting simulation... -info: Entering event queue @ 1416044720500. Starting simulation... -info: Entering event queue @ 1416044727000. Starting simulation... +info: Entering event queue @ 1409044695500. Starting simulation... +info: Entering event queue @ 1416044694500. Starting simulation... +info: Entering event queue @ 1416044701500. Starting simulation... switching cpus -info: Entering event queue @ 1416044727500. Starting simulation... +info: Entering event queue @ 1416044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1417044727500. Starting simulation... +info: Entering event queue @ 1417044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1418044727500. Starting simulation... +info: Entering event queue @ 1418044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1419044727500. Starting simulation... -info: Entering event queue @ 1426044720500. Starting simulation... -info: Entering event queue @ 1426044727000. Starting simulation... +info: Entering event queue @ 1419044706000. Starting simulation... +info: Entering event queue @ 1426044694500. Starting simulation... +info: Entering event queue @ 1426044701500. Starting simulation... switching cpus -info: Entering event queue @ 1426044727500. Starting simulation... +info: Entering event queue @ 1426044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1427044727500. Starting simulation... +info: Entering event queue @ 1427044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1428044727500. Starting simulation... +info: Entering event queue @ 1428044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1429044727500. Starting simulation... -info: Entering event queue @ 1436044720500. Starting simulation... -info: Entering event queue @ 1436044727000. Starting simulation... +info: Entering event queue @ 1429044706000. Starting simulation... +info: Entering event queue @ 1436044694500. Starting simulation... +info: Entering event queue @ 1436044701000. Starting simulation... switching cpus -info: Entering event queue @ 1436044727500. Starting simulation... +info: Entering event queue @ 1436044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1437044727500. Starting simulation... +info: Entering event queue @ 1437044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1438044727500. Starting simulation... +info: Entering event queue @ 1438044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1439044727500. Starting simulation... -info: Entering event queue @ 1446044720500. Starting simulation... -info: Entering event queue @ 1446044727000. Starting simulation... +info: Entering event queue @ 1439044701500. Starting simulation... +info: Entering event queue @ 1446044694500. Starting simulation... +info: Entering event queue @ 1446044701500. Starting simulation... switching cpus -info: Entering event queue @ 1446044727500. Starting simulation... +info: Entering event queue @ 1446044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1447044727500. Starting simulation... +info: Entering event queue @ 1447044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1448044727500. Starting simulation... +info: Entering event queue @ 1448044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1449044727500. Starting simulation... -info: Entering event queue @ 1456044720500. Starting simulation... -info: Entering event queue @ 1456044727000. Starting simulation... +info: Entering event queue @ 1449044706000. Starting simulation... +info: Entering event queue @ 1456044695500. Starting simulation... +info: Entering event queue @ 1456044702500. Starting simulation... switching cpus -info: Entering event queue @ 1456044727500. Starting simulation... +info: Entering event queue @ 1456044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1457044727500. Starting simulation... +info: Entering event queue @ 1457044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1458044727500. Starting simulation... +info: Entering event queue @ 1458044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1459044727500. Starting simulation... -info: Entering event queue @ 1466044720500. Starting simulation... -info: Entering event queue @ 1466044727000. Starting simulation... +info: Entering event queue @ 1459044707000. Starting simulation... +info: Entering event queue @ 1466044694500. Starting simulation... +info: Entering event queue @ 1466044701500. Starting simulation... switching cpus -info: Entering event queue @ 1466044727500. Starting simulation... +info: Entering event queue @ 1466044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1467044727500. Starting simulation... +info: Entering event queue @ 1467044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1468044727500. Starting simulation... +info: Entering event queue @ 1468044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1469044727500. Starting simulation... -info: Entering event queue @ 1476044720500. Starting simulation... -info: Entering event queue @ 1476044727000. Starting simulation... +info: Entering event queue @ 1469044706000. Starting simulation... +info: Entering event queue @ 1476044694500. Starting simulation... +info: Entering event queue @ 1476044701500. Starting simulation... switching cpus -info: Entering event queue @ 1476044727500. Starting simulation... +info: Entering event queue @ 1476044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1477044727500. Starting simulation... +info: Entering event queue @ 1477044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1478044727500. Starting simulation... +info: Entering event queue @ 1478044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1479044727500. Starting simulation... -info: Entering event queue @ 1486044720500. Starting simulation... -info: Entering event queue @ 1486044727000. Starting simulation... +info: Entering event queue @ 1479044706000. Starting simulation... +info: Entering event queue @ 1486044695500. Starting simulation... +info: Entering event queue @ 1486044702500. Starting simulation... switching cpus -info: Entering event queue @ 1486044727500. Starting simulation... +info: Entering event queue @ 1486044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1487044727500. Starting simulation... +info: Entering event queue @ 1487044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1488044727500. Starting simulation... +info: Entering event queue @ 1488044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1489044727500. Starting simulation... -info: Entering event queue @ 1496044720500. Starting simulation... -info: Entering event queue @ 1496044727000. Starting simulation... +info: Entering event queue @ 1489044707000. Starting simulation... +info: Entering event queue @ 1496044695500. Starting simulation... +info: Entering event queue @ 1496044702500. Starting simulation... switching cpus -info: Entering event queue @ 1496044727500. Starting simulation... +info: Entering event queue @ 1496044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1497044727500. Starting simulation... +info: Entering event queue @ 1497044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1498044727500. Starting simulation... +info: Entering event queue @ 1498044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1499044727500. Starting simulation... -info: Entering event queue @ 1506044720500. Starting simulation... -info: Entering event queue @ 1506044727000. Starting simulation... +info: Entering event queue @ 1499044707000. Starting simulation... switching cpus -info: Entering event queue @ 1506044727500. Starting simulation... +info: Entering event queue @ 1506044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1507044727500. Starting simulation... +info: Entering event queue @ 1507044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1508044727500. Starting simulation... +info: Entering event queue @ 1508044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1509044727500. Starting simulation... -info: Entering event queue @ 1516044720500. Starting simulation... -info: Entering event queue @ 1516044727000. Starting simulation... +info: Entering event queue @ 1509044695500. Starting simulation... switching cpus -info: Entering event queue @ 1516044727500. Starting simulation... +info: Entering event queue @ 1516044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1517044727500. Starting simulation... +info: Entering event queue @ 1517044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1518044727500. Starting simulation... +info: Entering event queue @ 1518044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1519044727500. Starting simulation... -info: Entering event queue @ 1526044720500. Starting simulation... -info: Entering event queue @ 1526044727000. Starting simulation... +info: Entering event queue @ 1519044695500. Starting simulation... +info: Entering event queue @ 1526044694500. Starting simulation... +info: Entering event queue @ 1526044701500. Starting simulation... switching cpus -info: Entering event queue @ 1526044727500. Starting simulation... +info: Entering event queue @ 1526044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1527044727500. Starting simulation... +info: Entering event queue @ 1527044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1528044727500. Starting simulation... +info: Entering event queue @ 1528044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1529044727500. Starting simulation... -info: Entering event queue @ 1536044720500. Starting simulation... -info: Entering event queue @ 1536044727000. Starting simulation... +info: Entering event queue @ 1529044706000. Starting simulation... +info: Entering event queue @ 1536044695500. Starting simulation... +info: Entering event queue @ 1536044703500. Starting simulation... switching cpus -info: Entering event queue @ 1536044727500. Starting simulation... +info: Entering event queue @ 1536044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1537044727500. Starting simulation... +info: Entering event queue @ 1537044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1538044727500. Starting simulation... +info: Entering event queue @ 1538044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1539044727500. Starting simulation... -info: Entering event queue @ 1546044720500. Starting simulation... -info: Entering event queue @ 1546044727000. Starting simulation... +info: Entering event queue @ 1539044708000. Starting simulation... +info: Entering event queue @ 1546044694500. Starting simulation... +info: Entering event queue @ 1546044701000. Starting simulation... switching cpus -info: Entering event queue @ 1546044727500. Starting simulation... +info: Entering event queue @ 1546044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1547044727500. Starting simulation... +info: Entering event queue @ 1547044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1548044727500. Starting simulation... +info: Entering event queue @ 1548044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1549044727500. Starting simulation... -info: Entering event queue @ 1556044720500. Starting simulation... -info: Entering event queue @ 1556044727000. Starting simulation... +info: Entering event queue @ 1549044701500. Starting simulation... +info: Entering event queue @ 1556044694500. Starting simulation... +info: Entering event queue @ 1556044701500. Starting simulation... switching cpus -info: Entering event queue @ 1556044727500. Starting simulation... +info: Entering event queue @ 1556044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1557044727500. Starting simulation... +info: Entering event queue @ 1557044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1558044727500. Starting simulation... +info: Entering event queue @ 1558044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1559044727500. Starting simulation... -info: Entering event queue @ 1566044720500. Starting simulation... -info: Entering event queue @ 1566044727000. Starting simulation... +info: Entering event queue @ 1559044706000. Starting simulation... +info: Entering event queue @ 1566044695500. Starting simulation... +info: Entering event queue @ 1566044703500. Starting simulation... switching cpus -info: Entering event queue @ 1566044727500. Starting simulation... +info: Entering event queue @ 1566044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1567044727500. Starting simulation... +info: Entering event queue @ 1567044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1568044727500. Starting simulation... +info: Entering event queue @ 1568044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1569044727500. Starting simulation... -info: Entering event queue @ 1576044720500. Starting simulation... -info: Entering event queue @ 1576298326000. Starting simulation... +info: Entering event queue @ 1569044708000. Starting simulation... +info: Entering event queue @ 1576044695500. Starting simulation... +info: Entering event queue @ 1576362334000. Starting simulation... switching cpus -info: Entering event queue @ 1576298328000. Starting simulation... +info: Entering event queue @ 1576362336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1577298328000. Starting simulation... +info: Entering event queue @ 1577362336000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1578298328000. Starting simulation... +info: Entering event queue @ 1578362336000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1579298328000. Starting simulation... -info: Entering event queue @ 1586044720500. Starting simulation... -info: Entering event queue @ 1586044727000. Starting simulation... +info: Entering event queue @ 1579362336000. Starting simulation... +info: Entering event queue @ 1586044695500. Starting simulation... +info: Entering event queue @ 1586044703500. Starting simulation... switching cpus -info: Entering event queue @ 1586044727500. Starting simulation... +info: Entering event queue @ 1586044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1587044727500. Starting simulation... +info: Entering event queue @ 1587044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1588044727500. Starting simulation... +info: Entering event queue @ 1588044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1589044727500. Starting simulation... -info: Entering event queue @ 1596044720500. Starting simulation... -info: Entering event queue @ 1596044727000. Starting simulation... +info: Entering event queue @ 1589044708000. Starting simulation... +info: Entering event queue @ 1596044694500. Starting simulation... +info: Entering event queue @ 1596044701000. Starting simulation... switching cpus -info: Entering event queue @ 1596044727500. Starting simulation... +info: Entering event queue @ 1596044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1597044727500. Starting simulation... +info: Entering event queue @ 1597044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1598044727500. Starting simulation... +info: Entering event queue @ 1598044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1599044727500. Starting simulation... -info: Entering event queue @ 1606044720500. Starting simulation... -info: Entering event queue @ 1606044727000. Starting simulation... +info: Entering event queue @ 1599044701500. Starting simulation... +info: Entering event queue @ 1606044695500. Starting simulation... +info: Entering event queue @ 1606044703000. Starting simulation... switching cpus -info: Entering event queue @ 1606044727500. Starting simulation... +info: Entering event queue @ 1606044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1607044727500. Starting simulation... +info: Entering event queue @ 1607044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1608044727500. Starting simulation... -info: Entering event queue @ 1609034473000. Starting simulation... +info: Entering event queue @ 1608044703500. Starting simulation... +info: Entering event queue @ 1609097918000. Starting simulation... switching cpus -info: Entering event queue @ 1609034475000. Starting simulation... +info: Entering event queue @ 1609097920000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610034475000. Starting simulation... -info: Entering event queue @ 1616044720500. Starting simulation... -info: Entering event queue @ 1616044727000. Starting simulation... +info: Entering event queue @ 1610097920000. Starting simulation... +info: Entering event queue @ 1616044694500. Starting simulation... +info: Entering event queue @ 1616044701500. Starting simulation... switching cpus -info: Entering event queue @ 1616044727500. Starting simulation... +info: Entering event queue @ 1616044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1617044727500. Starting simulation... +info: Entering event queue @ 1617044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1618044727500. Starting simulation... +info: Entering event queue @ 1618044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1619044727500. Starting simulation... -info: Entering event queue @ 1626044720500. Starting simulation... -info: Entering event queue @ 1626044727000. Starting simulation... +info: Entering event queue @ 1619044706000. Starting simulation... +info: Entering event queue @ 1626044694500. Starting simulation... +info: Entering event queue @ 1626044701500. Starting simulation... switching cpus -info: Entering event queue @ 1626044727500. Starting simulation... +info: Entering event queue @ 1626044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1627044727500. Starting simulation... +info: Entering event queue @ 1627044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1628044727500. Starting simulation... +info: Entering event queue @ 1628044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1629044727500. Starting simulation... -info: Entering event queue @ 1636044720500. Starting simulation... -info: Entering event queue @ 1636044727000. Starting simulation... +info: Entering event queue @ 1629044706000. Starting simulation... +info: Entering event queue @ 1636044694500. Starting simulation... +info: Entering event queue @ 1636044701500. Starting simulation... switching cpus -info: Entering event queue @ 1636044727500. Starting simulation... +info: Entering event queue @ 1636044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1637044727500. Starting simulation... +info: Entering event queue @ 1637044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1638044727500. Starting simulation... +info: Entering event queue @ 1638044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1639044727500. Starting simulation... -info: Entering event queue @ 1646044720500. Starting simulation... -info: Entering event queue @ 1646044727000. Starting simulation... +info: Entering event queue @ 1639044706000. Starting simulation... +info: Entering event queue @ 1646044695500. Starting simulation... +info: Entering event queue @ 1646044702500. Starting simulation... switching cpus -info: Entering event queue @ 1646044727500. Starting simulation... +info: Entering event queue @ 1646044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1647044727500. Starting simulation... +info: Entering event queue @ 1647044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1648044727500. Starting simulation... +info: Entering event queue @ 1648044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1649044727500. Starting simulation... -info: Entering event queue @ 1656044720500. Starting simulation... -info: Entering event queue @ 1656044727000. Starting simulation... +info: Entering event queue @ 1649044707000. Starting simulation... +info: Entering event queue @ 1656044695500. Starting simulation... +info: Entering event queue @ 1656044702500. Starting simulation... switching cpus -info: Entering event queue @ 1656044727500. Starting simulation... +info: Entering event queue @ 1656044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1657044727500. Starting simulation... +info: Entering event queue @ 1657044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1658044727500. Starting simulation... +info: Entering event queue @ 1658044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1659044727500. Starting simulation... -info: Entering event queue @ 1666044720500. Starting simulation... -info: Entering event queue @ 1666044727000. Starting simulation... +info: Entering event queue @ 1659044707000. Starting simulation... switching cpus -info: Entering event queue @ 1666044727500. Starting simulation... +info: Entering event queue @ 1666044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1667044727500. Starting simulation... +info: Entering event queue @ 1667044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1668044727500. Starting simulation... +info: Entering event queue @ 1668044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1669044727500. Starting simulation... -info: Entering event queue @ 1676044720500. Starting simulation... -info: Entering event queue @ 1676044727000. Starting simulation... +info: Entering event queue @ 1669044695500. Starting simulation... switching cpus -info: Entering event queue @ 1676044727500. Starting simulation... +info: Entering event queue @ 1676044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1677044727500. Starting simulation... +info: Entering event queue @ 1677044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1678044727500. Starting simulation... +info: Entering event queue @ 1678044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1679044727500. Starting simulation... -info: Entering event queue @ 1686044720500. Starting simulation... -info: Entering event queue @ 1686044727000. Starting simulation... +info: Entering event queue @ 1679044695500. Starting simulation... +info: Entering event queue @ 1686044694500. Starting simulation... +info: Entering event queue @ 1686044701500. Starting simulation... switching cpus -info: Entering event queue @ 1686044727500. Starting simulation... +info: Entering event queue @ 1686044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1687044727500. Starting simulation... +info: Entering event queue @ 1687044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1688044727500. Starting simulation... +info: Entering event queue @ 1688044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1689044727500. Starting simulation... -info: Entering event queue @ 1696044720500. Starting simulation... -info: Entering event queue @ 1696044727000. Starting simulation... +info: Entering event queue @ 1689044706000. Starting simulation... +info: Entering event queue @ 1696044695500. Starting simulation... +info: Entering event queue @ 1696044703500. Starting simulation... switching cpus -info: Entering event queue @ 1696044727500. Starting simulation... +info: Entering event queue @ 1696044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1697044727500. Starting simulation... +info: Entering event queue @ 1697044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1698044727500. Starting simulation... +info: Entering event queue @ 1698044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1699044727500. Starting simulation... -info: Entering event queue @ 1706044720500. Starting simulation... -info: Entering event queue @ 1707243505000. Starting simulation... +info: Entering event queue @ 1699044708000. Starting simulation... +info: Entering event queue @ 1706044694500. Starting simulation... +info: Entering event queue @ 1707307739000. Starting simulation... switching cpus -info: Entering event queue @ 1707243507000. Starting simulation... +info: Entering event queue @ 1707307741000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1708243507000. Starting simulation... +info: Entering event queue @ 1708307741000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1709243507000. Starting simulation... +info: Entering event queue @ 1709307741000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1710243507000. Starting simulation... -info: Entering event queue @ 1716044720500. Starting simulation... -info: Entering event queue @ 1716044727000. Starting simulation... +info: Entering event queue @ 1710307741000. Starting simulation... +info: Entering event queue @ 1716044694500. Starting simulation... +info: Entering event queue @ 1716044701500. Starting simulation... switching cpus -info: Entering event queue @ 1716044727500. Starting simulation... +info: Entering event queue @ 1716044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1717044727500. Starting simulation... +info: Entering event queue @ 1717044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1718044727500. Starting simulation... +info: Entering event queue @ 1718044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1719044727500. Starting simulation... -info: Entering event queue @ 1726044720500. Starting simulation... -info: Entering event queue @ 1726044727000. Starting simulation... +info: Entering event queue @ 1719044706000. Starting simulation... +info: Entering event queue @ 1726044694500. Starting simulation... +info: Entering event queue @ 1726044701500. Starting simulation... switching cpus -info: Entering event queue @ 1726044727500. Starting simulation... +info: Entering event queue @ 1726044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1727044727500. Starting simulation... +info: Entering event queue @ 1727044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1728044727500. Starting simulation... +info: Entering event queue @ 1728044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1729044727500. Starting simulation... -info: Entering event queue @ 1736044720500. Starting simulation... -info: Entering event queue @ 1736044727000. Starting simulation... +info: Entering event queue @ 1729044706000. Starting simulation... +info: Entering event queue @ 1736044695500. Starting simulation... +info: Entering event queue @ 1736044703500. Starting simulation... switching cpus -info: Entering event queue @ 1736044727500. Starting simulation... +info: Entering event queue @ 1736044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1737044727500. Starting simulation... +info: Entering event queue @ 1737044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1738044727500. Starting simulation... +info: Entering event queue @ 1738044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1739044727500. Starting simulation... -info: Entering event queue @ 1746044720500. Starting simulation... -info: Entering event queue @ 1746044727000. Starting simulation... +info: Entering event queue @ 1739044708000. Starting simulation... +info: Entering event queue @ 1746044695500. Starting simulation... +info: Entering event queue @ 1746044702500. Starting simulation... switching cpus -info: Entering event queue @ 1746044727500. Starting simulation... +info: Entering event queue @ 1746044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1747044727500. Starting simulation... +info: Entering event queue @ 1747044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1748044727500. Starting simulation... +info: Entering event queue @ 1748044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1749044727500. Starting simulation... -info: Entering event queue @ 1756044720500. Starting simulation... -info: Entering event queue @ 1756044727000. Starting simulation... +info: Entering event queue @ 1749044707000. Starting simulation... +info: Entering event queue @ 1756044694500. Starting simulation... +info: Entering event queue @ 1756044701000. Starting simulation... switching cpus -info: Entering event queue @ 1756044727500. Starting simulation... +info: Entering event queue @ 1756044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1757044727500. Starting simulation... +info: Entering event queue @ 1757044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1758044727500. Starting simulation... +info: Entering event queue @ 1758044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1759044727500. Starting simulation... -info: Entering event queue @ 1766044720500. Starting simulation... -info: Entering event queue @ 1766044727000. Starting simulation... +info: Entering event queue @ 1759044701500. Starting simulation... +info: Entering event queue @ 1766044694500. Starting simulation... +info: Entering event queue @ 1766044701500. Starting simulation... switching cpus -info: Entering event queue @ 1766044727500. Starting simulation... +info: Entering event queue @ 1766044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1767044727500. Starting simulation... +info: Entering event queue @ 1767044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1768044727500. Starting simulation... +info: Entering event queue @ 1768044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769044727500. Starting simulation... -info: Entering event queue @ 1776044720500. Starting simulation... -info: Entering event queue @ 1776044727000. Starting simulation... +info: Entering event queue @ 1769044706000. Starting simulation... +info: Entering event queue @ 1776044695500. Starting simulation... +info: Entering event queue @ 1776044703000. Starting simulation... switching cpus -info: Entering event queue @ 1776044727500. Starting simulation... +info: Entering event queue @ 1776044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1777044727500. Starting simulation... +info: Entering event queue @ 1777044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1778044727500. Starting simulation... +info: Entering event queue @ 1778044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1779044727500. Starting simulation... -info: Entering event queue @ 1786044720500. Starting simulation... -info: Entering event queue @ 1786044727000. Starting simulation... +info: Entering event queue @ 1779044703500. Starting simulation... +info: Entering event queue @ 1786044694500. Starting simulation... +info: Entering event queue @ 1786044701500. Starting simulation... switching cpus -info: Entering event queue @ 1786044727500. Starting simulation... +info: Entering event queue @ 1786044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1787044727500. Starting simulation... +info: Entering event queue @ 1787044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1788044727500. Starting simulation... +info: Entering event queue @ 1788044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1789044727500. Starting simulation... -info: Entering event queue @ 1796044720500. Starting simulation... -info: Entering event queue @ 1796044727000. Starting simulation... +info: Entering event queue @ 1789044706000. Starting simulation... +info: Entering event queue @ 1796044694500. Starting simulation... +info: Entering event queue @ 1796044701500. Starting simulation... switching cpus -info: Entering event queue @ 1796044727500. Starting simulation... +info: Entering event queue @ 1796044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1797044727500. Starting simulation... +info: Entering event queue @ 1797044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1798044727500. Starting simulation... +info: Entering event queue @ 1798044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1799044727500. Starting simulation... -info: Entering event queue @ 1806044720500. Starting simulation... -info: Entering event queue @ 1806044727000. Starting simulation... +info: Entering event queue @ 1799044706000. Starting simulation... +info: Entering event queue @ 1806044695500. Starting simulation... +info: Entering event queue @ 1806044704000. Starting simulation... switching cpus -info: Entering event queue @ 1806044727500. Starting simulation... +info: Entering event queue @ 1806044704500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1807044727500. Starting simulation... +info: Entering event queue @ 1807044704500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1808044727500. Starting simulation... +info: Entering event queue @ 1808044704500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1809044727500. Starting simulation... -info: Entering event queue @ 1816044720500. Starting simulation... -info: Entering event queue @ 1816044727000. Starting simulation... +info: Entering event queue @ 1809044704500. Starting simulation... +info: Entering event queue @ 1816044694500. Starting simulation... +info: Entering event queue @ 1816044701500. Starting simulation... switching cpus -info: Entering event queue @ 1816044727500. Starting simulation... +info: Entering event queue @ 1816044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1817044727500. Starting simulation... +info: Entering event queue @ 1817044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1818044727500. Starting simulation... +info: Entering event queue @ 1818044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1819044727500. Starting simulation... -info: Entering event queue @ 1826044720500. Starting simulation... -info: Entering event queue @ 1826044727000. Starting simulation... +info: Entering event queue @ 1819044706000. Starting simulation... switching cpus -info: Entering event queue @ 1826044727500. Starting simulation... +info: Entering event queue @ 1826044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1827044727500. Starting simulation... +info: Entering event queue @ 1827044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1828044727500. Starting simulation... +info: Entering event queue @ 1828044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1829044727500. Starting simulation... -info: Entering event queue @ 1836044720500. Starting simulation... -info: Entering event queue @ 1836044727000. Starting simulation... +info: Entering event queue @ 1829044695500. Starting simulation... switching cpus -info: Entering event queue @ 1836044727500. Starting simulation... +info: Entering event queue @ 1836044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1837044727500. Starting simulation... +info: Entering event queue @ 1837044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1838044727500. Starting simulation... +info: Entering event queue @ 1838044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839044727500. Starting simulation... -info: Entering event queue @ 1846044720500. Starting simulation... -info: Entering event queue @ 1846044727000. Starting simulation... +info: Entering event queue @ 1839044695500. Starting simulation... +info: Entering event queue @ 1846044694500. Starting simulation... +info: Entering event queue @ 1846044701500. Starting simulation... switching cpus -info: Entering event queue @ 1846044727500. Starting simulation... +info: Entering event queue @ 1846044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1847044727500. Starting simulation... +info: Entering event queue @ 1847044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1848044727500. Starting simulation... +info: Entering event queue @ 1848044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1849044727500. Starting simulation... -info: Entering event queue @ 1856044720500. Starting simulation... -info: Entering event queue @ 1856044727000. Starting simulation... +info: Entering event queue @ 1849044706000. Starting simulation... +info: Entering event queue @ 1856044695500. Starting simulation... +info: Entering event queue @ 1856044703500. Starting simulation... switching cpus -info: Entering event queue @ 1856044727500. Starting simulation... +info: Entering event queue @ 1856044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1857044727500. Starting simulation... +info: Entering event queue @ 1857044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1858044727500. Starting simulation... +info: Entering event queue @ 1858044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1859044727500. Starting simulation... -info: Entering event queue @ 1866044720500. Starting simulation... -info: Entering event queue @ 1866044727000. Starting simulation... +info: Entering event queue @ 1859044708000. Starting simulation... +info: Entering event queue @ 1866044694500. Starting simulation... +info: Entering event queue @ 1866044701000. Starting simulation... switching cpus -info: Entering event queue @ 1866044727500. Starting simulation... +info: Entering event queue @ 1866044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1867044727500. Starting simulation... +info: Entering event queue @ 1867044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1868044727500. Starting simulation... +info: Entering event queue @ 1868044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1869044727500. Starting simulation... -info: Entering event queue @ 1876044720500. Starting simulation... -info: Entering event queue @ 1876044727000. Starting simulation... +info: Entering event queue @ 1869044701500. Starting simulation... +info: Entering event queue @ 1876044694500. Starting simulation... +info: Entering event queue @ 1876044701500. Starting simulation... switching cpus -info: Entering event queue @ 1876044727500. Starting simulation... +info: Entering event queue @ 1876044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1877044727500. Starting simulation... +info: Entering event queue @ 1877044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1878044727500. Starting simulation... +info: Entering event queue @ 1878044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1879044727500. Starting simulation... -info: Entering event queue @ 1886044720500. Starting simulation... -info: Entering event queue @ 1886044727000. Starting simulation... +info: Entering event queue @ 1879044706000. Starting simulation... +info: Entering event queue @ 1886044694500. Starting simulation... +info: Entering event queue @ 1886044701500. Starting simulation... switching cpus -info: Entering event queue @ 1886044727500. Starting simulation... +info: Entering event queue @ 1886044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1887044727500. Starting simulation... +info: Entering event queue @ 1887044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1888044727500. Starting simulation... +info: Entering event queue @ 1888044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1889044727500. Starting simulation... -info: Entering event queue @ 1896044720500. Starting simulation... -info: Entering event queue @ 1896044727000. Starting simulation... +info: Entering event queue @ 1889044706000. Starting simulation... +info: Entering event queue @ 1896044695500. Starting simulation... +info: Entering event queue @ 1896044703500. Starting simulation... switching cpus -info: Entering event queue @ 1896044727500. Starting simulation... +info: Entering event queue @ 1896044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1897044727500. Starting simulation... +info: Entering event queue @ 1897044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1898044727500. Starting simulation... +info: Entering event queue @ 1898044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1899044727500. Starting simulation... -info: Entering event queue @ 1906044720500. Starting simulation... -info: Entering event queue @ 1906044727000. Starting simulation... +info: Entering event queue @ 1899044708000. Starting simulation... switching cpus -info: Entering event queue @ 1906044727500. Starting simulation... +info: Entering event queue @ 1906044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1907044727500. Starting simulation... +info: Entering event queue @ 1907044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1908044727500. Starting simulation... +info: Entering event queue @ 1908044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1909044727500. Starting simulation... -info: Entering event queue @ 1916044720500. Starting simulation... -info: Entering event queue @ 1916044727000. Starting simulation... +info: Entering event queue @ 1909044695500. Starting simulation... +info: Entering event queue @ 1916044694500. Starting simulation... +info: Entering event queue @ 1916044701000. Starting simulation... switching cpus -info: Entering event queue @ 1916044727500. Starting simulation... +info: Entering event queue @ 1916044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1917044727500. Starting simulation... +info: Entering event queue @ 1917044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1918044727500. Starting simulation... +info: Entering event queue @ 1918044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1919044727500. Starting simulation... -info: Entering event queue @ 1926044720500. Starting simulation... -info: Entering event queue @ 1926044727000. Starting simulation... +info: Entering event queue @ 1919044701500. Starting simulation... +info: Entering event queue @ 1926044694500. Starting simulation... +info: Entering event queue @ 1926044701500. Starting simulation... switching cpus -info: Entering event queue @ 1926044727500. Starting simulation... +info: Entering event queue @ 1926044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1927044727500. Starting simulation... +info: Entering event queue @ 1927044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1928044727500. Starting simulation... +info: Entering event queue @ 1928044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1929044727500. Starting simulation... -info: Entering event queue @ 1936044720500. Starting simulation... -info: Entering event queue @ 1936397407000. Starting simulation... +info: Entering event queue @ 1929044706000. Starting simulation... +info: Entering event queue @ 1936044695500. Starting simulation... +info: Entering event queue @ 1936460526000. Starting simulation... switching cpus -info: Entering event queue @ 1936397409000. Starting simulation... +info: Entering event queue @ 1936460528000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1937397409000. Starting simulation... +info: Entering event queue @ 1937460528000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1938397409000. Starting simulation... +info: Entering event queue @ 1938460528000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1939397409000. Starting simulation... -info: Entering event queue @ 1946044720500. Starting simulation... -info: Entering event queue @ 1946044727000. Starting simulation... +info: Entering event queue @ 1939460528000. Starting simulation... +info: Entering event queue @ 1946044694500. Starting simulation... +info: Entering event queue @ 1946044701500. Starting simulation... switching cpus -info: Entering event queue @ 1946044727500. Starting simulation... +info: Entering event queue @ 1946044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1947044727500. Starting simulation... +info: Entering event queue @ 1947044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1948044727500. Starting simulation... +info: Entering event queue @ 1948044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1949044727500. Starting simulation... -info: Entering event queue @ 1956044720500. Starting simulation... -info: Entering event queue @ 1956044727000. Starting simulation... +info: Entering event queue @ 1949044706000. Starting simulation... +info: Entering event queue @ 1956044694500. Starting simulation... +info: Entering event queue @ 1956044701500. Starting simulation... switching cpus -info: Entering event queue @ 1956044727500. Starting simulation... +info: Entering event queue @ 1956044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1957044727500. Starting simulation... +info: Entering event queue @ 1957044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1958044727500. Starting simulation... +info: Entering event queue @ 1958044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1959044727500. Starting simulation... -info: Entering event queue @ 1966044720500. Starting simulation... -info: Entering event queue @ 1966044727000. Starting simulation... +info: Entering event queue @ 1959044706000. Starting simulation... +info: Entering event queue @ 1966044695500. Starting simulation... +info: Entering event queue @ 1966044704000. Starting simulation... switching cpus -info: Entering event queue @ 1966044727500. Starting simulation... +info: Entering event queue @ 1966044704500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1967044727500. Starting simulation... +info: Entering event queue @ 1967044704500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1968044727500. Starting simulation... -info: Entering event queue @ 1969133554000. Starting simulation... +info: Entering event queue @ 1968044704500. Starting simulation... +info: Entering event queue @ 1969197126000. Starting simulation... switching cpus -info: Entering event queue @ 1969133556000. Starting simulation... +info: Entering event queue @ 1969197128000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1970133556000. Starting simulation... -info: Entering event queue @ 1976044720500. Starting simulation... -info: Entering event queue @ 1976044727000. Starting simulation... +info: Entering event queue @ 1970197128000. Starting simulation... +info: Entering event queue @ 1976044695500. Starting simulation... +info: Entering event queue @ 1976044703000. Starting simulation... switching cpus -info: Entering event queue @ 1976044727500. Starting simulation... +info: Entering event queue @ 1976044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1977044727500. Starting simulation... +info: Entering event queue @ 1977044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1978044727500. Starting simulation... +info: Entering event queue @ 1978044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1979044727500. Starting simulation... -info: Entering event queue @ 1986044720500. Starting simulation... -info: Entering event queue @ 1986044727000. Starting simulation... +info: Entering event queue @ 1979044703500. Starting simulation... switching cpus -info: Entering event queue @ 1986044727500. Starting simulation... +info: Entering event queue @ 1986044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1987044727500. Starting simulation... +info: Entering event queue @ 1987044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1988044727500. Starting simulation... +info: Entering event queue @ 1988044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1989044727500. Starting simulation... -info: Entering event queue @ 1996044720500. Starting simulation... -info: Entering event queue @ 1996044727000. Starting simulation... +info: Entering event queue @ 1989044695500. Starting simulation... switching cpus -info: Entering event queue @ 1996044727500. Starting simulation... +info: Entering event queue @ 1996044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1997044727500. Starting simulation... +info: Entering event queue @ 1997044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1998044727500. Starting simulation... +info: Entering event queue @ 1998044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1999044727500. Starting simulation... -info: Entering event queue @ 2006044720500. Starting simulation... -info: Entering event queue @ 2006044727000. Starting simulation... +info: Entering event queue @ 1999044695500. Starting simulation... +info: Entering event queue @ 2006044695500. Starting simulation... +info: Entering event queue @ 2006044703500. Starting simulation... switching cpus -info: Entering event queue @ 2006044727500. Starting simulation... +info: Entering event queue @ 2006044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2007044727500. Starting simulation... +info: Entering event queue @ 2007044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2008044727500. Starting simulation... +info: Entering event queue @ 2008044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2009044727500. Starting simulation... -info: Entering event queue @ 2016044720500. Starting simulation... -info: Entering event queue @ 2016044727000. Starting simulation... +info: Entering event queue @ 2009044704000. Starting simulation... +info: Entering event queue @ 2016044695500. Starting simulation... +info: Entering event queue @ 2016044702000. Starting simulation... switching cpus -info: Entering event queue @ 2016044727500. Starting simulation... +info: Entering event queue @ 2016044702500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2017044727500. Starting simulation... +info: Entering event queue @ 2017044702500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2018044727500. Starting simulation... +info: Entering event queue @ 2018044702500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2019044727500. Starting simulation... -info: Entering event queue @ 2026044720500. Starting simulation... -info: Entering event queue @ 2026044727000. Starting simulation... +info: Entering event queue @ 2019044702500. Starting simulation... +info: Entering event queue @ 2026044694500. Starting simulation... +info: Entering event queue @ 2026044701000. Starting simulation... switching cpus -info: Entering event queue @ 2026044727500. Starting simulation... +info: Entering event queue @ 2026044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2027044727500. Starting simulation... +info: Entering event queue @ 2027044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2028044727500. Starting simulation... +info: Entering event queue @ 2028044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2029044727500. Starting simulation... -info: Entering event queue @ 2036044720500. Starting simulation... -info: Entering event queue @ 2036044727000. Starting simulation... +info: Entering event queue @ 2029044701500. Starting simulation... +info: Entering event queue @ 2036044694500. Starting simulation... +info: Entering event queue @ 2036044701500. Starting simulation... switching cpus -info: Entering event queue @ 2036044727500. Starting simulation... +info: Entering event queue @ 2036044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2037044727500. Starting simulation... +info: Entering event queue @ 2037044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2038044727500. Starting simulation... +info: Entering event queue @ 2038044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2039044727500. Starting simulation... -info: Entering event queue @ 2046044720500. Starting simulation... -info: Entering event queue @ 2046044727000. Starting simulation... +info: Entering event queue @ 2039044706000. Starting simulation... +info: Entering event queue @ 2046044694500. Starting simulation... +info: Entering event queue @ 2046044701500. Starting simulation... switching cpus -info: Entering event queue @ 2046044727500. Starting simulation... +info: Entering event queue @ 2046044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2047044727500. Starting simulation... +info: Entering event queue @ 2047044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2048044727500. Starting simulation... +info: Entering event queue @ 2048044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2049044727500. Starting simulation... -info: Entering event queue @ 2056044720500. Starting simulation... -info: Entering event queue @ 2056044727000. Starting simulation... +info: Entering event queue @ 2049044706000. Starting simulation... +info: Entering event queue @ 2056044695500. Starting simulation... +info: Entering event queue @ 2056044703500. Starting simulation... switching cpus -info: Entering event queue @ 2056044727500. Starting simulation... +info: Entering event queue @ 2056044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2057044727500. Starting simulation... +info: Entering event queue @ 2057044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2058044727500. Starting simulation... +info: Entering event queue @ 2058044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2059044727500. Starting simulation... -info: Entering event queue @ 2066044720500. Starting simulation... -info: Entering event queue @ 2067342280000. Starting simulation... +info: Entering event queue @ 2059044708000. Starting simulation... +info: Entering event queue @ 2066044695500. Starting simulation... +info: Entering event queue @ 2067405755000. Starting simulation... switching cpus -info: Entering event queue @ 2067342282000. Starting simulation... +info: Entering event queue @ 2067405757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2068342282000. Starting simulation... +info: Entering event queue @ 2068405757000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2069342282000. Starting simulation... +info: Entering event queue @ 2069405757000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2070342282000. Starting simulation... -info: Entering event queue @ 2076044720500. Starting simulation... -info: Entering event queue @ 2076044727000. Starting simulation... +info: Entering event queue @ 2070405757000. Starting simulation... +info: Entering event queue @ 2076044694500. Starting simulation... +info: Entering event queue @ 2076044701000. Starting simulation... switching cpus -info: Entering event queue @ 2076044727500. Starting simulation... +info: Entering event queue @ 2076044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2077044727500. Starting simulation... +info: Entering event queue @ 2077044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2078044727500. Starting simulation... +info: Entering event queue @ 2078044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2079044727500. Starting simulation... -info: Entering event queue @ 2086044720500. Starting simulation... -info: Entering event queue @ 2086044727000. Starting simulation... +info: Entering event queue @ 2079044701500. Starting simulation... +info: Entering event queue @ 2086044694500. Starting simulation... +info: Entering event queue @ 2086044701500. Starting simulation... switching cpus -info: Entering event queue @ 2086044727500. Starting simulation... +info: Entering event queue @ 2086044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2087044727500. Starting simulation... +info: Entering event queue @ 2087044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2088044727500. Starting simulation... +info: Entering event queue @ 2088044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2089044727500. Starting simulation... -info: Entering event queue @ 2096044720500. Starting simulation... -info: Entering event queue @ 2096044727000. Starting simulation... +info: Entering event queue @ 2089044706000. Starting simulation... +info: Entering event queue @ 2096044695500. Starting simulation... +info: Entering event queue @ 2096044702500. Starting simulation... switching cpus -info: Entering event queue @ 2096044727500. Starting simulation... +info: Entering event queue @ 2096044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2097044727500. Starting simulation... +info: Entering event queue @ 2097044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2098044727500. Starting simulation... +info: Entering event queue @ 2098044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2099044727500. Starting simulation... -info: Entering event queue @ 2106044720500. Starting simulation... -info: Entering event queue @ 2106044727000. Starting simulation... +info: Entering event queue @ 2099044707000. Starting simulation... +info: Entering event queue @ 2106044694500. Starting simulation... +info: Entering event queue @ 2106044701500. Starting simulation... switching cpus -info: Entering event queue @ 2106044727500. Starting simulation... +info: Entering event queue @ 2106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2107044727500. Starting simulation... +info: Entering event queue @ 2107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2108044727500. Starting simulation... +info: Entering event queue @ 2108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2109044727500. Starting simulation... -info: Entering event queue @ 2116044720500. Starting simulation... -info: Entering event queue @ 2116044727000. Starting simulation... +info: Entering event queue @ 2109044706000. Starting simulation... +info: Entering event queue @ 2116044694500. Starting simulation... +info: Entering event queue @ 2116044701500. Starting simulation... switching cpus -info: Entering event queue @ 2116044727500. Starting simulation... +info: Entering event queue @ 2116044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2117044727500. Starting simulation... +info: Entering event queue @ 2117044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2118044727500. Starting simulation... +info: Entering event queue @ 2118044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2119044727500. Starting simulation... -info: Entering event queue @ 2126044720500. Starting simulation... -info: Entering event queue @ 2126044727000. Starting simulation... +info: Entering event queue @ 2119044706000. Starting simulation... +info: Entering event queue @ 2126044695500. Starting simulation... +info: Entering event queue @ 2126044704000. Starting simulation... switching cpus -info: Entering event queue @ 2126044727500. Starting simulation... +info: Entering event queue @ 2126044708500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2127044727500. Starting simulation... +info: Entering event queue @ 2127044708500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2128044727500. Starting simulation... +info: Entering event queue @ 2128044708500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2129044727500. Starting simulation... -info: Entering event queue @ 2136044720500. Starting simulation... -info: Entering event queue @ 2136044727000. Starting simulation... +info: Entering event queue @ 2129044708500. Starting simulation... switching cpus -info: Entering event queue @ 2136044727500. Starting simulation... +info: Entering event queue @ 2136044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2137044727500. Starting simulation... +info: Entering event queue @ 2137044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2138044727500. Starting simulation... +info: Entering event queue @ 2138044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2139044727500. Starting simulation... -info: Entering event queue @ 2146044720500. Starting simulation... -info: Entering event queue @ 2146044727000. Starting simulation... +info: Entering event queue @ 2139044695500. Starting simulation... switching cpus -info: Entering event queue @ 2146044727500. Starting simulation... +info: Entering event queue @ 2146044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2147044727500. Starting simulation... +info: Entering event queue @ 2147044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2148044727500. Starting simulation... +info: Entering event queue @ 2148044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2149044727500. Starting simulation... -info: Entering event queue @ 2156044720500. Starting simulation... -info: Entering event queue @ 2156044727000. Starting simulation... +info: Entering event queue @ 2149044695500. Starting simulation... switching cpus -info: Entering event queue @ 2156044727500. Starting simulation... +info: Entering event queue @ 2156044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2157044727500. Starting simulation... +info: Entering event queue @ 2157044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2158044727500. Starting simulation... +info: Entering event queue @ 2158044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2159044727500. Starting simulation... -info: Entering event queue @ 2166044720500. Starting simulation... -info: Entering event queue @ 2166044727000. Starting simulation... +info: Entering event queue @ 2159044695500. Starting simulation... +info: Entering event queue @ 2166044694500. Starting simulation... +info: Entering event queue @ 2166044701500. Starting simulation... switching cpus -info: Entering event queue @ 2166044727500. Starting simulation... +info: Entering event queue @ 2166044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2167044727500. Starting simulation... +info: Entering event queue @ 2167044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2168044727500. Starting simulation... +info: Entering event queue @ 2168044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2169044727500. Starting simulation... -info: Entering event queue @ 2176044720500. Starting simulation... -info: Entering event queue @ 2176044727000. Starting simulation... +info: Entering event queue @ 2169044706000. Starting simulation... +info: Entering event queue @ 2176044694500. Starting simulation... +info: Entering event queue @ 2176044701500. Starting simulation... switching cpus -info: Entering event queue @ 2176044727500. Starting simulation... +info: Entering event queue @ 2176044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2177044727500. Starting simulation... +info: Entering event queue @ 2177044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2178044727500. Starting simulation... +info: Entering event queue @ 2178044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2179044727500. Starting simulation... -info: Entering event queue @ 2186044720500. Starting simulation... -info: Entering event queue @ 2186044727000. Starting simulation... +info: Entering event queue @ 2179044706000. Starting simulation... +info: Entering event queue @ 2186044694500. Starting simulation... +info: Entering event queue @ 2186044701000. Starting simulation... switching cpus -info: Entering event queue @ 2186044727500. Starting simulation... +info: Entering event queue @ 2186044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2187044727500. Starting simulation... +info: Entering event queue @ 2187044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2188044727500. Starting simulation... +info: Entering event queue @ 2188044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2189044727500. Starting simulation... -info: Entering event queue @ 2196044720500. Starting simulation... -info: Entering event queue @ 2196044727000. Starting simulation... +info: Entering event queue @ 2189044701500. Starting simulation... +info: Entering event queue @ 2196044694500. Starting simulation... +info: Entering event queue @ 2196044701500. Starting simulation... switching cpus -info: Entering event queue @ 2196044727500. Starting simulation... +info: Entering event queue @ 2196044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2197044727500. Starting simulation... +info: Entering event queue @ 2197044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2198044727500. Starting simulation... +info: Entering event queue @ 2198044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2199044727500. Starting simulation... -info: Entering event queue @ 2206044720500. Starting simulation... -info: Entering event queue @ 2206044727000. Starting simulation... +info: Entering event queue @ 2199044706000. Starting simulation... switching cpus -info: Entering event queue @ 2206044727500. Starting simulation... +info: Entering event queue @ 2206044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2207044727500. Starting simulation... +info: Entering event queue @ 2207044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2208044727500. Starting simulation... +info: Entering event queue @ 2208044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2209044727500. Starting simulation... -info: Entering event queue @ 2216044720500. Starting simulation... -info: Entering event queue @ 2216044727000. Starting simulation... +info: Entering event queue @ 2209044695500. Starting simulation... +info: Entering event queue @ 2216044694500. Starting simulation... +info: Entering event queue @ 2216044701500. Starting simulation... switching cpus -info: Entering event queue @ 2216044727500. Starting simulation... +info: Entering event queue @ 2216044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2217044727500. Starting simulation... +info: Entering event queue @ 2217044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2218044727500. Starting simulation... +info: Entering event queue @ 2218044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2219044727500. Starting simulation... -info: Entering event queue @ 2226044720500. Starting simulation... -info: Entering event queue @ 2226044727000. Starting simulation... +info: Entering event queue @ 2219044706000. Starting simulation... +info: Entering event queue @ 2226044695500. Starting simulation... +info: Entering event queue @ 2226044703500. Starting simulation... switching cpus -info: Entering event queue @ 2226044727500. Starting simulation... +info: Entering event queue @ 2226044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2227044727500. Starting simulation... +info: Entering event queue @ 2227044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2228044727500. Starting simulation... +info: Entering event queue @ 2228044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2229044727500. Starting simulation... -info: Entering event queue @ 2236044720500. Starting simulation... -info: Entering event queue @ 2236044727000. Starting simulation... +info: Entering event queue @ 2229044708000. Starting simulation... +info: Entering event queue @ 2236044694500. Starting simulation... +info: Entering event queue @ 2236044701000. Starting simulation... switching cpus -info: Entering event queue @ 2236044727500. Starting simulation... +info: Entering event queue @ 2236044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2237044727500. Starting simulation... +info: Entering event queue @ 2237044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2238044727500. Starting simulation... +info: Entering event queue @ 2238044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2239044727500. Starting simulation... -info: Entering event queue @ 2246044720500. Starting simulation... -info: Entering event queue @ 2246044727000. Starting simulation... +info: Entering event queue @ 2239044701500. Starting simulation... +info: Entering event queue @ 2246044694500. Starting simulation... +info: Entering event queue @ 2246044701500. Starting simulation... switching cpus -info: Entering event queue @ 2246044727500. Starting simulation... +info: Entering event queue @ 2246044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2247044727500. Starting simulation... +info: Entering event queue @ 2247044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2248044727500. Starting simulation... +info: Entering event queue @ 2248044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2249044727500. Starting simulation... -info: Entering event queue @ 2256044720500. Starting simulation... -info: Entering event queue @ 2256044727000. Starting simulation... +info: Entering event queue @ 2249044706000. Starting simulation... +info: Entering event queue @ 2256044694500. Starting simulation... +info: Entering event queue @ 2256044701500. Starting simulation... switching cpus -info: Entering event queue @ 2256044727500. Starting simulation... +info: Entering event queue @ 2256044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2257044727500. Starting simulation... +info: Entering event queue @ 2257044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2258044727500. Starting simulation... +info: Entering event queue @ 2258044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2259044727500. Starting simulation... -info: Entering event queue @ 2266044720500. Starting simulation... -info: Entering event queue @ 2266044727000. Starting simulation... +info: Entering event queue @ 2259044706000. Starting simulation... +info: Entering event queue @ 2266044694500. Starting simulation... +info: Entering event queue @ 2266044701500. Starting simulation... switching cpus -info: Entering event queue @ 2266044727500. Starting simulation... +info: Entering event queue @ 2266044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2267044727500. Starting simulation... +info: Entering event queue @ 2267044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2268044727500. Starting simulation... +info: Entering event queue @ 2268044706000. Starting simulation... switching cpus -info: Entering event queue @ 2268044728500. Starting simulation... +info: Entering event queue @ 2268044713500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2269044728500. Starting simulation... +info: Entering event queue @ 2269044713500. Starting simulation... switching cpus -info: Entering event queue @ 2269044739000. Starting simulation... +info: Entering event queue @ 2269044786000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2270044739000. Starting simulation... +info: Entering event queue @ 2270044786000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2271044739000. Starting simulation... +info: Entering event queue @ 2271044786000. Starting simulation... switching cpus -info: Entering event queue @ 2271044767000. Starting simulation... +info: Entering event queue @ 2271044847000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2272044767000. Starting simulation... +info: Entering event queue @ 2272044847000. Starting simulation... switching cpus -info: Entering event queue @ 2272044790000. Starting simulation... +info: Entering event queue @ 2272044909000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2273044790000. Starting simulation... +info: Entering event queue @ 2273044909000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2274044790000. Starting simulation... +info: Entering event queue @ 2274044909000. Starting simulation... switching cpus -info: Entering event queue @ 2274044828000. Starting simulation... +info: Entering event queue @ 2274045051000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2275044828000. Starting simulation... +info: Entering event queue @ 2275045051000. Starting simulation... switching cpus -info: Entering event queue @ 2275044925000. Starting simulation... +info: Entering event queue @ 2275045114000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 2276045114000. Starting simulation... switching cpus -info: Entering event queue @ 2276044925000. Starting simulation... +info: Entering event queue @ 2276045117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2277044925000. Starting simulation... +info: Entering event queue @ 2277045117500. Starting simulation... switching cpus -info: Entering event queue @ 2277045053000. Starting simulation... +info: Entering event queue @ 2277045208000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2278045053000. Starting simulation... +info: Entering event queue @ 2278045208000. Starting simulation... switching cpus -info: Entering event queue @ 2278045122000. Starting simulation... +info: Entering event queue @ 2278045280000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2279045122000. Starting simulation... +info: Entering event queue @ 2279045280000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2280045122000. Starting simulation... +info: Entering event queue @ 2280045280000. Starting simulation... switching cpus -info: Entering event queue @ 2280045138000. Starting simulation... +info: Entering event queue @ 2280045384000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2281045138000. Starting simulation... +info: Entering event queue @ 2281045384000. Starting simulation... switching cpus -info: Entering event queue @ 2281045900000. Starting simulation... +info: Entering event queue @ 2281048528000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2282045900000. Starting simulation... +info: Entering event queue @ 2282048528000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2283045900000. Starting simulation... +info: Entering event queue @ 2283048528000. Starting simulation... switching cpus -info: Entering event queue @ 2283045901000. Starting simulation... +info: Entering event queue @ 2283048535500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2284045901000. Starting simulation... +info: Entering event queue @ 2284048535500. Starting simulation... switching cpus -info: Entering event queue @ 2284045960000. Starting simulation... +info: Entering event queue @ 2284048596000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2285045960000. Starting simulation... +info: Entering event queue @ 2285048596000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2286045960000. Starting simulation... +info: Entering event queue @ 2286048596000. Starting simulation... switching cpus -info: Entering event queue @ 2286045982000. Starting simulation... +info: Entering event queue @ 2286048638000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2287045982000. Starting simulation... +info: Entering event queue @ 2287048638000. Starting simulation... switching cpus -info: Entering event queue @ 2287045989000. Starting simulation... +info: Entering event queue @ 2287048678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2288045989000. Starting simulation... +info: Entering event queue @ 2288048678500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2289045989000. Starting simulation... +info: Entering event queue @ 2289048678500. Starting simulation... switching cpus -info: Entering event queue @ 2289046000000. Starting simulation... +info: Entering event queue @ 2289048766000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2290046000000. Starting simulation... +info: Entering event queue @ 2290048766000. Starting simulation... switching cpus -info: Entering event queue @ 2290046070000. Starting simulation... +info: Entering event queue @ 2290048836000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2291046070000. Starting simulation... +info: Entering event queue @ 2291048836000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2292046070000. Starting simulation... +info: Entering event queue @ 2292048836000. Starting simulation... switching cpus -info: Entering event queue @ 2292046106000. Starting simulation... +info: Entering event queue @ 2292048927000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2293046106000. Starting simulation... +info: Entering event queue @ 2293048927000. Starting simulation... switching cpus -info: Entering event queue @ 2293046137000. Starting simulation... +info: Entering event queue @ 2293049027000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2294046137000. Starting simulation... +info: Entering event queue @ 2294049027000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2295046137000. Starting simulation... -info: Entering event queue @ 2296496182000. Starting simulation... +info: Entering event queue @ 2295049027000. Starting simulation... +info: Entering event queue @ 2296559734000. Starting simulation... switching cpus -info: Entering event queue @ 2296496184000. Starting simulation... +info: Entering event queue @ 2296559736000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2297496184000. Starting simulation... +info: Entering event queue @ 2297559736000. Starting simulation... switching cpus -info: Entering event queue @ 2297496268000. Starting simulation... +info: Entering event queue @ 2297559885000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2298496268000. Starting simulation... +info: Entering event queue @ 2298559885000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2299496268000. Starting simulation... +info: Entering event queue @ 2299559885000. Starting simulation... switching cpus -info: Entering event queue @ 2299496348000. Starting simulation... +info: Entering event queue @ 2299559978000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2300496348000. Starting simulation... +info: Entering event queue @ 2300559978000. Starting simulation... switching cpus -info: Entering event queue @ 2300496430000. Starting simulation... +info: Entering event queue @ 2300560079000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2301496430000. Starting simulation... +info: Entering event queue @ 2301560079000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2302496430000. Starting simulation... +info: Entering event queue @ 2302560079000. Starting simulation... switching cpus -info: Entering event queue @ 2302496531000. Starting simulation... +info: Entering event queue @ 2302560132000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2303496531000. Starting simulation... +info: Entering event queue @ 2303560132000. Starting simulation... switching cpus -info: Entering event queue @ 2303496584000. Starting simulation... +info: Entering event queue @ 2303560241000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2304496584000. Starting simulation... +info: Entering event queue @ 2304560241000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2305496584000. Starting simulation... +info: Entering event queue @ 2305560241000. Starting simulation... switching cpus -info: Entering event queue @ 2305496661000. Starting simulation... +info: Entering event queue @ 2305560280000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2306496661000. Starting simulation... +info: Entering event queue @ 2306560280000. Starting simulation... switching cpus -info: Entering event queue @ 2306496732000. Starting simulation... +info: Entering event queue @ 2306560431000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2307496732000. Starting simulation... +info: Entering event queue @ 2307560431000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2308496732000. Starting simulation... +info: Entering event queue @ 2308560431000. Starting simulation... switching cpus -info: Entering event queue @ 2308496815000. Starting simulation... +info: Entering event queue @ 2308560560000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2309496815000. Starting simulation... +info: Entering event queue @ 2309560560000. Starting simulation... switching cpus -info: Entering event queue @ 2309496944500. Starting simulation... +info: Entering event queue @ 2309560642000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2310496944500. Starting simulation... +info: Entering event queue @ 2310560642000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2311496944500. Starting simulation... +info: Entering event queue @ 2311560642000. Starting simulation... switching cpus -info: Entering event queue @ 2311496968000. Starting simulation... +info: Entering event queue @ 2311560786000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2312496968000. Starting simulation... +info: Entering event queue @ 2312560786000. Starting simulation... switching cpus -info: Entering event queue @ 2312497014000. Starting simulation... +info: Entering event queue @ 2312560905000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2313497014000. Starting simulation... +info: Entering event queue @ 2313560905000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2314497014000. Starting simulation... +info: Entering event queue @ 2314560905000. Starting simulation... switching cpus -info: Entering event queue @ 2314497034000. Starting simulation... +info: Entering event queue @ 2314561028000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2315497034000. Starting simulation... +info: Entering event queue @ 2315561028000. Starting simulation... switching cpus -info: Entering event queue @ 2315497085000. Starting simulation... +info: Entering event queue @ 2315561054000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2316497085000. Starting simulation... +info: Entering event queue @ 2316561054000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2317497085000. Starting simulation... +info: Entering event queue @ 2317561054000. Starting simulation... switching cpus -info: Entering event queue @ 2317497141000. Starting simulation... +info: Entering event queue @ 2317561176000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2318497141000. Starting simulation... +info: Entering event queue @ 2318561176000. Starting simulation... switching cpus -info: Entering event queue @ 2318497292000. Starting simulation... +info: Entering event queue @ 2318561200000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2319497292000. Starting simulation... +info: Entering event queue @ 2319561200000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2320497292000. Starting simulation... +info: Entering event queue @ 2320561200000. Starting simulation... switching cpus -info: Entering event queue @ 2320497349000. Starting simulation... +info: Entering event queue @ 2320561287000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2321497349000. Starting simulation... +info: Entering event queue @ 2321561287000. Starting simulation... switching cpus -info: Entering event queue @ 2321497426000. Starting simulation... +info: Entering event queue @ 2321561319000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2322497426000. Starting simulation... +info: Entering event queue @ 2322561319000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2323497426000. Starting simulation... +info: Entering event queue @ 2323561319000. Starting simulation... switching cpus -info: Entering event queue @ 2323497512000. Starting simulation... +info: Entering event queue @ 2323561362000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2324497512000. Starting simulation... +info: Entering event queue @ 2324561362000. Starting simulation... switching cpus -info: Entering event queue @ 2324497588000. Starting simulation... +info: Entering event queue @ 2324561408000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2325497588000. Starting simulation... +info: Entering event queue @ 2325561408000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2326497588000. Starting simulation... +info: Entering event queue @ 2326561408000. Starting simulation... switching cpus -info: Entering event queue @ 2326497667000. Starting simulation... +info: Entering event queue @ 2326561540000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2327497667000. Starting simulation... +info: Entering event queue @ 2327561540000. Starting simulation... switching cpus -info: Entering event queue @ 2327497830500. Starting simulation... +info: Entering event queue @ 2327561579000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2328497830500. Starting simulation... +info: Entering event queue @ 2328561579000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2329497830500. Starting simulation... +info: Entering event queue @ 2329561579000. Starting simulation... switching cpus -info: Entering event queue @ 2329497980000. Starting simulation... +info: Entering event queue @ 2329561703000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2330497980000. Starting simulation... +info: Entering event queue @ 2330561703000. Starting simulation... switching cpus -info: Entering event queue @ 2330498019000. Starting simulation... +info: Entering event queue @ 2330561718000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2331498019000. Starting simulation... +info: Entering event queue @ 2331561718000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2332498019000. Starting simulation... +info: Entering event queue @ 2332561718000. Starting simulation... switching cpus -info: Entering event queue @ 2332498021000. Starting simulation... +info: Entering event queue @ 2332561741000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2333498021000. Starting simulation... +info: Entering event queue @ 2333561741000. Starting simulation... switching cpus -info: Entering event queue @ 2333498144000. Starting simulation... +info: Entering event queue @ 2333561793000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2334498144000. Starting simulation... +info: Entering event queue @ 2334561793000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2335498144000. Starting simulation... +info: Entering event queue @ 2335561793000. Starting simulation... switching cpus -info: Entering event queue @ 2335498177000. Starting simulation... +info: Entering event queue @ 2335561883000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2336498177000. Starting simulation... +info: Entering event queue @ 2336561883000. Starting simulation... switching cpus -info: Entering event queue @ 2336498207000. Starting simulation... +info: Entering event queue @ 2336561949000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2337498207000. Starting simulation... +info: Entering event queue @ 2337561949000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2338498207000. Starting simulation... +info: Entering event queue @ 2338561949000. Starting simulation... switching cpus -info: Entering event queue @ 2338498322500. Starting simulation... +info: Entering event queue @ 2338562083000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2339498322500. Starting simulation... +info: Entering event queue @ 2339562083000. Starting simulation... switching cpus -info: Entering event queue @ 2339498342500. Starting simulation... +info: Entering event queue @ 2339562223000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2340498342500. Starting simulation... +info: Entering event queue @ 2340562223000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2341498342500. Starting simulation... +info: Entering event queue @ 2341562223000. Starting simulation... switching cpus -info: Entering event queue @ 2341498465000. Starting simulation... +info: Entering event queue @ 2341562231000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2342498465000. Starting simulation... +info: Entering event queue @ 2342562231000. Starting simulation... switching cpus -info: Entering event queue @ 2342498545000. Starting simulation... +info: Entering event queue @ 2342562288000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2343498545000. Starting simulation... +info: Entering event queue @ 2343562288000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2344498545000. Starting simulation... +info: Entering event queue @ 2344562288000. Starting simulation... switching cpus -info: Entering event queue @ 2344498670000. Starting simulation... +info: Entering event queue @ 2344562311000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2345498670000. Starting simulation... +info: Entering event queue @ 2345562311000. Starting simulation... switching cpus -info: Entering event queue @ 2345498729000. Starting simulation... +info: Entering event queue @ 2345562459000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2346498729000. Starting simulation... +info: Entering event queue @ 2346562459000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2347498729000. Starting simulation... +info: Entering event queue @ 2347562459000. Starting simulation... switching cpus -info: Entering event queue @ 2347498836000. Starting simulation... +info: Entering event queue @ 2347562517000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2348498836000. Starting simulation... +info: Entering event queue @ 2348562517000. Starting simulation... switching cpus -info: Entering event queue @ 2348498903500. Starting simulation... +info: Entering event queue @ 2348562659000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2349498903500. Starting simulation... +info: Entering event queue @ 2349562659000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2350498903500. Starting simulation... +info: Entering event queue @ 2350562659000. Starting simulation... switching cpus -info: Entering event queue @ 2350499004000. Starting simulation... +info: Entering event queue @ 2350562734000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2351499004000. Starting simulation... +info: Entering event queue @ 2351562734000. Starting simulation... switching cpus -info: Entering event queue @ 2351499092000. Starting simulation... +info: Entering event queue @ 2351562890000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2352499092000. Starting simulation... +info: Entering event queue @ 2352562890000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2353499092000. Starting simulation... +info: Entering event queue @ 2353562890000. Starting simulation... switching cpus -info: Entering event queue @ 2353499228000. Starting simulation... +info: Entering event queue @ 2353562986000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2354499228000. Starting simulation... +info: Entering event queue @ 2354562986000. Starting simulation... switching cpus -info: Entering event queue @ 2354499241000. Starting simulation... +info: Entering event queue @ 2354563105000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2355499241000. Starting simulation... +info: Entering event queue @ 2355563105000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2356499241000. Starting simulation... +info: Entering event queue @ 2356563105000. Starting simulation... switching cpus -info: Entering event queue @ 2356499328000. Starting simulation... +info: Entering event queue @ 2356563162000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2357499328000. Starting simulation... +info: Entering event queue @ 2357563162000. Starting simulation... switching cpus -info: Entering event queue @ 2357499348000. Starting simulation... +info: Entering event queue @ 2357568596000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2358499348000. Starting simulation... +info: Entering event queue @ 2358568596000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2359499348000. Starting simulation... +info: Entering event queue @ 2359568596000. Starting simulation... switching cpus -info: Entering event queue @ 2359499378000. Starting simulation... +info: Entering event queue @ 2359568661000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2360499378000. Starting simulation... -info: Entering event queue @ 2361968926000. Starting simulation... +info: Entering event queue @ 2360568661000. Starting simulation... +info: Entering event queue @ 2362032934000. Starting simulation... switching cpus -info: Entering event queue @ 2361968928000. Starting simulation... +info: Entering event queue @ 2362032936000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2362968928000. Starting simulation... +info: Entering event queue @ 2363032936000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2363968928000. Starting simulation... +info: Entering event queue @ 2364032936000. Starting simulation... switching cpus -info: Entering event queue @ 2363969050000. Starting simulation... +info: Entering event queue @ 2364033051000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2364969050000. Starting simulation... +info: Entering event queue @ 2365033051000. Starting simulation... switching cpus -info: Entering event queue @ 2364969072000. Starting simulation... +info: Entering event queue @ 2365033171000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2365969072000. Starting simulation... +info: Entering event queue @ 2366033171000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2366969072000. Starting simulation... +info: Entering event queue @ 2367033171000. Starting simulation... switching cpus -info: Entering event queue @ 2366969074000. Starting simulation... +info: Entering event queue @ 2367033178500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2367969074000. Starting simulation... +info: Entering event queue @ 2368033178500. Starting simulation... switching cpus -info: Entering event queue @ 2367969092500. Starting simulation... +info: Entering event queue @ 2368033187500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2368969092500. Starting simulation... +info: Entering event queue @ 2369033187500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2369969092500. Starting simulation... +info: Entering event queue @ 2370033187500. Starting simulation... switching cpus -info: Entering event queue @ 2369969184000. Starting simulation... +info: Entering event queue @ 2370033205000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2370969184000. Starting simulation... +info: Entering event queue @ 2371033205000. Starting simulation... switching cpus -info: Entering event queue @ 2370969281000. Starting simulation... +info: Entering event queue @ 2371033365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2371969281000. Starting simulation... +info: Entering event queue @ 2372033365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2372969281000. Starting simulation... +info: Entering event queue @ 2373033365500. Starting simulation... +info: Entering event queue @ 2373033604000. Starting simulation... switching cpus -info: Entering event queue @ 2372969283000. Starting simulation... +info: Entering event queue @ 2373033611500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2373969283000. Starting simulation... +info: Entering event queue @ 2374033611500. Starting simulation... switching cpus -info: Entering event queue @ 2373969828500. Starting simulation... +info: Entering event queue @ 2374033619000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2374969828500. Starting simulation... +info: Entering event queue @ 2375033619000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2375969828500. Starting simulation... +info: Entering event queue @ 2376033619000. Starting simulation... switching cpus -info: Entering event queue @ 2375969851000. Starting simulation... +info: Entering event queue @ 2376033645000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2376969851000. Starting simulation... +info: Entering event queue @ 2377033645000. Starting simulation... switching cpus -info: Entering event queue @ 2376969901000. Starting simulation... +info: Entering event queue @ 2377043485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2377969901000. Starting simulation... +info: Entering event queue @ 2378043485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2378969901000. Starting simulation... +info: Entering event queue @ 2379043485500. Starting simulation... switching cpus -info: Entering event queue @ 2378969954000. Starting simulation... +info: Entering event queue @ 2379043518000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2379969954000. Starting simulation... +info: Entering event queue @ 2380043518000. Starting simulation... switching cpus -info: Entering event queue @ 2379970086500. Starting simulation... +info: Entering event queue @ 2380043682500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2380970086500. Starting simulation... +info: Entering event queue @ 2381043682500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2381970086500. Starting simulation... +info: Entering event queue @ 2382043682500. Starting simulation... switching cpus -info: Entering event queue @ 2381970242000. Starting simulation... +info: Entering event queue @ 2382043698000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2382970242000. Starting simulation... +info: Entering event queue @ 2383043698000. Starting simulation... switching cpus -info: Entering event queue @ 2382978620000. Starting simulation... +info: Entering event queue @ 2383051750000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2383978620000. Starting simulation... +info: Entering event queue @ 2384051750000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2384978620000. Starting simulation... +info: Entering event queue @ 2385051750000. Starting simulation... switching cpus -info: Entering event queue @ 2384978773000. Starting simulation... +info: Entering event queue @ 2385051891000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2385978773000. Starting simulation... +info: Entering event queue @ 2386051891000. Starting simulation... +info: Entering event queue @ 2386051935000. Starting simulation... switching cpus -info: Entering event queue @ 2385978776000. Starting simulation... +info: Entering event queue @ 2386052242750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2386978776000. Starting simulation... +info: Entering event queue @ 2387052242750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2387978776000. Starting simulation... +info: Entering event queue @ 2388052242750. Starting simulation... switching cpus -info: Entering event queue @ 2387978777500. Starting simulation... +info: Entering event queue @ 2388052250250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2388978777500. Starting simulation... +info: Entering event queue @ 2389052250250. Starting simulation... switching cpus -info: Entering event queue @ 2388978785000. Starting simulation... +info: Entering event queue @ 2389052257750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2389978785000. Starting simulation... +info: Entering event queue @ 2390052257750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2390978785000. Starting simulation... +info: Entering event queue @ 2391052257750. Starting simulation... switching cpus -info: Entering event queue @ 2390978786000. Starting simulation... +info: Entering event queue @ 2391052265250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2391978786000. Starting simulation... -info: Entering event queue @ 2391978831000. Starting simulation... -info: Entering event queue @ 2391978840500. Starting simulation... -info: Entering event queue @ 2391978845000. Starting simulation... +info: Entering event queue @ 2392052265250. Starting simulation... switching cpus -info: Entering event queue @ 2391978846000. Starting simulation... +info: Entering event queue @ 2392062139500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 2393062139500. Starting simulation... switching cpus -info: Entering event queue @ 2392978846000. Starting simulation... +info: Entering event queue @ 2393062140000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2393978846000. Starting simulation... -info: Entering event queue @ 2394705526000. Starting simulation... +info: Entering event queue @ 2394062140000. Starting simulation... +info: Entering event queue @ 2394135530000. Starting simulation... switching cpus -info: Entering event queue @ 2394705528000. Starting simulation... +info: Entering event queue @ 2394135532000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2395705528000. Starting simulation... +info: Entering event queue @ 2395135532000. Starting simulation... switching cpus -info: Entering event queue @ 2395708224000. Starting simulation... +info: Entering event queue @ 2395135538000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2396708224000. Starting simulation... +info: Entering event queue @ 2396135538000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2397708224000. Starting simulation... +info: Entering event queue @ 2397135538000. Starting simulation... switching cpus -info: Entering event queue @ 2397708236000. Starting simulation... +info: Entering event queue @ 2397135545500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2398708236000. Starting simulation... +info: Entering event queue @ 2398135545500. Starting simulation... switching cpus -info: Entering event queue @ 2398708269500. Starting simulation... +info: Entering event queue @ 2398135611000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2399708269500. Starting simulation... +info: Entering event queue @ 2399135611000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2400708269500. Starting simulation... +info: Entering event queue @ 2400135611000. Starting simulation... switching cpus -info: Entering event queue @ 2400708271500. Starting simulation... +info: Entering event queue @ 2400135618500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 7a69bab79..6bf02cff4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,175 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401336 # Number of seconds simulated -sim_ticks 2401336466000 # Number of ticks simulated -final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400708 # Number of seconds simulated +sim_ticks 2400708253000 # Number of ticks simulated +final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184517 # Simulator instruction rate (inst/s) -host_op_rate 236966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7343776984 # Simulator tick rate (ticks/s) -host_mem_usage 427572 # Number of bytes of host memory used -host_seconds 326.99 # Real time elapsed on the host -sim_insts 60334938 # Number of instructions simulated -sim_ops 77485485 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 71724 # Simulator instruction rate (inst/s) +host_op_rate 92116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2854182500 # Simulator tick rate (ticks/s) +host_mem_usage 441348 # Number of bytes of host memory used +host_seconds 841.12 # Real time elapsed on the host +sim_insts 60328852 # Number of instructions simulated +sim_ops 77480507 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7113744 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 84352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1286200 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 84352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3747008 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111186 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58547 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812501 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47827166 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2963186 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 535759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51926879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2817012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47827166 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3583907 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12617991 # Total number of read requests seen -system.physmem.writeReqs 398645 # Total number of write requests seen -system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807551424 # Total number of bytes read from memory -system.physmem.bytesWritten 25513280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1088176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54743891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12544378 # Total number of read requests seen +system.physmem.writeReqs 398835 # Total number of write requests seen +system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 802840192 # Total number of bytes read from memory +system.physmem.bytesWritten 25525440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102301752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2640780 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 2352 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 784491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 784138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 784232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 784566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 784404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 784106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 784266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 784324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 783997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 783399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 783436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 783681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 783642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 783494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 783837 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 784365 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24877 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24782 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24972 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400301266000 # Total gap between requests +system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry +system.physmem.totGap 2399673084000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::2 14 # Categorize read packet sizes +system.physmem.readPktSize::3 12509600 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35064 # Categorize read packet sizes +system.physmem.readPktSize::6 34764 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381229 # Categorize write packet sizes +system.physmem.writePktSize::2 381411 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17416 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17424 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 811080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 787373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 793054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2980679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2247655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2247973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2236496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 48996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 48907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 132798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 90866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,326 +177,356 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see -system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests -system.physmem.totBusLat 63089955000 # Total cycles spent in databus access -system.physmem.totBankLat 12731042500 # Total cycles spent in bank access -system.physmem.avgQLat 21968.79 # Average queueing delay per request -system.physmem.avgBankLat 1008.96 # Average bank access latency per request +system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see +system.physmem.totQLat 275491085000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 350869643750 # Sum of mem lat for all requests +system.physmem.totBusLat 62721890000 # Total cycles spent in databus access +system.physmem.totBankLat 12656668750 # Total cycles spent in bank access +system.physmem.avgQLat 21961.32 # Average queueing delay per request +system.physmem.avgBankLat 1008.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27977.75 # Average memory access latency -system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27970.27 # Average memory access latency +system.physmem.avgRdBW 334.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.61 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage +system.physmem.busUtil 2.70 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563370 # Number of row buffer hits during reads -system.physmem.writeRowHits 392291 # Number of row buffer hits during writes +system.physmem.readRowHits 12490088 # Number of row buffer hits during reads +system.physmem.writeRowHits 392491 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184402.58 # Average gap between requests -system.l2c.replacements 63266 # number of replacements -system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use -system.l2c.total_refs 1749187 # Total number of references to valid blocks. -system.l2c.sampled_refs 128660 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.595422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor +system.physmem.avgGap 185400.11 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 63256 # number of replacements +system.l2c.tagsinuse 50350.042137 # Cycle average of tags in use +system.l2c.total_refs 1749849 # Total number of references to valid blocks. +system.l2c.sampled_refs 128650 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.601625 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374435455000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36844.077748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5145.178956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3770.285257 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.231814 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 751.654048 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 12.723407 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1461.831435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1586.827913 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562010 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5153.281590 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3773.823073 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 798.045066 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.763007 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 4.909443 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.003957 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1438.233653 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.911142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562196 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078509 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057530 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078633 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057584 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011469 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022306 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024213 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768457 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461136 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 170235 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 134711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65741 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 17822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284203 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 137164 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290958 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597590 # number of Writeback hits -system.l2c.Writeback_hits::total 597590 # number of Writeback hits +system.l2c.occ_percent::cpu1.inst 0.012177 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011410 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.021946 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024245 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768281 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3206 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 462948 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169043 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2530 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 132569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 139144 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291227 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597831 # number of Writeback hits +system.l2c.Writeback_hits::total 597831 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61031 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19032 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33560 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113623 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3213 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461136 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 231266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 134711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 17822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 284203 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 170724 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404581 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3213 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461136 # number of overall hits -system.l2c.overall_hits::cpu0.data 231266 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2537 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1106 # number of overall hits -system.l2c.overall_hits::cpu1.inst 134711 # number of overall hits -system.l2c.overall_hits::cpu1.data 84773 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 17822 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits -system.l2c.overall_hits::cpu2.inst 284203 # number of overall hits -system.l2c.overall_hits::cpu2.data 170724 # number of overall hits -system.l2c.overall_hits::total 1404581 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19416 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113594 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3206 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 462948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 132569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 84682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284351 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 172535 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404821 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8858 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3206 # number of overall hits +system.l2c.overall_hits::cpu0.inst 462948 # number of overall hits +system.l2c.overall_hits::cpu0.data 229830 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2530 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1092 # number of overall hits +system.l2c.overall_hits::cpu1.inst 132569 # number of overall hits +system.l2c.overall_hits::cpu1.data 84682 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18106 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4114 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284351 # number of overall hits +system.l2c.overall_hits::cpu2.data 172535 # number of overall hits +system.l2c.overall_hits::total 1404821 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6349 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7451 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1339 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1210 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2574 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21682 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1194 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2765 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2549 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21668 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9583 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 18426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu1.data 507 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 980 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105561 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9656 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18147 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133364 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 111708 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7451 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111942 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10793 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2790 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21000 # number of demand (read+write) misses -system.l2c.demand_misses::total 155050 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1318 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2765 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20696 # number of demand (read+write) misses +system.l2c.demand_misses::total 155032 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7403 # number of overall misses -system.l2c.overall_misses::cpu0.data 111708 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7451 # number of overall misses +system.l2c.overall_misses::cpu0.data 111942 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1339 # number of overall misses -system.l2c.overall_misses::cpu1.data 10793 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2790 # number of overall misses -system.l2c.overall_misses::cpu2.data 21000 # number of overall misses -system.l2c.overall_misses::total 155050 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1318 # number of overall misses +system.l2c.overall_misses::cpu1.data 10850 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2765 # number of overall misses +system.l2c.overall_misses::cpu2.data 20696 # number of overall misses +system.l2c.overall_misses::total 155032 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 76508500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69917500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 783000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 178873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 152904999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 479056499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 69000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 160500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 429692000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 973653500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1403345500 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 73618000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 68964500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 344500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 180915000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 155129499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 479109499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 115000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 90000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 433667500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 956422000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1390089500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 76508500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 499609500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 783000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 178873500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1126558499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1882401999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 73618000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 502632000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 344500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 180915000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1111551499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1869198999 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 76508500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 499609500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 783000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 178873500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1126558499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1882401999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 468539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 176584 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1106 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 136050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 66951 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 17835 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 286993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 139738 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312640 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597590 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597590 # number of Writeback accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 73618000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 502632000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 344500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 180915000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1111551499 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1869198999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8859 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3208 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 470399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 175424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2531 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1092 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 133887 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 66460 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18111 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 287116 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 141693 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312895 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597831 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597831 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 499 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1000 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166390 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28615 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 51986 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246991 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 468539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 342974 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 136050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 95566 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 17835 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 286993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 191724 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559631 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 468539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 342974 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 136050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 95566 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 17835 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 286993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 191724 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559631 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000622 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015800 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035955 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009842 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.018073 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009721 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018420 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016518 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu1.data 511 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 995 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2940 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166348 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 29072 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51538 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246958 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8859 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 470399 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341772 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2531 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1092 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 133887 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 95532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18111 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4115 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 287116 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 193231 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559853 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8859 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 470399 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341772 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2531 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1092 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 133887 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 95532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18111 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4115 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 287116 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 193231 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559853 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000623 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036375 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017966 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000243 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.017990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016504 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991984 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989772 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.633205 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.334894 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.354442 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539971 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000622 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015800 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.325704 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009842 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112938 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009721 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109532 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099415 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000622 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015800 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.325704 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009842 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112938 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009721 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109532 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099415 # miss rate for overall accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992172 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984925 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989116 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.634579 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332141 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.352109 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540027 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.327534 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009844 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.113575 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000243 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.107105 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099389 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.327534 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009844 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.113575 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000243 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.107105 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099389 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57138.536221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 57783.057851 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64112.365591 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 59403.651515 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 22094.663730 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.848485 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 69.908815 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 55.287633 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44838.985704 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52841.284055 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 10522.355438 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55855.842185 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57759.212730 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 68900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65430.379747 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 60858.963907 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22111.385407 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 226.824458 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 91.836735 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 70.495186 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44911.712925 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52704.138425 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10423.273897 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12140.612699 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12056.859223 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12140.612699 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12056.859223 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,8 +535,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58534 # number of writebacks -system.l2c.writebacks::total 58534 # number of writebacks +system.l2c.writebacks::writebacks 58547 # number of writebacks +system.l2c.writebacks::total 58547 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits @@ -522,122 +544,142 @@ system.l2c.demand_mshr_hits::total 8 # nu system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1339 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1210 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 13 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2790 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2566 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7919 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9583 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 18426 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28009 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1318 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1194 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 5 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2765 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2541 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7825 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 507 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 980 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1487 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9656 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18147 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 27803 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1339 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10793 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2790 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20992 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 35928 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1318 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2765 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20688 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 35628 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1339 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10793 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2790 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20992 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 35928 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1318 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2765 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20688 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 35628 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59716089 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54808460 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 621263 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144123701 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 120589158 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 379914922 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4988470 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14859457 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 310362321 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 743903257 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1054265578 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57085318 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54060944 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 281255 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 146465179 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 123133891 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 381139089 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5113480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9800980 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14914460 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313418646 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 730113588 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1043532234 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 59716089 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 365170781 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 621263 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 144123701 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 864492415 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1434180500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 57085318 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 367479590 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 281255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 146465179 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 853247479 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1424671323 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 59716089 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 365170781 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 621263 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 144123701 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 864492415 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1434180500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25160642000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26578724012 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51739366012 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647954364 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9829694360 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10477648724 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25808596364 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36408418372 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62217014736 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018073 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018363 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006033 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991984 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.505285 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334894 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354442 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.113401 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023036 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 57085318 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 367479590 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 281255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 146465179 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 853247479 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1424671323 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25256982500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26555773011 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51812755511 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 643112863 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9826950545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10470063408 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25900095363 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36382723556 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62282818919 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005960 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992172 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984925 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505782 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.332141 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.352109 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.112582 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022841 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022841 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45277.172529 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48458.831562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48707.870799 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10085.759369 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.899126 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32458.434756 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40233.294098 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37533.080387 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -656,436 +698,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8079595 # DTB read hits -system.cpu0.dtb.read_misses 6254 # DTB read misses -system.cpu0.dtb.write_hits 6630051 # DTB write hits -system.cpu0.dtb.write_misses 2055 # DTB write misses +system.cpu0.dtb.read_hits 8066044 # DTB read hits +system.cpu0.dtb.read_misses 6218 # DTB read misses +system.cpu0.dtb.write_hits 6637384 # DTB write hits +system.cpu0.dtb.write_misses 2035 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8085849 # DTB read accesses -system.cpu0.dtb.write_accesses 6632106 # DTB write accesses +system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8072262 # DTB read accesses +system.cpu0.dtb.write_accesses 6639419 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14709646 # DTB hits -system.cpu0.dtb.misses 8309 # DTB misses -system.cpu0.dtb.accesses 14717955 # DTB accesses -system.cpu0.itb.inst_hits 32707746 # ITB inst hits -system.cpu0.itb.inst_misses 3496 # ITB inst misses +system.cpu0.dtb.hits 14703428 # DTB hits +system.cpu0.dtb.misses 8253 # DTB misses +system.cpu0.dtb.accesses 14711681 # DTB accesses +system.cpu0.itb.inst_hits 32696148 # ITB inst hits +system.cpu0.itb.inst_misses 3481 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses -system.cpu0.itb.hits 32707746 # DTB hits -system.cpu0.itb.misses 3496 # DTB misses -system.cpu0.itb.accesses 32711242 # DTB accesses -system.cpu0.numCycles 113988289 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32699629 # ITB inst accesses +system.cpu0.itb.hits 32696148 # DTB hits +system.cpu0.itb.misses 3481 # DTB misses +system.cpu0.itb.accesses 32699629 # DTB accesses +system.cpu0.numCycles 114001235 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32205724 # Number of instructions committed -system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses -system.cpu0.num_func_calls 1187729 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37554027 # number of integer instructions -system.cpu0.num_fp_insts 5120 # number of float instructions -system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written -system.cpu0.num_mem_refs 15372618 # number of memory refs -system.cpu0.num_load_insts 8447076 # Number of load instructions -system.cpu0.num_store_insts 6925542 # Number of store instructions -system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles -system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles -system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles +system.cpu0.committedInsts 32202356 # Number of instructions committed +system.cpu0.committedOps 42405748 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37555932 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses +system.cpu0.num_func_calls 1189098 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4237826 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37555932 # number of integer instructions +system.cpu0.num_fp_insts 5136 # number of float instructions +system.cpu0.num_int_register_reads 191328019 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39633304 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu0.num_mem_refs 15368046 # number of memory refs +system.cpu0.num_load_insts 8434010 # Number of load instructions +system.cpu0.num_store_insts 6934036 # Number of store instructions +system.cpu0.num_idle_cycles 13414288023.648659 # Number of idle cycles +system.cpu0.num_busy_cycles -13300286788.648659 # Number of busy cycles +system.cpu0.not_idle_fraction -116.667918 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.667918 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed -system.cpu0.icache.replacements 892496 # number of replacements -system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use -system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.202829 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934428 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.035106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.029693 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32241170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8377396 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3742426 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44360992 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32241170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8377396 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3742426 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44360992 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32241170 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8377396 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3742426 # number of overall hits -system.cpu0.icache.overall_hits::total 44360992 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469261 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 136323 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311228 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916812 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469261 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 136323 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311228 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916812 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469261 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 136323 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311228 # number of overall misses -system.cpu0.icache.overall_misses::total 916812 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1838935000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152917486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5991852486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1838935000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4152917486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5991852486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1838935000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4152917486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5991852486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32710431 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8513719 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45277804 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32710431 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8513719 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4053654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45277804 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32710431 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8513719 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4053654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45277804 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014346 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016012 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076777 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020249 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014346 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016012 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076777 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020249 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014346 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016012 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076777 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020249 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.543217 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13343.649948 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6535.530170 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6535.530170 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6535.530170 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3861 # number of cycles access was blocked +system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed +system.cpu0.icache.replacements 892329 # number of replacements +system.cpu0.icache.tagsinuse 511.602586 # Cycle average of tags in use +system.cpu0.icache.total_refs 44224471 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 892841 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.532303 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 8120621000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 478.364653 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.665639 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 15.572294 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.934306 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034503 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.030415 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32227698 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8245303 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3751470 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44224471 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32227698 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8245303 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3751470 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44224471 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32227698 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8245303 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3751470 # number of overall hits +system.cpu0.icache.overall_hits::total 44224471 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 471122 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 134159 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311537 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 471122 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 134159 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311537 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 471122 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 134159 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311537 # number of overall misses +system.cpu0.icache.overall_misses::total 916818 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1808055500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4158384493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5966439993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1808055500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4158384493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5966439993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1808055500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4158384493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5966439993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32698820 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8379462 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4063007 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45141289 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32698820 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8379462 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4063007 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45141289 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32698820 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8379462 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4063007 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45141289 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014408 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016010 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076676 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020310 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014408 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016010 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076676 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020310 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014408 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016010 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076676 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020310 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.960174 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.963462 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6507.769255 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6507.769255 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6507.769255 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5517 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.550000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.292308 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23796 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23796 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23796 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23796 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23796 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23796 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136323 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287432 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 423755 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 136323 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 287432 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 423755 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 136323 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 287432 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 423755 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1566289000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3388078986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4954367986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1566289000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3388078986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4954367986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1566289000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3388078986 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4954367986 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.585907 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23964 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23964 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23964 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23964 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23964 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23964 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134159 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287573 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 421732 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 134159 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287573 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 421732 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 134159 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287573 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 421732 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1539737500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3392264993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4932002493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1539737500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3392264993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4932002493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1539737500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3392264993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4932002493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009342 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009342 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009342 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.636625 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629752 # number of replacements -system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23211225 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630264 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.827782 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 630023 # number of replacements +system.cpu0.dcache.tagsinuse 511.997115 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23223254 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630535 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.831031 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.729006 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.821503 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.446607 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968221 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019183 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012591 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.880002 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.605532 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.511582 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968516 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.018761 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012718 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6959921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1905228 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4437258 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13302407 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5951579 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1349529 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2119159 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9420267 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34182 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72930 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238178 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137461 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35898 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74040 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247399 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12911500 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3254757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6556417 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22722674 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12911500 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3254757 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6556417 # number of overall hits -system.cpu0.dcache.overall_hits::total 22722674 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170189 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65235 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 281776 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 517200 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167824 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29114 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 599232 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 796170 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6395 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1716 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11986 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 338013 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94349 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 881008 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1313370 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 338013 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94349 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 881008 # number of overall misses -system.cpu0.dcache.overall_misses::total 1313370 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910187500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4059279000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4969466500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 718682500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18333372895 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19052055395 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22464000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52254000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74718000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1628870000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22392651895 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24021521895 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1628870000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22392651895 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24021521895 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7130110 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1970463 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4719034 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13819607 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6119403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1378643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2718391 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137461 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35898 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76805 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250164 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74042 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13249513 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3349106 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7437425 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24036044 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13249513 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3349106 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7437425 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24036044 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023869 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033106 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059711 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037425 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027425 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220436 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077930 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046522 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047802 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047913 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025511 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028171 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118456 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054642 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025511 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028171 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118456 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054642 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13952.441174 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.049486 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9608.403906 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24685.117126 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30594.782814 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23929.632359 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.909091 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13484.903226 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6233.772735 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18289.988271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18289.988271 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9551 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.762385 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.434783 # average number of cycles each access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 6947766 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1882163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4477345 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13307274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5958886 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1342354 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2125973 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9427213 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131324 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34069 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72982 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238375 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137698 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35791 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73904 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12906652 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3224517 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6603318 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22734487 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12906652 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3224517 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6603318 # number of overall hits +system.cpu0.dcache.overall_hits::total 22734487 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169050 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 64738 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 285084 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 518872 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167782 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29583 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 591784 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 789149 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1722 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3871 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336832 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94321 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 876868 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1308021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336832 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 94321 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 876868 # number of overall misses +system.cpu0.dcache.overall_misses::total 1308021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 902894500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4121906000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5024800500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 728179000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17993273399 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 18721452399 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22543500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52244000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74787500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1631073500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22115179399 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 23746252899 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1631073500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22115179399 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 23746252899 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7116816 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1946901 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4762429 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13826146 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6126668 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1371937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2717757 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137698 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35791 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250342 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137698 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35791 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73908 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13243484 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3318838 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7480186 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24042508 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13243484 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3318838 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7480186 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24042508 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023754 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033252 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059861 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021563 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217747 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077244 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046290 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048113 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050369 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047803 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025434 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028420 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117225 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054405 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025434 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028420 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117225 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054405 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13946.901356 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14458.566598 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9684.084900 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24614.778758 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30405.136670 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23723.596430 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.463415 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13496.254198 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6249.477730 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18154.336130 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18154.336130 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8894 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1121 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 44 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.933988 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.886364 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks -system.cpu0.dcache.writebacks::total 597590 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597831 # number of writebacks +system.cpu0.dcache.writebacks::total 597831 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146824 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146824 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539280 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 539280 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 409 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 409 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 686104 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 686104 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 686104 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 686104 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138260 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202998 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29583 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52504 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82087 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1722 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5184 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94321 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190764 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285085 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94321 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190764 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285085 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773418500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795552000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568970500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 669013000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1403739991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2072752991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19099500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40608500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59708000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442431500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3199291991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4641723491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442431500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3199291991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4641723491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592956500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28992541000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56585497500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276098000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147117763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423215763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28869054500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43139658763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 72008713263 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033252 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029031 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014682 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021563 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019319 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008035 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048113 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020708 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011858 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011858 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11946.901356 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12986.778533 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.151775 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22614.778758 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26735.867572 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25250.685139 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.463415 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11729.780474 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11517.746914 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,388 +1140,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2185339 # DTB read hits -system.cpu1.dtb.read_misses 2099 # DTB read misses -system.cpu1.dtb.write_hits 1465312 # DTB write hits -system.cpu1.dtb.write_misses 382 # DTB write misses +system.cpu1.dtb.read_hits 2162379 # DTB read hits +system.cpu1.dtb.read_misses 2097 # DTB read misses +system.cpu1.dtb.write_hits 1458481 # DTB write hits +system.cpu1.dtb.write_misses 389 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2187438 # DTB read accesses -system.cpu1.dtb.write_accesses 1465694 # DTB write accesses +system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2164476 # DTB read accesses +system.cpu1.dtb.write_accesses 1458870 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3650651 # DTB hits -system.cpu1.dtb.misses 2481 # DTB misses -system.cpu1.dtb.accesses 3653132 # DTB accesses -system.cpu1.itb.inst_hits 8513719 # ITB inst hits -system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.dtb.hits 3620860 # DTB hits +system.cpu1.dtb.misses 2486 # DTB misses +system.cpu1.dtb.accesses 3623346 # DTB accesses +system.cpu1.itb.inst_hits 8379462 # ITB inst hits +system.cpu1.itb.inst_misses 1132 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses -system.cpu1.itb.hits 8513719 # DTB hits -system.cpu1.itb.misses 1131 # DTB misses -system.cpu1.itb.accesses 8514850 # DTB accesses -system.cpu1.numCycles 574637078 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8380594 # ITB inst accesses +system.cpu1.itb.hits 8379462 # DTB hits +system.cpu1.itb.misses 1132 # DTB misses +system.cpu1.itb.accesses 8380594 # DTB accesses +system.cpu1.numCycles 573333879 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8294211 # Number of instructions committed -system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses -system.cpu1.num_func_calls 319530 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9421872 # number of integer instructions -system.cpu1.num_fp_insts 2078 # number of float instructions -system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3824850 # number of memory refs -system.cpu1.num_load_insts 2281405 # Number of load instructions -system.cpu1.num_store_insts 1543445 # Number of store instructions -system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles -system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles -system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles +system.cpu1.committedInsts 8178203 # Number of instructions committed +system.cpu1.committedOps 10418210 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9330752 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses +system.cpu1.num_func_calls 315480 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1141385 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9330752 # number of integer instructions +system.cpu1.num_fp_insts 1998 # number of float instructions +system.cpu1.num_int_register_reads 53785556 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10103056 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written +system.cpu1.num_mem_refs 3793769 # number of memory refs +system.cpu1.num_load_insts 2257716 # Number of load instructions +system.cpu1.num_store_insts 1536053 # Number of store instructions +system.cpu1.num_idle_cycles 537669981.200710 # Number of idle cycles +system.cpu1.num_busy_cycles 35663897.799290 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062204 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937796 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4687055 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits +system.cpu2.branchPred.lookups 4726334 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843092 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222010 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 2958856 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2529751 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.497604 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412073 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21648 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10844149 # DTB read hits -system.cpu2.dtb.read_misses 22603 # DTB read misses -system.cpu2.dtb.write_hits 3263914 # DTB write hits -system.cpu2.dtb.write_misses 5857 # DTB write misses +system.cpu2.dtb.read_hits 10884010 # DTB read hits +system.cpu2.dtb.read_misses 22849 # DTB read misses +system.cpu2.dtb.write_hits 3265307 # DTB write hits +system.cpu2.dtb.write_misses 5901 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 675 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 176 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10866752 # DTB read accesses -system.cpu2.dtb.write_accesses 3269771 # DTB write accesses +system.cpu2.dtb.perms_faults 462 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10906859 # DTB read accesses +system.cpu2.dtb.write_accesses 3271208 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14108063 # DTB hits -system.cpu2.dtb.misses 28460 # DTB misses -system.cpu2.dtb.accesses 14136523 # DTB accesses -system.cpu2.itb.inst_hits 4055013 # ITB inst hits -system.cpu2.itb.inst_misses 4560 # ITB inst misses +system.cpu2.dtb.hits 14149317 # DTB hits +system.cpu2.dtb.misses 28750 # DTB misses +system.cpu2.dtb.accesses 14178067 # DTB accesses +system.cpu2.itb.inst_hits 4064296 # ITB inst hits +system.cpu2.itb.inst_misses 4509 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1562 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 968 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses -system.cpu2.itb.hits 4055013 # DTB hits -system.cpu2.itb.misses 4560 # DTB misses -system.cpu2.itb.accesses 4059573 # DTB accesses -system.cpu2.numCycles 88254759 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4068805 # ITB inst accesses +system.cpu2.itb.hits 4064296 # DTB hits +system.cpu2.itb.misses 4509 # DTB misses +system.cpu2.itb.accesses 4068805 # DTB accesses +system.cpu2.numCycles 88279018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9458864 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32433194 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4726334 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941824 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6832879 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1816174 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51286 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19337351 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 2080 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 975 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33815 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 56915 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 312 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4063011 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 310021 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1911 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37021672 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050656 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436806 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30193705 81.56% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383800 1.04% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509282 1.38% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 813035 2.20% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 655040 1.77% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344627 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1013096 2.74% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 238978 0.65% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2870109 7.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37021672 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053539 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367394 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10074280 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19273281 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6183203 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 295071 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1194753 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 612486 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53708 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36748038 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181597 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1194753 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10649029 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6564844 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11163009 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5883991 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1564995 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34501786 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2424 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 422794 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 878812 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 93 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37014698 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157694934 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157667196 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27738 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25798325 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11216372 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231057 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207527 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3357295 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6536002 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3838530 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 533894 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 787090 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31736542 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511835 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34275347 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54662 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7411950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19918044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155690 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37021672 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580792 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24452597 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3909614 10.56% 76.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2349010 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1972018 5.33% 88.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2798812 7.56% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 886009 2.39% 98.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 484017 1.31% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 134496 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35099 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37021672 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18701 1.22% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1408658 91.63% 92.85% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109949 7.15% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61376 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19371931 56.52% 56.70% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11383572 33.21% 89.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3432179 10.01% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued -system.cpu2.iq.rate 0.386887 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34275347 # Type of FU issued +system.cpu2.iq.rate 0.388262 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537308 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044852 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107186070 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39665615 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27402348 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6887 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3783 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3156 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35747644 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3635 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 208180 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1582611 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1901 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9388 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582353 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5366761 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352360 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1194753 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4874895 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91791 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32329432 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60600 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6536002 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3838530 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369520 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31433 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2533 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9388 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105889 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88624 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194513 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33284218 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11095059 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 991129 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 72670 # number of nop insts executed -system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3670278 # Number of branches executed -system.cpu2.iew.exec_stores 3398105 # Number of stores executed -system.cpu2.iew.exec_rate 0.375646 # Inst execution rate -system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15591378 # num instructions producing a value -system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value +system.cpu2.iew.exec_nop 81055 # number of nop insts executed +system.cpu2.iew.exec_refs 14494094 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3696710 # Number of branches executed +system.cpu2.iew.exec_stores 3399035 # Number of stores executed +system.cpu2.iew.exec_rate 0.377034 # Inst execution rate +system.cpu2.iew.wb_sent 32864100 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27405504 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15677727 # num instructions producing a value +system.cpu2.iew.wb_consumers 28502633 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.310442 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.550045 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7348668 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356145 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169071 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35826783 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.689728 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.717733 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27184585 75.88% 75.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4182145 11.67% 87.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258559 3.51% 91.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 654760 1.83% 92.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 571167 1.59% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 316320 0.88% 95.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 401210 1.12% 96.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 290625 0.81% 97.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 967412 2.70% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19883492 # Number of instructions committed -system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35826783 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20002486 # Number of instructions committed +system.cpu2.commit.committedOps 24710742 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8174125 # Number of memory references committed -system.cpu2.commit.loads 4916766 # Number of loads committed -system.cpu2.commit.membars 94500 # Number of memory barriers committed -system.cpu2.commit.branches 3146107 # Number of branches committed -system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions. -system.cpu2.commit.function_calls 293773 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8209568 # Number of memory references committed +system.cpu2.commit.loads 4953391 # Number of loads committed +system.cpu2.commit.membars 94240 # Number of memory barriers committed +system.cpu2.commit.branches 3168906 # Number of branches committed +system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21931175 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294969 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 967412 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66150526 # The number of ROB reads -system.cpu2.rob.rob_writes 64978873 # The number of ROB writes -system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19835003 # Number of Instructions Simulated -system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated -system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads -system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes +system.cpu2.rob.rob_reads 66393860 # The number of ROB reads +system.cpu2.rob.rob_writes 65354684 # The number of ROB writes +system.cpu2.timesIdled 360581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51257346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567291742 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19948293 # Number of Instructions Simulated +system.cpu2.committedOps 24656549 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19948293 # Number of Instructions Simulated +system.cpu2.cpi 4.425392 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.425392 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225969 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225969 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153783407 # number of integer regfile reads +system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9021581 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1536,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 975317722127 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 975317722127 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 975317722127 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 975317722127 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 4166fc5d7..e2c3921ac 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 5a85b4fca..42bd5914c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -18,3 +19,5 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 3d5d4d8cd..23d3f50f7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:10:12 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:19:45 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second @@ -15,2599 +15,2610 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1000000000. Starting simulation... switching cpus -info: Entering event queue @ 1000004500. Starting simulation... +info: Entering event queue @ 1000007500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2000004500. Starting simulation... +info: Entering event queue @ 2000007500. Starting simulation... switching cpus -info: Entering event queue @ 2000028000. Starting simulation... +info: Entering event queue @ 2000059000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3000028000. Starting simulation... +info: Entering event queue @ 3000059000. Starting simulation... switching cpus -info: Entering event queue @ 3000031000. Starting simulation... +info: Entering event queue @ 3000062500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 4000031000. Starting simulation... +info: Entering event queue @ 4000062500. Starting simulation... switching cpus -info: Entering event queue @ 4000247000. Starting simulation... +info: Entering event queue @ 4000382000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5000247000. Starting simulation... +info: Entering event queue @ 5000382000. Starting simulation... +info: Entering event queue @ 5000388500. Starting simulation... switching cpus -info: Entering event queue @ 5000410000. Starting simulation... +info: Entering event queue @ 5000393500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 6000410000. Starting simulation... -info: Entering event queue @ 6000457500. Starting simulation... -info: Entering event queue @ 6000493000. Starting simulation... +info: Entering event queue @ 6000393500. Starting simulation... switching cpus -info: Entering event queue @ 6000497500. Starting simulation... +info: Entering event queue @ 6000471000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 7000497500. Starting simulation... -info: Entering event queue @ 7000507000. Starting simulation... +info: Entering event queue @ 7000471000. Starting simulation... +info: Entering event queue @ 7000479500. Starting simulation... switching cpus -info: Entering event queue @ 7000511500. Starting simulation... +info: Entering event queue @ 7000484000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 8000511500. Starting simulation... +info: Entering event queue @ 8000484000. Starting simulation... switching cpus -info: Entering event queue @ 8000635000. Starting simulation... +info: Entering event queue @ 8000798500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 9000635000. Starting simulation... +info: Entering event queue @ 9000798500. Starting simulation... +info: Entering event queue @ 9000819500. Starting simulation... +info: Entering event queue @ 9000821500. Starting simulation... switching cpus -info: Entering event queue @ 9000641000. Starting simulation... +info: Entering event queue @ 9000826000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 10000641000. Starting simulation... +info: Entering event queue @ 10000826000. Starting simulation... switching cpus -info: Entering event queue @ 10000646500. Starting simulation... +info: Entering event queue @ 10000828500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 11000646500. Starting simulation... +info: Entering event queue @ 11000828500. Starting simulation... switching cpus -info: Entering event queue @ 11000922500. Starting simulation... +info: Entering event queue @ 11000860500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 12000922500. Starting simulation... -info: Entering event queue @ 12000932500. Starting simulation... +info: Entering event queue @ 12000860500. Starting simulation... switching cpus -info: Entering event queue @ 12000937000. Starting simulation... +info: Entering event queue @ 12000871500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 13000937000. Starting simulation... -info: Entering event queue @ 13000946500. Starting simulation... +info: Entering event queue @ 13000871500. Starting simulation... switching cpus -info: Entering event queue @ 13000951000. Starting simulation... +info: Entering event queue @ 13000879000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 14000951000. Starting simulation... +info: Entering event queue @ 14000879000. Starting simulation... +info: Entering event queue @ 14000902000. Starting simulation... +info: Entering event queue @ 14000911000. Starting simulation... switching cpus -info: Entering event queue @ 14000960000. Starting simulation... +info: Entering event queue @ 14000916504. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 15000960000. Starting simulation... -info: Entering event queue @ 15000966000. Starting simulation... +info: Entering event queue @ 15000916504. Starting simulation... +info: Entering event queue @ 15000925500. Starting simulation... +info: Entering event queue @ 15000931500. Starting simulation... switching cpus -info: Entering event queue @ 15000970500. Starting simulation... +info: Entering event queue @ 15000936000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 16000970500. Starting simulation... +info: Entering event queue @ 16000936000. Starting simulation... switching cpus -info: Entering event queue @ 16001125000. Starting simulation... +info: Entering event queue @ 16001197000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 17001125000. Starting simulation... +info: Entering event queue @ 17001197000. Starting simulation... switching cpus -info: Entering event queue @ 25966288000. Starting simulation... +info: Entering event queue @ 26026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 26966288000. Starting simulation... +info: Entering event queue @ 27026543000. Starting simulation... switching cpus -info: Entering event queue @ 35966288000. Starting simulation... +info: Entering event queue @ 36026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 36966288000. Starting simulation... +info: Entering event queue @ 37026543000. Starting simulation... switching cpus -info: Entering event queue @ 45966288000. Starting simulation... +info: Entering event queue @ 46026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 46966288000. Starting simulation... -info: Entering event queue @ 48430354000. Starting simulation... +info: Entering event queue @ 47026543000. Starting simulation... +info: Entering event queue @ 48597551000. Starting simulation... switching cpus -info: Entering event queue @ 48430356000. Starting simulation... +info: Entering event queue @ 48597553000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 49430356000. Starting simulation... +info: Entering event queue @ 49597553000. Starting simulation... switching cpus -info: Entering event queue @ 49430481500. Starting simulation... +info: Entering event queue @ 49597756250. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 50430481500. Starting simulation... +info: Entering event queue @ 50597756250. Starting simulation... switching cpus -info: Entering event queue @ 50430618000. Starting simulation... +info: Entering event queue @ 50597763750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 51430618000. Starting simulation... +info: Entering event queue @ 51597763750. Starting simulation... switching cpus -info: Entering event queue @ 51430627000. Starting simulation... +info: Entering event queue @ 51597906750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 52430627000. Starting simulation... -info: Entering event queue @ 52430630500. Starting simulation... +info: Entering event queue @ 52597906750. Starting simulation... +info: Entering event queue @ 52597914250. Starting simulation... +info: Entering event queue @ 52597920000. Starting simulation... switching cpus -info: Entering event queue @ 52430635000. Starting simulation... +info: Entering event queue @ 52597924500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 53430635000. Starting simulation... +info: Entering event queue @ 53597924500. Starting simulation... +info: Entering event queue @ 53597946500. Starting simulation... switching cpus -info: Entering event queue @ 53430641000. Starting simulation... +info: Entering event queue @ 53597952000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 54430641000. Starting simulation... -info: Entering event queue @ 54430651500. Starting simulation... +info: Entering event queue @ 54597952000. Starting simulation... switching cpus -info: Entering event queue @ 54430656000. Starting simulation... +info: Entering event queue @ 54597974500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 55430656000. Starting simulation... -info: Entering event queue @ 55430664500. Starting simulation... +info: Entering event queue @ 55597974500. Starting simulation... +info: Entering event queue @ 55597991000. Starting simulation... +info: Entering event queue @ 55597997500. Starting simulation... switching cpus -info: Entering event queue @ 55430669000. Starting simulation... +info: Entering event queue @ 55598002000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 56430669000. Starting simulation... +info: Entering event queue @ 56598002000. Starting simulation... switching cpus -info: Entering event queue @ 56430965500. Starting simulation... +info: Entering event queue @ 56598009500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 57430965500. Starting simulation... +info: Entering event queue @ 57598009500. Starting simulation... +info: Entering event queue @ 57598017000. Starting simulation... +info: Entering event queue @ 57598021000. Starting simulation... switching cpus -info: Entering event queue @ 65966288000. Starting simulation... +info: Entering event queue @ 57598025500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 66966288000. Starting simulation... +info: Entering event queue @ 58598025500. Starting simulation... switching cpus -info: Entering event queue @ 75966288000. Starting simulation... +info: Entering event queue @ 66026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 76966288000. Starting simulation... +info: Entering event queue @ 67026543000. Starting simulation... switching cpus -info: Entering event queue @ 85966288000. Starting simulation... +info: Entering event queue @ 76026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 86966288000. Starting simulation... +info: Entering event queue @ 77026543000. Starting simulation... switching cpus -info: Entering event queue @ 95966288000. Starting simulation... +info: Entering event queue @ 86026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 96966288000. Starting simulation... +info: Entering event queue @ 87026543000. Starting simulation... switching cpus -info: Entering event queue @ 105966288000. Starting simulation... +info: Entering event queue @ 96026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 106966288000. Starting simulation... +info: Entering event queue @ 97026543000. Starting simulation... switching cpus -info: Entering event queue @ 115966288000. Starting simulation... +info: Entering event queue @ 106026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 116966288000. Starting simulation... +info: Entering event queue @ 107026543000. Starting simulation... switching cpus -info: Entering event queue @ 125966288000. Starting simulation... +info: Entering event queue @ 116026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 126966288000. Starting simulation... +info: Entering event queue @ 117026543000. Starting simulation... switching cpus -info: Entering event queue @ 135966288000. Starting simulation... +info: Entering event queue @ 126026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 136966288000. Starting simulation... +info: Entering event queue @ 127026543000. Starting simulation... switching cpus -info: Entering event queue @ 145966288000. Starting simulation... +info: Entering event queue @ 136026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 146966288000. Starting simulation... +info: Entering event queue @ 137026543000. Starting simulation... switching cpus -info: Entering event queue @ 155966288000. Starting simulation... +info: Entering event queue @ 146026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 156966288000. Starting simulation... +info: Entering event queue @ 147026543000. Starting simulation... switching cpus -info: Entering event queue @ 165966288000. Starting simulation... +info: Entering event queue @ 156026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 166966288000. Starting simulation... +info: Entering event queue @ 157026543000. Starting simulation... switching cpus -info: Entering event queue @ 175966288000. Starting simulation... +info: Entering event queue @ 166026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 176966288000. Starting simulation... +info: Entering event queue @ 167026543000. Starting simulation... switching cpus -info: Entering event queue @ 185966288000. Starting simulation... +info: Entering event queue @ 176026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 186966288000. Starting simulation... +info: Entering event queue @ 177026543000. Starting simulation... switching cpus -info: Entering event queue @ 195966288000. Starting simulation... +info: Entering event queue @ 186026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 196966288000. Starting simulation... +info: Entering event queue @ 187026543000. Starting simulation... switching cpus -info: Entering event queue @ 205966288000. Starting simulation... +info: Entering event queue @ 196026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 206966288000. Starting simulation... -info: Entering event queue @ 206966298000. Starting simulation... -info: Entering event queue @ 206966304500. Starting simulation... +info: Entering event queue @ 197026543000. Starting simulation... switching cpus -info: Entering event queue @ 206966309000. Starting simulation... +info: Entering event queue @ 206026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 207966309000. Starting simulation... +info: Entering event queue @ 207026543000. Starting simulation... switching cpus -info: Entering event queue @ 215966288000. Starting simulation... +info: Entering event queue @ 216026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 216966288000. Starting simulation... +info: Entering event queue @ 217026543000. Starting simulation... switching cpus -info: Entering event queue @ 225966288000. Starting simulation... +info: Entering event queue @ 217026554500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 226966288000. Starting simulation... +info: Entering event queue @ 218026554500. Starting simulation... switching cpus -info: Entering event queue @ 235966288000. Starting simulation... +info: Entering event queue @ 226026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 236966288000. Starting simulation... +info: Entering event queue @ 227026543000. Starting simulation... switching cpus -info: Entering event queue @ 245966288000. Starting simulation... +info: Entering event queue @ 236026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 246966288000. Starting simulation... +info: Entering event queue @ 237026543000. Starting simulation... switching cpus -info: Entering event queue @ 255966288000. Starting simulation... +info: Entering event queue @ 246026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 256966288000. Starting simulation... +info: Entering event queue @ 247026543000. Starting simulation... switching cpus -info: Entering event queue @ 265966288000. Starting simulation... +info: Entering event queue @ 256026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 266966288000. Starting simulation... -info: Entering event queue @ 275966288000. Starting simulation... -info: Entering event queue @ 276772747000. Starting simulation... +info: Entering event queue @ 257026543000. Starting simulation... switching cpus -info: Entering event queue @ 276772749000. Starting simulation... +info: Entering event queue @ 266026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 277772749000. Starting simulation... +info: Entering event queue @ 267026543000. Starting simulation... +info: Entering event queue @ 276026543000. Starting simulation... +info: Entering event queue @ 276896939000. Starting simulation... switching cpus -info: Entering event queue @ 285966288000. Starting simulation... +info: Entering event queue @ 276896941000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 286966288000. Starting simulation... +info: Entering event queue @ 277896941000. Starting simulation... switching cpus -info: Entering event queue @ 295966288000. Starting simulation... +info: Entering event queue @ 286026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 296966288000. Starting simulation... +info: Entering event queue @ 287026543000. Starting simulation... switching cpus -info: Entering event queue @ 305966288000. Starting simulation... +info: Entering event queue @ 296026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 306966288000. Starting simulation... +info: Entering event queue @ 297026543000. Starting simulation... switching cpus -info: Entering event queue @ 315966288000. Starting simulation... +info: Entering event queue @ 306026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 316966288000. Starting simulation... +info: Entering event queue @ 307026543000. Starting simulation... switching cpus -info: Entering event queue @ 325966288000. Starting simulation... +info: Entering event queue @ 316026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 326966288000. Starting simulation... +info: Entering event queue @ 317026543000. Starting simulation... switching cpus -info: Entering event queue @ 335966288000. Starting simulation... +info: Entering event queue @ 326026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 336966288000. Starting simulation... +info: Entering event queue @ 327026543000. Starting simulation... switching cpus -info: Entering event queue @ 345966288000. Starting simulation... +info: Entering event queue @ 336026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 346966288000. Starting simulation... +info: Entering event queue @ 337026543000. Starting simulation... switching cpus -info: Entering event queue @ 355966288000. Starting simulation... +info: Entering event queue @ 346026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 356966288000. Starting simulation... +info: Entering event queue @ 347026543000. Starting simulation... switching cpus -info: Entering event queue @ 365966288000. Starting simulation... +info: Entering event queue @ 356026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 366966288000. Starting simulation... +info: Entering event queue @ 357026543000. Starting simulation... switching cpus -info: Entering event queue @ 375966288000. Starting simulation... +info: Entering event queue @ 366026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 376966288000. Starting simulation... +info: Entering event queue @ 367026543000. Starting simulation... switching cpus -info: Entering event queue @ 385966288000. Starting simulation... +info: Entering event queue @ 376026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 386966288000. Starting simulation... +info: Entering event queue @ 377026543000. Starting simulation... switching cpus -info: Entering event queue @ 395966288000. Starting simulation... +info: Entering event queue @ 386026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 396966288000. Starting simulation... +info: Entering event queue @ 387026543000. Starting simulation... switching cpus -info: Entering event queue @ 405966288000. Starting simulation... +info: Entering event queue @ 396026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 406966288000. Starting simulation... +info: Entering event queue @ 397026543000. Starting simulation... switching cpus -info: Entering event queue @ 415966288000. Starting simulation... +info: Entering event queue @ 406026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 416966288000. Starting simulation... +info: Entering event queue @ 407026543000. Starting simulation... switching cpus -info: Entering event queue @ 425966288000. Starting simulation... +info: Entering event queue @ 416026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 426966288000. Starting simulation... +info: Entering event queue @ 417026543000. Starting simulation... switching cpus -info: Entering event queue @ 435966288000. Starting simulation... +info: Entering event queue @ 426026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 436966288000. Starting simulation... +info: Entering event queue @ 427026543000. Starting simulation... switching cpus -info: Entering event queue @ 445966288000. Starting simulation... +info: Entering event queue @ 436026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 446966288000. Starting simulation... +info: Entering event queue @ 437026543000. Starting simulation... switching cpus -info: Entering event queue @ 455966288000. Starting simulation... +info: Entering event queue @ 446026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 456966288000. Starting simulation... +info: Entering event queue @ 447026543000. Starting simulation... switching cpus -info: Entering event queue @ 465966288000. Starting simulation... +info: Entering event queue @ 456026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 466966288000. Starting simulation... +info: Entering event queue @ 457026543000. Starting simulation... switching cpus -info: Entering event queue @ 475966288000. Starting simulation... +info: Entering event queue @ 466026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 476966288000. Starting simulation... +info: Entering event queue @ 467026543000. Starting simulation... switching cpus -info: Entering event queue @ 485966288000. Starting simulation... +info: Entering event queue @ 476026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 486966288000. Starting simulation... +info: Entering event queue @ 477026543000. Starting simulation... switching cpus -info: Entering event queue @ 495966288000. Starting simulation... +info: Entering event queue @ 486026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 496966288000. Starting simulation... +info: Entering event queue @ 487026543000. Starting simulation... switching cpus -info: Entering event queue @ 505966288000. Starting simulation... +info: Entering event queue @ 496026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 506966288000. Starting simulation... +info: Entering event queue @ 497026543000. Starting simulation... +info: Entering event queue @ 506026543000. Starting simulation... +info: Entering event queue @ 506050935000. Starting simulation... switching cpus -info: Entering event queue @ 515966288000. Starting simulation... +info: Entering event queue @ 506050937000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 516966288000. Starting simulation... +info: Entering event queue @ 507050937000. Starting simulation... switching cpus -info: Entering event queue @ 525966288000. Starting simulation... +info: Entering event queue @ 516026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 526966288000. Starting simulation... +info: Entering event queue @ 517026543000. Starting simulation... switching cpus -info: Entering event queue @ 535966288000. Starting simulation... +info: Entering event queue @ 526026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 536966288000. Starting simulation... +info: Entering event queue @ 527026543000. Starting simulation... switching cpus -info: Entering event queue @ 545966288000. Starting simulation... +info: Entering event queue @ 536026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 546966288000. Starting simulation... +info: Entering event queue @ 537026543000. Starting simulation... switching cpus -info: Entering event queue @ 555966288000. Starting simulation... +info: Entering event queue @ 546026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 556966288000. Starting simulation... +info: Entering event queue @ 547026543000. Starting simulation... switching cpus -info: Entering event queue @ 565966288000. Starting simulation... +info: Entering event queue @ 556026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 566966288000. Starting simulation... +info: Entering event queue @ 557026543000. Starting simulation... switching cpus -info: Entering event queue @ 575966288000. Starting simulation... +info: Entering event queue @ 566026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 576966288000. Starting simulation... +info: Entering event queue @ 567026543000. Starting simulation... switching cpus -info: Entering event queue @ 585966288000. Starting simulation... +info: Entering event queue @ 576026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 586966288000. Starting simulation... +info: Entering event queue @ 577026543000. Starting simulation... switching cpus -info: Entering event queue @ 595966288000. Starting simulation... +info: Entering event queue @ 586026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 596966288000. Starting simulation... +info: Entering event queue @ 587026543000. Starting simulation... switching cpus -info: Entering event queue @ 605966288000. Starting simulation... +info: Entering event queue @ 596026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 606966288000. Starting simulation... +info: Entering event queue @ 597026543000. Starting simulation... switching cpus -info: Entering event queue @ 615966288000. Starting simulation... +info: Entering event queue @ 606026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 616966288000. Starting simulation... +info: Entering event queue @ 607026543000. Starting simulation... switching cpus -info: Entering event queue @ 625966288000. Starting simulation... +info: Entering event queue @ 616026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 626966288000. Starting simulation... -info: Entering event queue @ 635966288000. Starting simulation... -info: Entering event queue @ 636871372000. Starting simulation... +info: Entering event queue @ 617026543000. Starting simulation... switching cpus -info: Entering event queue @ 636871374000. Starting simulation... +info: Entering event queue @ 626026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 637871374000. Starting simulation... +info: Entering event queue @ 627026543000. Starting simulation... +info: Entering event queue @ 636026543000. Starting simulation... +info: Entering event queue @ 636994938000. Starting simulation... switching cpus -info: Entering event queue @ 645966288000. Starting simulation... +info: Entering event queue @ 636994940000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 646966288000. Starting simulation... +info: Entering event queue @ 637994940000. Starting simulation... switching cpus -info: Entering event queue @ 655966288000. Starting simulation... +info: Entering event queue @ 646026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 656966288000. Starting simulation... +info: Entering event queue @ 647026543000. Starting simulation... switching cpus -info: Entering event queue @ 665966288000. Starting simulation... +info: Entering event queue @ 656026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 666966288000. Starting simulation... +info: Entering event queue @ 657026543000. Starting simulation... switching cpus -info: Entering event queue @ 675966288000. Starting simulation... +info: Entering event queue @ 666026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 676966288000. Starting simulation... +info: Entering event queue @ 667026543000. Starting simulation... switching cpus -info: Entering event queue @ 685966288000. Starting simulation... +info: Entering event queue @ 676026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 686966288000. Starting simulation... +info: Entering event queue @ 677026543000. Starting simulation... switching cpus -info: Entering event queue @ 695966288000. Starting simulation... +info: Entering event queue @ 686026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 696966288000. Starting simulation... +info: Entering event queue @ 687026543000. Starting simulation... switching cpus -info: Entering event queue @ 705966288000. Starting simulation... +info: Entering event queue @ 696026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 706966288000. Starting simulation... +info: Entering event queue @ 697026543000. Starting simulation... switching cpus -info: Entering event queue @ 715966288000. Starting simulation... +info: Entering event queue @ 706026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 716966288000. Starting simulation... +info: Entering event queue @ 707026543000. Starting simulation... switching cpus -info: Entering event queue @ 725966288000. Starting simulation... +info: Entering event queue @ 716026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 726966288000. Starting simulation... +info: Entering event queue @ 717026543000. Starting simulation... switching cpus -info: Entering event queue @ 735966288000. Starting simulation... +info: Entering event queue @ 726026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 736966288000. Starting simulation... +info: Entering event queue @ 727026543000. Starting simulation... switching cpus -info: Entering event queue @ 745966288000. Starting simulation... +info: Entering event queue @ 736026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 746966288000. Starting simulation... +info: Entering event queue @ 737026543000. Starting simulation... switching cpus -info: Entering event queue @ 755966288000. Starting simulation... +info: Entering event queue @ 746026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 756966288000. Starting simulation... +info: Entering event queue @ 747026543000. Starting simulation... switching cpus -info: Entering event queue @ 765966288000. Starting simulation... +info: Entering event queue @ 756026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 766966288000. Starting simulation... +info: Entering event queue @ 757026543000. Starting simulation... switching cpus -info: Entering event queue @ 775966288000. Starting simulation... +info: Entering event queue @ 766026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 776966288000. Starting simulation... +info: Entering event queue @ 767026543000. Starting simulation... switching cpus -info: Entering event queue @ 785966288000. Starting simulation... +info: Entering event queue @ 776026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 786966288000. Starting simulation... +info: Entering event queue @ 777026543000. Starting simulation... switching cpus -info: Entering event queue @ 795966288000. Starting simulation... +info: Entering event queue @ 786026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 796966288000. Starting simulation... +info: Entering event queue @ 787026543000. Starting simulation... switching cpus -info: Entering event queue @ 805966288000. Starting simulation... +info: Entering event queue @ 796026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 806966288000. Starting simulation... +info: Entering event queue @ 797026543000. Starting simulation... switching cpus -info: Entering event queue @ 815966288000. Starting simulation... +info: Entering event queue @ 806026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 816966288000. Starting simulation... +info: Entering event queue @ 807026543000. Starting simulation... switching cpus -info: Entering event queue @ 825966288000. Starting simulation... +info: Entering event queue @ 816026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 826966288000. Starting simulation... +info: Entering event queue @ 817026543000. Starting simulation... switching cpus -info: Entering event queue @ 835966288000. Starting simulation... +info: Entering event queue @ 826026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 836966288000. Starting simulation... +info: Entering event queue @ 827026543000. Starting simulation... switching cpus -info: Entering event queue @ 845966288000. Starting simulation... +info: Entering event queue @ 836026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 846966288000. Starting simulation... +info: Entering event queue @ 837026543000. Starting simulation... switching cpus -info: Entering event queue @ 855966288000. Starting simulation... +info: Entering event queue @ 846026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 856966288000. Starting simulation... -info: Entering event queue @ 865966288000. Starting simulation... -info: Entering event queue @ 866025280000. Starting simulation... +info: Entering event queue @ 847026543000. Starting simulation... switching cpus -info: Entering event queue @ 866025282000. Starting simulation... +info: Entering event queue @ 856026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 867025282000. Starting simulation... +info: Entering event queue @ 857026543000. Starting simulation... +info: Entering event queue @ 866026543000. Starting simulation... +info: Entering event queue @ 866148955000. Starting simulation... switching cpus -info: Entering event queue @ 875966288000. Starting simulation... +info: Entering event queue @ 866148957000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 876966288000. Starting simulation... +info: Entering event queue @ 867148957000. Starting simulation... switching cpus -info: Entering event queue @ 885966288000. Starting simulation... +info: Entering event queue @ 876026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 886966288000. Starting simulation... +info: Entering event queue @ 877026543000. Starting simulation... switching cpus -info: Entering event queue @ 895966288000. Starting simulation... +info: Entering event queue @ 886026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 896966288000. Starting simulation... +info: Entering event queue @ 887026543000. Starting simulation... switching cpus -info: Entering event queue @ 905966288000. Starting simulation... +info: Entering event queue @ 896026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 906966288000. Starting simulation... +info: Entering event queue @ 897026543000. Starting simulation... switching cpus -info: Entering event queue @ 915966288000. Starting simulation... +info: Entering event queue @ 906026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 916966288000. Starting simulation... +info: Entering event queue @ 907026543000. Starting simulation... switching cpus -info: Entering event queue @ 925966288000. Starting simulation... +info: Entering event queue @ 916026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 926966288000. Starting simulation... +info: Entering event queue @ 917026543000. Starting simulation... switching cpus -info: Entering event queue @ 935966288000. Starting simulation... +info: Entering event queue @ 926026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 936966288000. Starting simulation... +info: Entering event queue @ 927026543000. Starting simulation... switching cpus -info: Entering event queue @ 945966288000. Starting simulation... +info: Entering event queue @ 936026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 946966288000. Starting simulation... +info: Entering event queue @ 937026543000. Starting simulation... switching cpus -info: Entering event queue @ 955966288000. Starting simulation... +info: Entering event queue @ 946026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 956966288000. Starting simulation... +info: Entering event queue @ 947026543000. Starting simulation... switching cpus -info: Entering event queue @ 965966288000. Starting simulation... +info: Entering event queue @ 956026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 966966288000. Starting simulation... +info: Entering event queue @ 957026543000. Starting simulation... switching cpus -info: Entering event queue @ 975966288000. Starting simulation... +info: Entering event queue @ 966026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 976966288000. Starting simulation... +info: Entering event queue @ 967026543000. Starting simulation... switching cpus -info: Entering event queue @ 985966288000. Starting simulation... +info: Entering event queue @ 976026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 986966288000. Starting simulation... -info: Entering event queue @ 995966288000. Starting simulation... -info: Entering event queue @ 996970147000. Starting simulation... +info: Entering event queue @ 977026543000. Starting simulation... switching cpus -info: Entering event queue @ 996970149000. Starting simulation... +info: Entering event queue @ 986026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 997970149000. Starting simulation... +info: Entering event queue @ 987026543000. Starting simulation... +info: Entering event queue @ 996026543000. Starting simulation... +info: Entering event queue @ 997094339000. Starting simulation... switching cpus -info: Entering event queue @ 1005966288000. Starting simulation... +info: Entering event queue @ 997094341000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1006966288000. Starting simulation... +info: Entering event queue @ 998094341000. Starting simulation... switching cpus -info: Entering event queue @ 1015966288000. Starting simulation... +info: Entering event queue @ 1006026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1016966288000. Starting simulation... +info: Entering event queue @ 1007026543000. Starting simulation... switching cpus -info: Entering event queue @ 1025966288000. Starting simulation... +info: Entering event queue @ 1016026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1026966288000. Starting simulation... +info: Entering event queue @ 1017026543000. Starting simulation... switching cpus -info: Entering event queue @ 1035966288000. Starting simulation... +info: Entering event queue @ 1026026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1036966288000. Starting simulation... +info: Entering event queue @ 1027026543000. Starting simulation... switching cpus -info: Entering event queue @ 1045966288000. Starting simulation... +info: Entering event queue @ 1036026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1046966288000. Starting simulation... +info: Entering event queue @ 1037026543000. Starting simulation... switching cpus -info: Entering event queue @ 1055966288000. Starting simulation... +info: Entering event queue @ 1046026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1056966288000. Starting simulation... +info: Entering event queue @ 1047026543000. Starting simulation... switching cpus -info: Entering event queue @ 1065966288000. Starting simulation... +info: Entering event queue @ 1056026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1066966288000. Starting simulation... +info: Entering event queue @ 1057026543000. Starting simulation... switching cpus -info: Entering event queue @ 1075966288000. Starting simulation... +info: Entering event queue @ 1066026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1076966288000. Starting simulation... +info: Entering event queue @ 1067026543000. Starting simulation... switching cpus -info: Entering event queue @ 1085966288000. Starting simulation... +info: Entering event queue @ 1076026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1086966288000. Starting simulation... +info: Entering event queue @ 1077026543000. Starting simulation... switching cpus -info: Entering event queue @ 1095966288000. Starting simulation... +info: Entering event queue @ 1086026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1096966288000. Starting simulation... +info: Entering event queue @ 1087026543000. Starting simulation... switching cpus -info: Entering event queue @ 1105966288000. Starting simulation... +info: Entering event queue @ 1096026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1106966288000. Starting simulation... +info: Entering event queue @ 1097026543000. Starting simulation... switching cpus -info: Entering event queue @ 1115966288000. Starting simulation... +info: Entering event queue @ 1106026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1116966288000. Starting simulation... +info: Entering event queue @ 1107026543000. Starting simulation... switching cpus -info: Entering event queue @ 1125966288000. Starting simulation... +info: Entering event queue @ 1116026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1126966288000. Starting simulation... +info: Entering event queue @ 1117026543000. Starting simulation... switching cpus -info: Entering event queue @ 1135966288000. Starting simulation... +info: Entering event queue @ 1126026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1136966288000. Starting simulation... +info: Entering event queue @ 1127026543000. Starting simulation... switching cpus -info: Entering event queue @ 1145966288000. Starting simulation... +info: Entering event queue @ 1136026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1146966288000. Starting simulation... +info: Entering event queue @ 1137026543000. Starting simulation... switching cpus -info: Entering event queue @ 1155966288000. Starting simulation... +info: Entering event queue @ 1146026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1156966288000. Starting simulation... +info: Entering event queue @ 1147026543000. Starting simulation... switching cpus -info: Entering event queue @ 1165966288000. Starting simulation... +info: Entering event queue @ 1156026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1166966288000. Starting simulation... +info: Entering event queue @ 1157026543000. Starting simulation... switching cpus -info: Entering event queue @ 1175966288000. Starting simulation... +info: Entering event queue @ 1166026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1176966288000. Starting simulation... +info: Entering event queue @ 1167026543000. Starting simulation... switching cpus -info: Entering event queue @ 1185966288000. Starting simulation... +info: Entering event queue @ 1176026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1186966288000. Starting simulation... +info: Entering event queue @ 1177026543000. Starting simulation... switching cpus -info: Entering event queue @ 1195966288000. Starting simulation... +info: Entering event queue @ 1186026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1196966288000. Starting simulation... +info: Entering event queue @ 1187026543000. Starting simulation... switching cpus -info: Entering event queue @ 1205966288000. Starting simulation... +info: Entering event queue @ 1196026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1206966288000. Starting simulation... +info: Entering event queue @ 1197026543000. Starting simulation... switching cpus -info: Entering event queue @ 1215966288000. Starting simulation... +info: Entering event queue @ 1206026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1216966288000. Starting simulation... -info: Entering event queue @ 1225966288000. Starting simulation... -info: Entering event queue @ 1226123905000. Starting simulation... +info: Entering event queue @ 1207026543000. Starting simulation... switching cpus -info: Entering event queue @ 1226123907000. Starting simulation... +info: Entering event queue @ 1216026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1227123907000. Starting simulation... +info: Entering event queue @ 1217026543000. Starting simulation... +info: Entering event queue @ 1226026543000. Starting simulation... +info: Entering event queue @ 1226248314000. Starting simulation... switching cpus -info: Entering event queue @ 1235966288000. Starting simulation... +info: Entering event queue @ 1226248316000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1236966288000. Starting simulation... +info: Entering event queue @ 1227248316000. Starting simulation... switching cpus -info: Entering event queue @ 1245966288000. Starting simulation... +info: Entering event queue @ 1236026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1246966288000. Starting simulation... +info: Entering event queue @ 1237026543000. Starting simulation... switching cpus -info: Entering event queue @ 1255966288000. Starting simulation... +info: Entering event queue @ 1246026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1256966288000. Starting simulation... +info: Entering event queue @ 1247026543000. Starting simulation... switching cpus -info: Entering event queue @ 1265966288000. Starting simulation... +info: Entering event queue @ 1256026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1266966288000. Starting simulation... +info: Entering event queue @ 1257026543000. Starting simulation... switching cpus -info: Entering event queue @ 1275966288000. Starting simulation... +info: Entering event queue @ 1266026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1276966288000. Starting simulation... +info: Entering event queue @ 1267026543000. Starting simulation... switching cpus -info: Entering event queue @ 1285966288000. Starting simulation... +info: Entering event queue @ 1276026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1286966288000. Starting simulation... +info: Entering event queue @ 1277026543000. Starting simulation... switching cpus -info: Entering event queue @ 1295966288000. Starting simulation... +info: Entering event queue @ 1286026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1296966288000. Starting simulation... +info: Entering event queue @ 1287026543000. Starting simulation... switching cpus -info: Entering event queue @ 1305966288000. Starting simulation... +info: Entering event queue @ 1296026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1306966288000. Starting simulation... +info: Entering event queue @ 1297026543000. Starting simulation... switching cpus -info: Entering event queue @ 1315966288000. Starting simulation... +info: Entering event queue @ 1306026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1316966288000. Starting simulation... +info: Entering event queue @ 1307026543000. Starting simulation... switching cpus -info: Entering event queue @ 1325966288000. Starting simulation... +info: Entering event queue @ 1316026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1326966288000. Starting simulation... +info: Entering event queue @ 1317026543000. Starting simulation... switching cpus -info: Entering event queue @ 1335966288000. Starting simulation... +info: Entering event queue @ 1326026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1336966288000. Starting simulation... +info: Entering event queue @ 1327026543000. Starting simulation... switching cpus -info: Entering event queue @ 1345966288000. Starting simulation... +info: Entering event queue @ 1336026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1346966288000. Starting simulation... -info: Entering event queue @ 1355966288000. Starting simulation... -info: Entering event queue @ 1357069231000. Starting simulation... +info: Entering event queue @ 1337026543000. Starting simulation... switching cpus -info: Entering event queue @ 1357069233000. Starting simulation... +info: Entering event queue @ 1346026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1358069233000. Starting simulation... +info: Entering event queue @ 1347026543000. Starting simulation... +info: Entering event queue @ 1356026543000. Starting simulation... +info: Entering event queue @ 1357193547000. Starting simulation... switching cpus -info: Entering event queue @ 1365966288000. Starting simulation... +info: Entering event queue @ 1357193549000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1366966288000. Starting simulation... +info: Entering event queue @ 1358193549000. Starting simulation... switching cpus -info: Entering event queue @ 1375966288000. Starting simulation... +info: Entering event queue @ 1366026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1376966288000. Starting simulation... +info: Entering event queue @ 1367026543000. Starting simulation... switching cpus -info: Entering event queue @ 1385966288000. Starting simulation... +info: Entering event queue @ 1376026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1386966288000. Starting simulation... +info: Entering event queue @ 1377026543000. Starting simulation... switching cpus -info: Entering event queue @ 1395966288000. Starting simulation... +info: Entering event queue @ 1386026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1396966288000. Starting simulation... +info: Entering event queue @ 1387026543000. Starting simulation... switching cpus -info: Entering event queue @ 1405966288000. Starting simulation... +info: Entering event queue @ 1396026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1406966288000. Starting simulation... +info: Entering event queue @ 1397026543000. Starting simulation... switching cpus -info: Entering event queue @ 1415966288000. Starting simulation... +info: Entering event queue @ 1406026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1416966288000. Starting simulation... +info: Entering event queue @ 1407026543000. Starting simulation... switching cpus -info: Entering event queue @ 1425966288000. Starting simulation... +info: Entering event queue @ 1416026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1426966288000. Starting simulation... +info: Entering event queue @ 1417026543000. Starting simulation... switching cpus -info: Entering event queue @ 1435966288000. Starting simulation... +info: Entering event queue @ 1426026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1436966288000. Starting simulation... +info: Entering event queue @ 1427026543000. Starting simulation... switching cpus -info: Entering event queue @ 1445966288000. Starting simulation... +info: Entering event queue @ 1436026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1446966288000. Starting simulation... +info: Entering event queue @ 1437026543000. Starting simulation... switching cpus -info: Entering event queue @ 1455966288000. Starting simulation... +info: Entering event queue @ 1446026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1456966288000. Starting simulation... +info: Entering event queue @ 1447026543000. Starting simulation... switching cpus -info: Entering event queue @ 1465966288000. Starting simulation... +info: Entering event queue @ 1456026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1466966288000. Starting simulation... +info: Entering event queue @ 1457026543000. Starting simulation... switching cpus -info: Entering event queue @ 1475966288000. Starting simulation... +info: Entering event queue @ 1466026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1476966288000. Starting simulation... +info: Entering event queue @ 1467026543000. Starting simulation... switching cpus -info: Entering event queue @ 1485966288000. Starting simulation... +info: Entering event queue @ 1476026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1486966288000. Starting simulation... +info: Entering event queue @ 1477026543000. Starting simulation... switching cpus -info: Entering event queue @ 1495966288000. Starting simulation... +info: Entering event queue @ 1486026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1496966288000. Starting simulation... +info: Entering event queue @ 1487026543000. Starting simulation... switching cpus -info: Entering event queue @ 1505966288000. Starting simulation... +info: Entering event queue @ 1496026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1506966288000. Starting simulation... +info: Entering event queue @ 1497026543000. Starting simulation... switching cpus -info: Entering event queue @ 1515966288000. Starting simulation... +info: Entering event queue @ 1506026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1516966288000. Starting simulation... +info: Entering event queue @ 1507026543000. Starting simulation... switching cpus -info: Entering event queue @ 1525966288000. Starting simulation... +info: Entering event queue @ 1516026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1526966288000. Starting simulation... +info: Entering event queue @ 1517026543000. Starting simulation... switching cpus -info: Entering event queue @ 1535966288000. Starting simulation... +info: Entering event queue @ 1526026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1536966288000. Starting simulation... +info: Entering event queue @ 1527026543000. Starting simulation... switching cpus -info: Entering event queue @ 1545966288000. Starting simulation... +info: Entering event queue @ 1536026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1546966288000. Starting simulation... +info: Entering event queue @ 1537026543000. Starting simulation... switching cpus -info: Entering event queue @ 1555966288000. Starting simulation... +info: Entering event queue @ 1546026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1556966288000. Starting simulation... +info: Entering event queue @ 1547026543000. Starting simulation... switching cpus -info: Entering event queue @ 1565966288000. Starting simulation... +info: Entering event queue @ 1556026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1566966288000. Starting simulation... +info: Entering event queue @ 1557026543000. Starting simulation... switching cpus -info: Entering event queue @ 1575966288000. Starting simulation... +info: Entering event queue @ 1566026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1576966288000. Starting simulation... -info: Entering event queue @ 1585966288000. Starting simulation... -info: Entering event queue @ 1586222989000. Starting simulation... +info: Entering event queue @ 1567026543000. Starting simulation... switching cpus -info: Entering event queue @ 1586222991000. Starting simulation... +info: Entering event queue @ 1576026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1587222991000. Starting simulation... +info: Entering event queue @ 1577026543000. Starting simulation... +info: Entering event queue @ 1586026543000. Starting simulation... +info: Entering event queue @ 1586347543000. Starting simulation... switching cpus -info: Entering event queue @ 1595966288000. Starting simulation... +info: Entering event queue @ 1586347545000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1596966288000. Starting simulation... +info: Entering event queue @ 1587347545000. Starting simulation... switching cpus -info: Entering event queue @ 1605966288000. Starting simulation... +info: Entering event queue @ 1596026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1606966288000. Starting simulation... +info: Entering event queue @ 1597026543000. Starting simulation... switching cpus -info: Entering event queue @ 1615966288000. Starting simulation... +info: Entering event queue @ 1606026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1616966288000. Starting simulation... +info: Entering event queue @ 1607026543000. Starting simulation... switching cpus -info: Entering event queue @ 1625966288000. Starting simulation... +info: Entering event queue @ 1616026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1626966288000. Starting simulation... +info: Entering event queue @ 1617026543000. Starting simulation... switching cpus -info: Entering event queue @ 1635966288000. Starting simulation... +info: Entering event queue @ 1626026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1636966288000. Starting simulation... +info: Entering event queue @ 1627026543000. Starting simulation... switching cpus -info: Entering event queue @ 1645966288000. Starting simulation... +info: Entering event queue @ 1636026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1646966288000. Starting simulation... +info: Entering event queue @ 1637026543000. Starting simulation... switching cpus -info: Entering event queue @ 1655966288000. Starting simulation... +info: Entering event queue @ 1646026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1656966288000. Starting simulation... +info: Entering event queue @ 1647026543000. Starting simulation... switching cpus -info: Entering event queue @ 1665966288000. Starting simulation... +info: Entering event queue @ 1656026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1666966288000. Starting simulation... +info: Entering event queue @ 1657026543000. Starting simulation... switching cpus -info: Entering event queue @ 1675966288000. Starting simulation... +info: Entering event queue @ 1666026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1676966288000. Starting simulation... +info: Entering event queue @ 1667026543000. Starting simulation... switching cpus -info: Entering event queue @ 1685966288000. Starting simulation... +info: Entering event queue @ 1676026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1686966288000. Starting simulation... +info: Entering event queue @ 1677026543000. Starting simulation... switching cpus -info: Entering event queue @ 1695966288000. Starting simulation... +info: Entering event queue @ 1686026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1696966288000. Starting simulation... +info: Entering event queue @ 1687026543000. Starting simulation... switching cpus -info: Entering event queue @ 1705966288000. Starting simulation... +info: Entering event queue @ 1696026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1706966288000. Starting simulation... -info: Entering event queue @ 1715966288000. Starting simulation... -info: Entering event queue @ 1717167856000. Starting simulation... +info: Entering event queue @ 1697026543000. Starting simulation... switching cpus -info: Entering event queue @ 1717167858000. Starting simulation... +info: Entering event queue @ 1706026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1718167858000. Starting simulation... +info: Entering event queue @ 1707026543000. Starting simulation... +info: Entering event queue @ 1716026543000. Starting simulation... +info: Entering event queue @ 1717291739000. Starting simulation... switching cpus -info: Entering event queue @ 1725966288000. Starting simulation... +info: Entering event queue @ 1717291741000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1726966288000. Starting simulation... +info: Entering event queue @ 1718291741000. Starting simulation... switching cpus -info: Entering event queue @ 1735966288000. Starting simulation... +info: Entering event queue @ 1726026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1736966288000. Starting simulation... +info: Entering event queue @ 1727026543000. Starting simulation... switching cpus -info: Entering event queue @ 1745966288000. Starting simulation... +info: Entering event queue @ 1736026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1746966288000. Starting simulation... +info: Entering event queue @ 1737026543000. Starting simulation... switching cpus -info: Entering event queue @ 1755966288000. Starting simulation... +info: Entering event queue @ 1746026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1756966288000. Starting simulation... +info: Entering event queue @ 1747026543000. Starting simulation... switching cpus -info: Entering event queue @ 1765966288000. Starting simulation... +info: Entering event queue @ 1756026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1766966288000. Starting simulation... +info: Entering event queue @ 1757026543000. Starting simulation... switching cpus -info: Entering event queue @ 1775966288000. Starting simulation... +info: Entering event queue @ 1766026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1776966288000. Starting simulation... +info: Entering event queue @ 1767026543000. Starting simulation... switching cpus -info: Entering event queue @ 1785966288000. Starting simulation... +info: Entering event queue @ 1776026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1786966288000. Starting simulation... +info: Entering event queue @ 1777026543000. Starting simulation... switching cpus -info: Entering event queue @ 1795966288000. Starting simulation... +info: Entering event queue @ 1786026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1796966288000. Starting simulation... +info: Entering event queue @ 1787026543000. Starting simulation... switching cpus -info: Entering event queue @ 1805966288000. Starting simulation... +info: Entering event queue @ 1796026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1806966288000. Starting simulation... +info: Entering event queue @ 1797026543000. Starting simulation... switching cpus -info: Entering event queue @ 1815966288000. Starting simulation... +info: Entering event queue @ 1806026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1816966288000. Starting simulation... +info: Entering event queue @ 1807026543000. Starting simulation... switching cpus -info: Entering event queue @ 1825966288000. Starting simulation... +info: Entering event queue @ 1816026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1826966288000. Starting simulation... +info: Entering event queue @ 1817026543000. Starting simulation... switching cpus -info: Entering event queue @ 1835966288000. Starting simulation... +info: Entering event queue @ 1826026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1836966288000. Starting simulation... +info: Entering event queue @ 1827026543000. Starting simulation... switching cpus -info: Entering event queue @ 1845966288000. Starting simulation... +info: Entering event queue @ 1836026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1846966288000. Starting simulation... +info: Entering event queue @ 1837026543000. Starting simulation... switching cpus -info: Entering event queue @ 1855966288000. Starting simulation... +info: Entering event queue @ 1846026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1856966288000. Starting simulation... +info: Entering event queue @ 1847026543000. Starting simulation... switching cpus -info: Entering event queue @ 1865966288000. Starting simulation... +info: Entering event queue @ 1856026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1866966288000. Starting simulation... +info: Entering event queue @ 1857026543000. Starting simulation... switching cpus -info: Entering event queue @ 1875966288000. Starting simulation... +info: Entering event queue @ 1866026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1876966288000. Starting simulation... +info: Entering event queue @ 1867026543000. Starting simulation... switching cpus -info: Entering event queue @ 1885966288000. Starting simulation... +info: Entering event queue @ 1876026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1886966288000. Starting simulation... +info: Entering event queue @ 1877026543000. Starting simulation... switching cpus -info: Entering event queue @ 1895966288000. Starting simulation... +info: Entering event queue @ 1886026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1896966288000. Starting simulation... +info: Entering event queue @ 1887026543000. Starting simulation... switching cpus -info: Entering event queue @ 1905966288000. Starting simulation... +info: Entering event queue @ 1896026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1906966288000. Starting simulation... +info: Entering event queue @ 1897026543000. Starting simulation... switching cpus -info: Entering event queue @ 1915966288000. Starting simulation... +info: Entering event queue @ 1906026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1916966288000. Starting simulation... +info: Entering event queue @ 1907026543000. Starting simulation... switching cpus -info: Entering event queue @ 1925966288000. Starting simulation... +info: Entering event queue @ 1916026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1926966288000. Starting simulation... +info: Entering event queue @ 1917026543000. Starting simulation... switching cpus -info: Entering event queue @ 1935966288000. Starting simulation... +info: Entering event queue @ 1926026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1936966288000. Starting simulation... -info: Entering event queue @ 1945966288000. Starting simulation... -info: Entering event queue @ 1946321761000. Starting simulation... +info: Entering event queue @ 1927026543000. Starting simulation... switching cpus -info: Entering event queue @ 1946321763000. Starting simulation... +info: Entering event queue @ 1936026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1947321763000. Starting simulation... +info: Entering event queue @ 1937026543000. Starting simulation... +info: Entering event queue @ 1946026543000. Starting simulation... +info: Entering event queue @ 1946445714000. Starting simulation... switching cpus -info: Entering event queue @ 1955966288000. Starting simulation... +info: Entering event queue @ 1946445716000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1956966288000. Starting simulation... +info: Entering event queue @ 1947445716000. Starting simulation... switching cpus -info: Entering event queue @ 1965966288000. Starting simulation... +info: Entering event queue @ 1956026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1966966288000. Starting simulation... +info: Entering event queue @ 1957026543000. Starting simulation... switching cpus -info: Entering event queue @ 1975966288000. Starting simulation... +info: Entering event queue @ 1966026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1976966288000. Starting simulation... +info: Entering event queue @ 1967026543000. Starting simulation... switching cpus -info: Entering event queue @ 1985966288000. Starting simulation... +info: Entering event queue @ 1976026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1986966288000. Starting simulation... +info: Entering event queue @ 1977026543000. Starting simulation... switching cpus -info: Entering event queue @ 1995966288000. Starting simulation... +info: Entering event queue @ 1986026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1996966288000. Starting simulation... +info: Entering event queue @ 1987026543000. Starting simulation... switching cpus -info: Entering event queue @ 2005966288000. Starting simulation... +info: Entering event queue @ 1996026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2006966288000. Starting simulation... +info: Entering event queue @ 1997026543000. Starting simulation... switching cpus -info: Entering event queue @ 2015966288000. Starting simulation... +info: Entering event queue @ 2006026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2016966288000. Starting simulation... +info: Entering event queue @ 2007026543000. Starting simulation... switching cpus -info: Entering event queue @ 2025966288000. Starting simulation... +info: Entering event queue @ 2016026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2026966288000. Starting simulation... +info: Entering event queue @ 2017026543000. Starting simulation... switching cpus -info: Entering event queue @ 2035966288000. Starting simulation... +info: Entering event queue @ 2026026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2036966288000. Starting simulation... +info: Entering event queue @ 2027026543000. Starting simulation... switching cpus -info: Entering event queue @ 2045966288000. Starting simulation... +info: Entering event queue @ 2036026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2046966288000. Starting simulation... +info: Entering event queue @ 2037026543000. Starting simulation... switching cpus -info: Entering event queue @ 2055966288000. Starting simulation... +info: Entering event queue @ 2046026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2056966288000. Starting simulation... +info: Entering event queue @ 2047026543000. Starting simulation... switching cpus -info: Entering event queue @ 2065966288000. Starting simulation... +info: Entering event queue @ 2056026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2066966288000. Starting simulation... -info: Entering event queue @ 2075966288000. Starting simulation... -info: Entering event queue @ 2077266937000. Starting simulation... +info: Entering event queue @ 2057026543000. Starting simulation... switching cpus -info: Entering event queue @ 2077266939000. Starting simulation... +info: Entering event queue @ 2066026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2078266939000. Starting simulation... +info: Entering event queue @ 2067026543000. Starting simulation... +info: Entering event queue @ 2076026543000. Starting simulation... +info: Entering event queue @ 2077390947000. Starting simulation... switching cpus -info: Entering event queue @ 2085966288000. Starting simulation... +info: Entering event queue @ 2077390949000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2086966288000. Starting simulation... +info: Entering event queue @ 2078390949000. Starting simulation... switching cpus -info: Entering event queue @ 2095966288000. Starting simulation... +info: Entering event queue @ 2086026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2096966288000. Starting simulation... +info: Entering event queue @ 2087026543000. Starting simulation... switching cpus -info: Entering event queue @ 2105966288000. Starting simulation... +info: Entering event queue @ 2096026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2106966288000. Starting simulation... +info: Entering event queue @ 2097026543000. Starting simulation... switching cpus -info: Entering event queue @ 2115966288000. Starting simulation... +info: Entering event queue @ 2106026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2116966288000. Starting simulation... +info: Entering event queue @ 2107026543000. Starting simulation... switching cpus -info: Entering event queue @ 2125966288000. Starting simulation... +info: Entering event queue @ 2116026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2126966288000. Starting simulation... +info: Entering event queue @ 2117026543000. Starting simulation... switching cpus -info: Entering event queue @ 2135966288000. Starting simulation... +info: Entering event queue @ 2126026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2136966288000. Starting simulation... +info: Entering event queue @ 2127026543000. Starting simulation... switching cpus -info: Entering event queue @ 2145966288000. Starting simulation... +info: Entering event queue @ 2136026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2146966288000. Starting simulation... +info: Entering event queue @ 2137026543000. Starting simulation... switching cpus -info: Entering event queue @ 2155966288000. Starting simulation... +info: Entering event queue @ 2146026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2156966288000. Starting simulation... +info: Entering event queue @ 2147026543000. Starting simulation... switching cpus -info: Entering event queue @ 2165966288000. Starting simulation... +info: Entering event queue @ 2156026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2166966288000. Starting simulation... +info: Entering event queue @ 2157026543000. Starting simulation... switching cpus -info: Entering event queue @ 2175966288000. Starting simulation... +info: Entering event queue @ 2166026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2176966288000. Starting simulation... +info: Entering event queue @ 2167026543000. Starting simulation... switching cpus -info: Entering event queue @ 2185966288000. Starting simulation... +info: Entering event queue @ 2176026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2186966288000. Starting simulation... +info: Entering event queue @ 2177026543000. Starting simulation... switching cpus -info: Entering event queue @ 2195966288000. Starting simulation... +info: Entering event queue @ 2186026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2196966288000. Starting simulation... +info: Entering event queue @ 2187026543000. Starting simulation... switching cpus -info: Entering event queue @ 2205966288000. Starting simulation... +info: Entering event queue @ 2196026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2206966288000. Starting simulation... +info: Entering event queue @ 2197026543000. Starting simulation... switching cpus -info: Entering event queue @ 2215966288000. Starting simulation... +info: Entering event queue @ 2206026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2216966288000. Starting simulation... +info: Entering event queue @ 2207026543000. Starting simulation... switching cpus -info: Entering event queue @ 2225966288000. Starting simulation... +info: Entering event queue @ 2216026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2226966288000. Starting simulation... +info: Entering event queue @ 2217026543000. Starting simulation... switching cpus -info: Entering event queue @ 2235966288000. Starting simulation... +info: Entering event queue @ 2226026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2236966288000. Starting simulation... +info: Entering event queue @ 2227026543000. Starting simulation... switching cpus -info: Entering event queue @ 2245966288000. Starting simulation... +info: Entering event queue @ 2236026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2246966288000. Starting simulation... +info: Entering event queue @ 2237026543000. Starting simulation... switching cpus -info: Entering event queue @ 2255966288000. Starting simulation... +info: Entering event queue @ 2246026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2256966288000. Starting simulation... +info: Entering event queue @ 2247026543000. Starting simulation... switching cpus -info: Entering event queue @ 2265966288000. Starting simulation... +info: Entering event queue @ 2256026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2266966288000. Starting simulation... +info: Entering event queue @ 2257026543000. Starting simulation... switching cpus -info: Entering event queue @ 2275966288000. Starting simulation... +info: Entering event queue @ 2266026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2276966288000. Starting simulation... -info: Entering event queue @ 2276966296500. Starting simulation... -info: Entering event queue @ 2276966301000. Starting simulation... +info: Entering event queue @ 2267026543000. Starting simulation... switching cpus -info: Entering event queue @ 2276966305500. Starting simulation... +info: Entering event queue @ 2276026543000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2277966305500. Starting simulation... -info: Entering event queue @ 2277966669500. Starting simulation... -info: Entering event queue @ 2277966675000. Starting simulation... +info: Entering event queue @ 2277026543000. Starting simulation... switching cpus -info: Entering event queue @ 2277966679500. Starting simulation... +info: Entering event queue @ 2277026550500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2278966679500. Starting simulation... +info: Entering event queue @ 2278026550500. Starting simulation... switching cpus -info: Entering event queue @ 2278966727000. Starting simulation... +info: Entering event queue @ 2278026844500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2279966727000. Starting simulation... +info: Entering event queue @ 2279026844500. Starting simulation... switching cpus -info: Entering event queue @ 2279966892500. Starting simulation... +info: Entering event queue @ 2279028634000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2280966892500. Starting simulation... +info: Entering event queue @ 2280028634000. Starting simulation... switching cpus -info: Entering event queue @ 2280967718000. Starting simulation... +info: Entering event queue @ 2280028792000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2281967718000. Starting simulation... +info: Entering event queue @ 2281028792000. Starting simulation... switching cpus -info: Entering event queue @ 2281967767000. Starting simulation... +info: Entering event queue @ 2281031728500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2282967767000. Starting simulation... +info: Entering event queue @ 2282031728500. Starting simulation... switching cpus -info: Entering event queue @ 2282971689500. Starting simulation... +info: Entering event queue @ 2282031872000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2283971689500. Starting simulation... +info: Entering event queue @ 2283031872000. Starting simulation... switching cpus -info: Entering event queue @ 2283971806000. Starting simulation... +info: Entering event queue @ 2283037827500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2284971806000. Starting simulation... +info: Entering event queue @ 2284037827500. Starting simulation... switching cpus -info: Entering event queue @ 2284971880000. Starting simulation... +info: Entering event queue @ 2284037973000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2285971880000. Starting simulation... +info: Entering event queue @ 2285037973000. Starting simulation... switching cpus -info: Entering event queue @ 2285971904500. Starting simulation... +info: Entering event queue @ 2285038127500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2286971904500. Starting simulation... +info: Entering event queue @ 2286038127500. Starting simulation... switching cpus -info: Entering event queue @ 2286972050000. Starting simulation... +info: Entering event queue @ 2286038281000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2287972050000. Starting simulation... +info: Entering event queue @ 2287038281000. Starting simulation... switching cpus -info: Entering event queue @ 2287972064000. Starting simulation... +info: Entering event queue @ 2287038326000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2288972064000. Starting simulation... +info: Entering event queue @ 2288038326000. Starting simulation... switching cpus -info: Entering event queue @ 2288972091500. Starting simulation... +info: Entering event queue @ 2288038395000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2289972091500. Starting simulation... +info: Entering event queue @ 2289038395000. Starting simulation... switching cpus -info: Entering event queue @ 2289980099000. Starting simulation... +info: Entering event queue @ 2289038454000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2290980099000. Starting simulation... +info: Entering event queue @ 2290038454000. Starting simulation... switching cpus -info: Entering event queue @ 2290980164000. Starting simulation... +info: Entering event queue @ 2290043867000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2291980164000. Starting simulation... +info: Entering event queue @ 2291043867000. Starting simulation... switching cpus -info: Entering event queue @ 2291980173000. Starting simulation... +info: Entering event queue @ 2291044009000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2292980173000. Starting simulation... +info: Entering event queue @ 2292044009000. Starting simulation... switching cpus -info: Entering event queue @ 2292980190000. Starting simulation... +info: Entering event queue @ 2292044100000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2293980190000. Starting simulation... +info: Entering event queue @ 2293044100000. Starting simulation... switching cpus -info: Entering event queue @ 2293980313000. Starting simulation... +info: Entering event queue @ 2293044163000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2294980313000. Starting simulation... +info: Entering event queue @ 2294044163000. Starting simulation... switching cpus -info: Entering event queue @ 2294980366000. Starting simulation... +info: Entering event queue @ 2294044227000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2295980366000. Starting simulation... +info: Entering event queue @ 2295044227000. Starting simulation... switching cpus -info: Entering event queue @ 2295980491500. Starting simulation... +info: Entering event queue @ 2295044273000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2296980491500. Starting simulation... +info: Entering event queue @ 2296044273000. Starting simulation... switching cpus -info: Entering event queue @ 2296980655000. Starting simulation... +info: Entering event queue @ 2296044353500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2297980655000. Starting simulation... -info: Entering event queue @ 2297980854500. Starting simulation... +info: Entering event queue @ 2297044353500. Starting simulation... switching cpus -info: Entering event queue @ 2297980855500. Starting simulation... +info: Entering event queue @ 2297044376000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2298980855500. Starting simulation... +info: Entering event queue @ 2298044376000. Starting simulation... switching cpus -info: Entering event queue @ 2298980896000. Starting simulation... +info: Entering event queue @ 2298044505000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2299980896000. Starting simulation... -info: Entering event queue @ 2299988769500. Starting simulation... -info: Entering event queue @ 2299988774500. Starting simulation... +info: Entering event queue @ 2299044505000. Starting simulation... switching cpus -info: Entering event queue @ 2299988779000. Starting simulation... +info: Entering event queue @ 2299044591000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2300988779000. Starting simulation... +info: Entering event queue @ 2300044591000. Starting simulation... +info: Entering event queue @ 2300054074500. Starting simulation... +info: Entering event queue @ 2300054079500. Starting simulation... switching cpus -info: Entering event queue @ 2300988932000. Starting simulation... +info: Entering event queue @ 2300054084000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2301988932000. Starting simulation... +info: Entering event queue @ 2301054084000. Starting simulation... switching cpus -info: Entering event queue @ 2301988991000. Starting simulation... +info: Entering event queue @ 2301054216000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2302988991000. Starting simulation... +info: Entering event queue @ 2302054216000. Starting simulation... switching cpus -info: Entering event queue @ 2302998893000. Starting simulation... +info: Entering event queue @ 2302054252000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2303998893000. Starting simulation... +info: Entering event queue @ 2303054252000. Starting simulation... switching cpus -info: Entering event queue @ 2303999033000. Starting simulation... +info: Entering event queue @ 2303064199000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2304999033000. Starting simulation... -info: Entering event queue @ 2306420845000. Starting simulation... +info: Entering event queue @ 2304064199000. Starting simulation... switching cpus -info: Entering event queue @ 2306420847000. Starting simulation... +info: Entering event queue @ 2304064238000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2307420847000. Starting simulation... +info: Entering event queue @ 2305064238000. Starting simulation... +info: Entering event queue @ 2306544922000. Starting simulation... switching cpus -info: Entering event queue @ 2307429463000. Starting simulation... +info: Entering event queue @ 2306544924000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2308429463000. Starting simulation... +info: Entering event queue @ 2307544924000. Starting simulation... switching cpus -info: Entering event queue @ 2308429518000. Starting simulation... +info: Entering event queue @ 2307554441000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2309429518000. Starting simulation... +info: Entering event queue @ 2308554441000. Starting simulation... switching cpus -info: Entering event queue @ 2309436929000. Starting simulation... +info: Entering event queue @ 2308554462000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2310436929000. Starting simulation... -info: Entering event queue @ 2310445490500. Starting simulation... -info: Entering event queue @ 2310445497000. Starting simulation... +info: Entering event queue @ 2309554462000. Starting simulation... switching cpus -info: Entering event queue @ 2310445501500. Starting simulation... +info: Entering event queue @ 2309561672000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2311445501500. Starting simulation... +info: Entering event queue @ 2310561672000. Starting simulation... +info: Entering event queue @ 2310570028500. Starting simulation... +info: Entering event queue @ 2310570035000. Starting simulation... switching cpus -info: Entering event queue @ 2311445524000. Starting simulation... +info: Entering event queue @ 2310570039500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2312445524000. Starting simulation... +info: Entering event queue @ 2311570039500. Starting simulation... switching cpus -info: Entering event queue @ 2312445649000. Starting simulation... +info: Entering event queue @ 2311570139000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2313445649000. Starting simulation... +info: Entering event queue @ 2312570139000. Starting simulation... switching cpus -info: Entering event queue @ 2313445802000. Starting simulation... +info: Entering event queue @ 2312570195000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2314445802000. Starting simulation... +info: Entering event queue @ 2313570195000. Starting simulation... switching cpus -info: Entering event queue @ 2314445861000. Starting simulation... +info: Entering event queue @ 2313570285000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2315445861000. Starting simulation... +info: Entering event queue @ 2314570285000. Starting simulation... switching cpus -info: Entering event queue @ 2315445973000. Starting simulation... +info: Entering event queue @ 2314570324500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2316445973000. Starting simulation... +info: Entering event queue @ 2315570324500. Starting simulation... switching cpus -info: Entering event queue @ 2316446034000. Starting simulation... +info: Entering event queue @ 2315570361000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2317446034000. Starting simulation... +info: Entering event queue @ 2316570361000. Starting simulation... switching cpus -info: Entering event queue @ 2317446194500. Starting simulation... +info: Entering event queue @ 2316570403500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2318446194500. Starting simulation... +info: Entering event queue @ 2317570403500. Starting simulation... switching cpus -info: Entering event queue @ 2318446348000. Starting simulation... +info: Entering event queue @ 2317570429000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2319446348000. Starting simulation... +info: Entering event queue @ 2318570429000. Starting simulation... switching cpus -info: Entering event queue @ 2319446393000. Starting simulation... +info: Entering event queue @ 2318570448000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2320446393000. Starting simulation... -info: Entering event queue @ 2320446744000. Starting simulation... +info: Entering event queue @ 2319570448000. Starting simulation... switching cpus -info: Entering event queue @ 2320446745000. Starting simulation... +info: Entering event queue @ 2319570560000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2321446745000. Starting simulation... +info: Entering event queue @ 2320570560000. Starting simulation... switching cpus -info: Entering event queue @ 2321446843000. Starting simulation... +info: Entering event queue @ 2320570567500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2322446843000. Starting simulation... +info: Entering event queue @ 2321570567500. Starting simulation... switching cpus -info: Entering event queue @ 2322446904000. Starting simulation... +info: Entering event queue @ 2321570700000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2323446904000. Starting simulation... +info: Entering event queue @ 2322570700000. Starting simulation... switching cpus -info: Entering event queue @ 2323456659000. Starting simulation... +info: Entering event queue @ 2322570838000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2324456659000. Starting simulation... +info: Entering event queue @ 2323570838000. Starting simulation... switching cpus -info: Entering event queue @ 2324456757000. Starting simulation... +info: Entering event queue @ 2323570953000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2325456757000. Starting simulation... +info: Entering event queue @ 2324570953000. Starting simulation... switching cpus -info: Entering event queue @ 2325456829500. Starting simulation... +info: Entering event queue @ 2324571046000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2326456829500. Starting simulation... +info: Entering event queue @ 2325571046000. Starting simulation... switching cpus -info: Entering event queue @ 2326458375000. Starting simulation... +info: Entering event queue @ 2325571075000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2327458375000. Starting simulation... +info: Entering event queue @ 2326571075000. Starting simulation... switching cpus -info: Entering event queue @ 2327458422000. Starting simulation... +info: Entering event queue @ 2326571130000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2328458422000. Starting simulation... +info: Entering event queue @ 2327571130000. Starting simulation... switching cpus -info: Entering event queue @ 2328458566500. Starting simulation... +info: Entering event queue @ 2327571202000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2329458566500. Starting simulation... +info: Entering event queue @ 2328571202000. Starting simulation... switching cpus -info: Entering event queue @ 2329458584500. Starting simulation... +info: Entering event queue @ 2328571330000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2330458584500. Starting simulation... +info: Entering event queue @ 2329571330000. Starting simulation... switching cpus -info: Entering event queue @ 2330458701000. Starting simulation... +info: Entering event queue @ 2329571413000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2331458701000. Starting simulation... +info: Entering event queue @ 2330571413000. Starting simulation... switching cpus -info: Entering event queue @ 2331458728000. Starting simulation... +info: Entering event queue @ 2330571445000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2332458728000. Starting simulation... +info: Entering event queue @ 2331571445000. Starting simulation... switching cpus -info: Entering event queue @ 2332458887000. Starting simulation... +info: Entering event queue @ 2331571479000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2333458887000. Starting simulation... +info: Entering event queue @ 2332571479000. Starting simulation... switching cpus -info: Entering event queue @ 2333458927000. Starting simulation... +info: Entering event queue @ 2332581124000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2334458927000. Starting simulation... +info: Entering event queue @ 2333581124000. Starting simulation... switching cpus -info: Entering event queue @ 2334458930500. Starting simulation... +info: Entering event queue @ 2333581247000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2335458930500. Starting simulation... +info: Entering event queue @ 2334581247000. Starting simulation... +info: Entering event queue @ 2334581254500. Starting simulation... switching cpus -info: Entering event queue @ 2335458946000. Starting simulation... +info: Entering event queue @ 2334581257000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2336458946000. Starting simulation... +info: Entering event queue @ 2335581257000. Starting simulation... switching cpus -info: Entering event queue @ 2336460942000. Starting simulation... +info: Entering event queue @ 2335581419000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2337460942000. Starting simulation... +info: Entering event queue @ 2336581419000. Starting simulation... switching cpus -info: Entering event queue @ 2337461094000. Starting simulation... +info: Entering event queue @ 2336590347000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2338461094000. Starting simulation... -info: Entering event queue @ 2339157445000. Starting simulation... +info: Entering event queue @ 2337590347000. Starting simulation... +info: Entering event queue @ 2339281522000. Starting simulation... switching cpus -info: Entering event queue @ 2339157447000. Starting simulation... +info: Entering event queue @ 2339281524000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2340157447000. Starting simulation... +info: Entering event queue @ 2340281524000. Starting simulation... switching cpus -info: Entering event queue @ 2340161367000. Starting simulation... +info: Entering event queue @ 2340281630500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2341161367000. Starting simulation... +info: Entering event queue @ 2341281630500. Starting simulation... switching cpus -info: Entering event queue @ 2341161393000. Starting simulation... +info: Entering event queue @ 2341281710000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2342161393000. Starting simulation... +info: Entering event queue @ 2342281710000. Starting simulation... switching cpus -info: Entering event queue @ 2342161440000. Starting simulation... +info: Entering event queue @ 2342281728000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2343161440000. Starting simulation... +info: Entering event queue @ 2343281728000. Starting simulation... switching cpus -info: Entering event queue @ 2343161538000. Starting simulation... +info: Entering event queue @ 2343281745500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2344161538000. Starting simulation... +info: Entering event queue @ 2344281745500. Starting simulation... switching cpus -info: Entering event queue @ 2344161625000. Starting simulation... +info: Entering event queue @ 2344281816000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2345161625000. Starting simulation... +info: Entering event queue @ 2345281816000. Starting simulation... switching cpus -info: Entering event queue @ 2345161713500. Starting simulation... +info: Entering event queue @ 2345281843000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2346161713500. Starting simulation... +info: Entering event queue @ 2346281843000. Starting simulation... switching cpus -info: Entering event queue @ 2346161788500. Starting simulation... +info: Entering event queue @ 2346281957000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2347161788500. Starting simulation... +info: Entering event queue @ 2347281957000. Starting simulation... switching cpus -info: Entering event queue @ 2347161936000. Starting simulation... +info: Entering event queue @ 2347282029000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2348161936000. Starting simulation... +info: Entering event queue @ 2348282029000. Starting simulation... switching cpus -info: Entering event queue @ 2348162002000. Starting simulation... +info: Entering event queue @ 2348282128000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2349162002000. Starting simulation... +info: Entering event queue @ 2349282128000. Starting simulation... switching cpus -info: Entering event queue @ 2349162065000. Starting simulation... +info: Entering event queue @ 2349282215000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2350162065000. Starting simulation... +info: Entering event queue @ 2350282215000. Starting simulation... switching cpus -info: Entering event queue @ 2350162134000. Starting simulation... +info: Entering event queue @ 2350282373000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2351162134000. Starting simulation... +info: Entering event queue @ 2351282373000. Starting simulation... switching cpus -info: Entering event queue @ 2351162263000. Starting simulation... +info: Entering event queue @ 2351282490000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2352162263000. Starting simulation... +info: Entering event queue @ 2352282490000. Starting simulation... switching cpus -info: Entering event queue @ 2352162285000. Starting simulation... +info: Entering event queue @ 2352282616000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2353162285000. Starting simulation... +info: Entering event queue @ 2353282616000. Starting simulation... switching cpus -info: Entering event queue @ 2353170607000. Starting simulation... +info: Entering event queue @ 2353282704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2354170607000. Starting simulation... +info: Entering event queue @ 2354282704000. Starting simulation... switching cpus -info: Entering event queue @ 2354170736000. Starting simulation... +info: Entering event queue @ 2354292637000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2355170736000. Starting simulation... +info: Entering event queue @ 2355292637000. Starting simulation... switching cpus -info: Entering event queue @ 2355170892500. Starting simulation... +info: Entering event queue @ 2355292752000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2356170892500. Starting simulation... +info: Entering event queue @ 2356292752000. Starting simulation... switching cpus -info: Entering event queue @ 2356172531000. Starting simulation... +info: Entering event queue @ 2356292829000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2357172531000. Starting simulation... +info: Entering event queue @ 2357292829000. Starting simulation... switching cpus -info: Entering event queue @ 2357172559000. Starting simulation... +info: Entering event queue @ 2357295010000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2358172559000. Starting simulation... +info: Entering event queue @ 2358295010000. Starting simulation... switching cpus -info: Entering event queue @ 2358172614000. Starting simulation... +info: Entering event queue @ 2358295060000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2359172614000. Starting simulation... +info: Entering event queue @ 2359295060000. Starting simulation... switching cpus -info: Entering event queue @ 2359172646000. Starting simulation... +info: Entering event queue @ 2359295117000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2360172646000. Starting simulation... +info: Entering event queue @ 2360295117000. Starting simulation... switching cpus -info: Entering event queue @ 2360172678000. Starting simulation... +info: Entering event queue @ 2360295201000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2361172678000. Starting simulation... +info: Entering event queue @ 2361295201000. Starting simulation... switching cpus -info: Entering event queue @ 2361172808000. Starting simulation... +info: Entering event queue @ 2361295232000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2362172808000. Starting simulation... +info: Entering event queue @ 2362295232000. Starting simulation... switching cpus -info: Entering event queue @ 2362172960000. Starting simulation... +info: Entering event queue @ 2362295364500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2363172960000. Starting simulation... +info: Entering event queue @ 2363295364500. Starting simulation... switching cpus -info: Entering event queue @ 2363178221000. Starting simulation... +info: Entering event queue @ 2363295520000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2364178221000. Starting simulation... +info: Entering event queue @ 2364295520000. Starting simulation... switching cpus -info: Entering event queue @ 2364178280000. Starting simulation... +info: Entering event queue @ 2364301747000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2365178280000. Starting simulation... +info: Entering event queue @ 2365301747000. Starting simulation... switching cpus -info: Entering event queue @ 2365178287500. Starting simulation... +info: Entering event queue @ 2365301807000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2366178287500. Starting simulation... +info: Entering event queue @ 2366301807000. Starting simulation... switching cpus -info: Entering event queue @ 2366178360000. Starting simulation... +info: Entering event queue @ 2366301912000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2367178360000. Starting simulation... +info: Entering event queue @ 2367301912000. Starting simulation... switching cpus -info: Entering event queue @ 2367178437000. Starting simulation... +info: Entering event queue @ 2367304066000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2368178437000. Starting simulation... +info: Entering event queue @ 2368304066000. Starting simulation... switching cpus -info: Entering event queue @ 2368178488000. Starting simulation... +info: Entering event queue @ 2368304184000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2369178488000. Starting simulation... +info: Entering event queue @ 2369304184000. Starting simulation... switching cpus -info: Entering event queue @ 2369178596000. Starting simulation... +info: Entering event queue @ 2369304297000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2370178596000. Starting simulation... +info: Entering event queue @ 2370304297000. Starting simulation... switching cpus -info: Entering event queue @ 2370178656000. Starting simulation... +info: Entering event queue @ 2370304370000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2371178656000. Starting simulation... -info: Entering event queue @ 2371894045000. Starting simulation... +info: Entering event queue @ 2371304370000. Starting simulation... +info: Entering event queue @ 2372016955000. Starting simulation... switching cpus -info: Entering event queue @ 2371894047000. Starting simulation... +info: Entering event queue @ 2372016957000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2372894047000. Starting simulation... +info: Entering event queue @ 2373016957000. Starting simulation... switching cpus -info: Entering event queue @ 2372894102500. Starting simulation... +info: Entering event queue @ 2373017069000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2373894102500. Starting simulation... +info: Entering event queue @ 2374017069000. Starting simulation... switching cpus -info: Entering event queue @ 2373894137500. Starting simulation... +info: Entering event queue @ 2374019359000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2374894137500. Starting simulation... +info: Entering event queue @ 2375019359000. Starting simulation... switching cpus -info: Entering event queue @ 2374894259000. Starting simulation... +info: Entering event queue @ 2375019391000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2375894259000. Starting simulation... +info: Entering event queue @ 2376019391000. Starting simulation... switching cpus -info: Entering event queue @ 2375894306000. Starting simulation... +info: Entering event queue @ 2376019468000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2376894306000. Starting simulation... +info: Entering event queue @ 2377019468000. Starting simulation... switching cpus -info: Entering event queue @ 2376900398000. Starting simulation... +info: Entering event queue @ 2377019493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2377900398000. Starting simulation... +info: Entering event queue @ 2378019493500. Starting simulation... switching cpus -info: Entering event queue @ 2377900421000. Starting simulation... +info: Entering event queue @ 2378019501000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2378900421000. Starting simulation... +info: Entering event queue @ 2379019501000. Starting simulation... switching cpus -info: Entering event queue @ 2378900488500. Starting simulation... +info: Entering event queue @ 2379019576000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2379900488500. Starting simulation... +info: Entering event queue @ 2380019576000. Starting simulation... switching cpus -info: Entering event queue @ 2379900521000. Starting simulation... +info: Entering event queue @ 2380019732000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2380900521000. Starting simulation... +info: Entering event queue @ 2381019732000. Starting simulation... switching cpus -info: Entering event queue @ 2380900624000. Starting simulation... +info: Entering event queue @ 2381028816000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2381900624000. Starting simulation... +info: Entering event queue @ 2382028816000. Starting simulation... switching cpus -info: Entering event queue @ 2381900718000. Starting simulation... +info: Entering event queue @ 2382028916000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2382900718000. Starting simulation... +info: Entering event queue @ 2383028916000. Starting simulation... switching cpus -info: Entering event queue @ 2382900790000. Starting simulation... +info: Entering event queue @ 2383028989000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2383900790000. Starting simulation... +info: Entering event queue @ 2384028989000. Starting simulation... switching cpus -info: Entering event queue @ 2383900839000. Starting simulation... +info: Entering event queue @ 2384029150000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2384900839000. Starting simulation... +info: Entering event queue @ 2385029150000. Starting simulation... switching cpus -info: Entering event queue @ 2384910381000. Starting simulation... +info: Entering event queue @ 2385029168000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2385910381000. Starting simulation... +info: Entering event queue @ 2386029168000. Starting simulation... switching cpus -info: Entering event queue @ 2385910485000. Starting simulation... +info: Entering event queue @ 2386029178000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2386910485000. Starting simulation... +info: Entering event queue @ 2387029178000. Starting simulation... switching cpus -info: Entering event queue @ 2386910628000. Starting simulation... +info: Entering event queue @ 2387029238000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2387910628000. Starting simulation... +info: Entering event queue @ 2388029238000. Starting simulation... switching cpus -info: Entering event queue @ 2387911152000. Starting simulation... +info: Entering event queue @ 2388029333000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2388911152000. Starting simulation... +info: Entering event queue @ 2389029333000. Starting simulation... switching cpus -info: Entering event queue @ 2388914114000. Starting simulation... +info: Entering event queue @ 2389029370000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2389914114000. Starting simulation... +info: Entering event queue @ 2390029370000. Starting simulation... switching cpus -info: Entering event queue @ 2389914243000. Starting simulation... +info: Entering event queue @ 2390029405000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2390914243000. Starting simulation... +info: Entering event queue @ 2391029405000. Starting simulation... switching cpus -info: Entering event queue @ 2390914368000. Starting simulation... +info: Entering event queue @ 2391029529500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2391914368000. Starting simulation... +info: Entering event queue @ 2392029529500. Starting simulation... switching cpus -info: Entering event queue @ 2391914402000. Starting simulation... +info: Entering event queue @ 2392029617500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2392914402000. Starting simulation... +info: Entering event queue @ 2393029617500. Starting simulation... switching cpus -info: Entering event queue @ 2392914536000. Starting simulation... +info: Entering event queue @ 2393029685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2393914536000. Starting simulation... +info: Entering event queue @ 2394029685500. Starting simulation... switching cpus -info: Entering event queue @ 2393914563000. Starting simulation... +info: Entering event queue @ 2394029788000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2394914563000. Starting simulation... +info: Entering event queue @ 2395029788000. Starting simulation... switching cpus -info: Entering event queue @ 2394914712000. Starting simulation... +info: Entering event queue @ 2395029853000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2395914712000. Starting simulation... +info: Entering event queue @ 2396029853000. Starting simulation... switching cpus -info: Entering event queue @ 2395914740000. Starting simulation... +info: Entering event queue @ 2396029864500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2396914740000. Starting simulation... +info: Entering event queue @ 2397029864500. Starting simulation... switching cpus -info: Entering event queue @ 2396914806500. Starting simulation... +info: Entering event queue @ 2397029943500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2397914806500. Starting simulation... +info: Entering event queue @ 2398029943500. Starting simulation... switching cpus -info: Entering event queue @ 2397914904000. Starting simulation... +info: Entering event queue @ 2398030031500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2398914904000. Starting simulation... +info: Entering event queue @ 2399030031500. Starting simulation... switching cpus -info: Entering event queue @ 2398914957000. Starting simulation... +info: Entering event queue @ 2399030085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2399914957000. Starting simulation... +info: Entering event queue @ 2400030085500. Starting simulation... switching cpus -info: Entering event queue @ 2399915059000. Starting simulation... +info: Entering event queue @ 2400030175000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2400915059000. Starting simulation... +info: Entering event queue @ 2401030175000. Starting simulation... switching cpus -info: Entering event queue @ 2400915130000. Starting simulation... +info: Entering event queue @ 2401030308000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2401915130000. Starting simulation... -info: Entering event queue @ 2401915136500. Starting simulation... +info: Entering event queue @ 2402030308000. Starting simulation... switching cpus -info: Entering event queue @ 2401915141000. Starting simulation... +info: Entering event queue @ 2402030463000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2402915141000. Starting simulation... +info: Entering event queue @ 2403030463000. Starting simulation... +info: Entering event queue @ 2403036923000. Starting simulation... +info: Entering event queue @ 2403036924000. Starting simulation... switching cpus -info: Entering event queue @ 2402915191000. Starting simulation... +info: Entering event queue @ 2403036928500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2403915191000. Starting simulation... -info: Entering event queue @ 2404629421000. Starting simulation... +info: Entering event queue @ 2404036928500. Starting simulation... +info: Entering event queue @ 2404753534000. Starting simulation... switching cpus -info: Entering event queue @ 2404629423000. Starting simulation... +info: Entering event queue @ 2404753536000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2405629423000. Starting simulation... +info: Entering event queue @ 2405753536000. Starting simulation... switching cpus -info: Entering event queue @ 2405629508000. Starting simulation... +info: Entering event queue @ 2405753688000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2406629508000. Starting simulation... +info: Entering event queue @ 2406753688000. Starting simulation... switching cpus -info: Entering event queue @ 2406632022000. Starting simulation... +info: Entering event queue @ 2406753797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2407632022000. Starting simulation... +info: Entering event queue @ 2407753797500. Starting simulation... switching cpus -info: Entering event queue @ 2407632051000. Starting simulation... +info: Entering event queue @ 2407753845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2408632051000. Starting simulation... +info: Entering event queue @ 2408753845500. Starting simulation... switching cpus -info: Entering event queue @ 2408632082000. Starting simulation... +info: Entering event queue @ 2408753915000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2409632082000. Starting simulation... +info: Entering event queue @ 2409753915000. Starting simulation... switching cpus -info: Entering event queue @ 2409632155000. Starting simulation... +info: Entering event queue @ 2409754052000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2410632155000. Starting simulation... +info: Entering event queue @ 2410754052000. Starting simulation... switching cpus -info: Entering event queue @ 2410632268000. Starting simulation... +info: Entering event queue @ 2410754121000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2411632268000. Starting simulation... +info: Entering event queue @ 2411754121000. Starting simulation... switching cpus -info: Entering event queue @ 2411632347000. Starting simulation... +info: Entering event queue @ 2411754241000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2412632347000. Starting simulation... +info: Entering event queue @ 2412754241000. Starting simulation... switching cpus -info: Entering event queue @ 2412632398000. Starting simulation... +info: Entering event queue @ 2412754335000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2413632398000. Starting simulation... +info: Entering event queue @ 2413754335000. Starting simulation... switching cpus -info: Entering event queue @ 2413632529000. Starting simulation... +info: Entering event queue @ 2413754496000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2414632529000. Starting simulation... +info: Entering event queue @ 2414754496000. Starting simulation... switching cpus -info: Entering event queue @ 2414632639500. Starting simulation... +info: Entering event queue @ 2414754503500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2415632639500. Starting simulation... +info: Entering event queue @ 2415754503500. Starting simulation... switching cpus -info: Entering event queue @ 2415632664000. Starting simulation... +info: Entering event queue @ 2415754548000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2416632664000. Starting simulation... +info: Entering event queue @ 2416754548000. Starting simulation... switching cpus -info: Entering event queue @ 2416632740000. Starting simulation... +info: Entering event queue @ 2416754666000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2417632740000. Starting simulation... +info: Entering event queue @ 2417754666000. Starting simulation... switching cpus -info: Entering event queue @ 2417632859000. Starting simulation... +info: Entering event queue @ 2417754746500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2418632859000. Starting simulation... +info: Entering event queue @ 2418754746500. Starting simulation... switching cpus -info: Entering event queue @ 2418633034000. Starting simulation... +info: Entering event queue @ 2418754759000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2419633034000. Starting simulation... +info: Entering event queue @ 2419754759000. Starting simulation... switching cpus -info: Entering event queue @ 2419633059000. Starting simulation... +info: Entering event queue @ 2419754791000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2420633059000. Starting simulation... +info: Entering event queue @ 2420754791000. Starting simulation... switching cpus -info: Entering event queue @ 2420633160000. Starting simulation... +info: Entering event queue @ 2420763573000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2421633160000. Starting simulation... +info: Entering event queue @ 2421763573000. Starting simulation... switching cpus -info: Entering event queue @ 2421633208000. Starting simulation... +info: Entering event queue @ 2421763627000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2422633208000. Starting simulation... +info: Entering event queue @ 2422763627000. Starting simulation... switching cpus -info: Entering event queue @ 2422633239000. Starting simulation... +info: Entering event queue @ 2422763683000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2423633239000. Starting simulation... +info: Entering event queue @ 2423763683000. Starting simulation... switching cpus -info: Entering event queue @ 2423633384000. Starting simulation... +info: Entering event queue @ 2423763816000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2424633384000. Starting simulation... +info: Entering event queue @ 2424763816000. Starting simulation... switching cpus -info: Entering event queue @ 2424633545000. Starting simulation... +info: Entering event queue @ 2424763896000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2425633545000. Starting simulation... +info: Entering event queue @ 2425763896000. Starting simulation... switching cpus -info: Entering event queue @ 2425633690000. Starting simulation... +info: Entering event queue @ 2425764024500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2426633690000. Starting simulation... +info: Entering event queue @ 2426764024500. Starting simulation... switching cpus -info: Entering event queue @ 2426641613000. Starting simulation... +info: Entering event queue @ 2426764049000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2427641613000. Starting simulation... +info: Entering event queue @ 2427764049000. Starting simulation... switching cpus -info: Entering event queue @ 2427641770000. Starting simulation... +info: Entering event queue @ 2427764185000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2428641770000. Starting simulation... +info: Entering event queue @ 2428764185000. Starting simulation... switching cpus -info: Entering event queue @ 2428641908500. Starting simulation... +info: Entering event queue @ 2428770274000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2429641908500. Starting simulation... +info: Entering event queue @ 2429770274000. Starting simulation... switching cpus -info: Entering event queue @ 2429641980500. Starting simulation... +info: Entering event queue @ 2429770406000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2430641980500. Starting simulation... +info: Entering event queue @ 2430770406000. Starting simulation... switching cpus -info: Entering event queue @ 2430642039000. Starting simulation... +info: Entering event queue @ 2430770512000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2431642039000. Starting simulation... +info: Entering event queue @ 2431770512000. Starting simulation... switching cpus -info: Entering event queue @ 2431645440000. Starting simulation... +info: Entering event queue @ 2431770631000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2432645440000. Starting simulation... +info: Entering event queue @ 2432770631000. Starting simulation... switching cpus -info: Entering event queue @ 2432645529000. Starting simulation... +info: Entering event queue @ 2432770756000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2433645529000. Starting simulation... +info: Entering event queue @ 2433770756000. Starting simulation... switching cpus -info: Entering event queue @ 2433645687500. Starting simulation... +info: Entering event queue @ 2433771542000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2434645687500. Starting simulation... +info: Entering event queue @ 2434771542000. Starting simulation... switching cpus -info: Entering event queue @ 2434645756000. Starting simulation... +info: Entering event queue @ 2434771640000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2435645756000. Starting simulation... +info: Entering event queue @ 2435771640000. Starting simulation... switching cpus -info: Entering event queue @ 2435645838500. Starting simulation... +info: Entering event queue @ 2435771648000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2436645838500. Starting simulation... -info: Entering event queue @ 2437366021000. Starting simulation... +info: Entering event queue @ 2436771648000. Starting simulation... +info: Entering event queue @ 2437490134000. Starting simulation... switching cpus -info: Entering event queue @ 2437366023000. Starting simulation... +info: Entering event queue @ 2437490136000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2438366023000. Starting simulation... +info: Entering event queue @ 2438490136000. Starting simulation... switching cpus -info: Entering event queue @ 2438371168000. Starting simulation... +info: Entering event queue @ 2438490158000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2439371168000. Starting simulation... +info: Entering event queue @ 2439490158000. Starting simulation... switching cpus -info: Entering event queue @ 2439371194000. Starting simulation... +info: Entering event queue @ 2439490217000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2440371194000. Starting simulation... +info: Entering event queue @ 2440490217000. Starting simulation... switching cpus -info: Entering event queue @ 2440371226000. Starting simulation... +info: Entering event queue @ 2440490335500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2441371226000. Starting simulation... +info: Entering event queue @ 2441490335500. Starting simulation... switching cpus -info: Entering event queue @ 2441371358000. Starting simulation... +info: Entering event queue @ 2441490449000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2442371358000. Starting simulation... +info: Entering event queue @ 2442490449000. Starting simulation... switching cpus -info: Entering event queue @ 2442371517000. Starting simulation... +info: Entering event queue @ 2442490551000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2443371517000. Starting simulation... +info: Entering event queue @ 2443490551000. Starting simulation... switching cpus -info: Entering event queue @ 2443380978000. Starting simulation... +info: Entering event queue @ 2443490670000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2444380978000. Starting simulation... +info: Entering event queue @ 2444490670000. Starting simulation... switching cpus -info: Entering event queue @ 2444381084000. Starting simulation... +info: Entering event queue @ 2444490744000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2445381084000. Starting simulation... +info: Entering event queue @ 2445490744000. Starting simulation... switching cpus -info: Entering event queue @ 2445381144000. Starting simulation... +info: Entering event queue @ 2445499008000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2446381144000. Starting simulation... +info: Entering event queue @ 2446499008000. Starting simulation... switching cpus -info: Entering event queue @ 2446383015000. Starting simulation... +info: Entering event queue @ 2446499143000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2447383015000. Starting simulation... +info: Entering event queue @ 2447499143000. Starting simulation... switching cpus -info: Entering event queue @ 2447383090000. Starting simulation... +info: Entering event queue @ 2447499251000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2448383090000. Starting simulation... +info: Entering event queue @ 2448499251000. Starting simulation... switching cpus -info: Entering event queue @ 2448383163000. Starting simulation... +info: Entering event queue @ 2448501472000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2449383163000. Starting simulation... +info: Entering event queue @ 2449501472000. Starting simulation... switching cpus -info: Entering event queue @ 2449383307000. Starting simulation... +info: Entering event queue @ 2449501552000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2450383307000. Starting simulation... +info: Entering event queue @ 2450501552000. Starting simulation... switching cpus -info: Entering event queue @ 2450383397000. Starting simulation... +info: Entering event queue @ 2450501708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2451383397000. Starting simulation... +info: Entering event queue @ 2451501708000. Starting simulation... switching cpus -info: Entering event queue @ 2451383538000. Starting simulation... +info: Entering event queue @ 2451501752500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2452383538000. Starting simulation... +info: Entering event queue @ 2452501752500. Starting simulation... switching cpus -info: Entering event queue @ 2452383697000. Starting simulation... +info: Entering event queue @ 2452501854000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2453383697000. Starting simulation... +info: Entering event queue @ 2453501854000. Starting simulation... switching cpus -info: Entering event queue @ 2453383787000. Starting simulation... +info: Entering event queue @ 2453501960000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2454383787000. Starting simulation... +info: Entering event queue @ 2454501960000. Starting simulation... switching cpus -info: Entering event queue @ 2454383902500. Starting simulation... +info: Entering event queue @ 2454502105000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2455383902500. Starting simulation... +info: Entering event queue @ 2455502105000. Starting simulation... switching cpus -info: Entering event queue @ 2455384008500. Starting simulation... +info: Entering event queue @ 2455502233000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2456384008500. Starting simulation... +info: Entering event queue @ 2456502233000. Starting simulation... switching cpus -info: Entering event queue @ 2456384150000. Starting simulation... +info: Entering event queue @ 2456502345000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2457384150000. Starting simulation... +info: Entering event queue @ 2457502345000. Starting simulation... switching cpus -info: Entering event queue @ 2457384245000. Starting simulation... +info: Entering event queue @ 2457502439000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2458384245000. Starting simulation... +info: Entering event queue @ 2458502439000. Starting simulation... switching cpus -info: Entering event queue @ 2458384323500. Starting simulation... +info: Entering event queue @ 2458502524000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2459384323500. Starting simulation... +info: Entering event queue @ 2459502524000. Starting simulation... switching cpus -info: Entering event queue @ 2459384411000. Starting simulation... +info: Entering event queue @ 2459502597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2460384411000. Starting simulation... +info: Entering event queue @ 2460502597500. Starting simulation... switching cpus -info: Entering event queue @ 2460393475000. Starting simulation... +info: Entering event queue @ 2460502627000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2461393475000. Starting simulation... +info: Entering event queue @ 2461502627000. Starting simulation... switching cpus -info: Entering event queue @ 2461393549000. Starting simulation... +info: Entering event queue @ 2461502675000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2462393549000. Starting simulation... +info: Entering event queue @ 2462502675000. Starting simulation... switching cpus -info: Entering event queue @ 2462393584000. Starting simulation... +info: Entering event queue @ 2462502774500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2463393584000. Starting simulation... +info: Entering event queue @ 2463502774500. Starting simulation... switching cpus -info: Entering event queue @ 2463393618000. Starting simulation... +info: Entering event queue @ 2463502818000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2464393618000. Starting simulation... +info: Entering event queue @ 2464502818000. Starting simulation... switching cpus -info: Entering event queue @ 2464393740000. Starting simulation... +info: Entering event queue @ 2464502945000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2465393740000. Starting simulation... +info: Entering event queue @ 2465502945000. Starting simulation... switching cpus -info: Entering event queue @ 2465393843000. Starting simulation... +info: Entering event queue @ 2465511849000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2466393843000. Starting simulation... +info: Entering event queue @ 2466511849000. Starting simulation... switching cpus -info: Entering event queue @ 2466393993000. Starting simulation... +info: Entering event queue @ 2466511856500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2467393993000. Starting simulation... +info: Entering event queue @ 2467511856500. Starting simulation... switching cpus -info: Entering event queue @ 2467394007000. Starting simulation... +info: Entering event queue @ 2467512001000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2468394007000. Starting simulation... +info: Entering event queue @ 2468512001000. Starting simulation... switching cpus -info: Entering event queue @ 2468394131000. Starting simulation... +info: Entering event queue @ 2468512063000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2469394131000. Starting simulation... -info: Entering event queue @ 2470103845000. Starting simulation... +info: Entering event queue @ 2469512063000. Starting simulation... +info: Entering event queue @ 2470225739000. Starting simulation... switching cpus -info: Entering event queue @ 2470103847000. Starting simulation... +info: Entering event queue @ 2470225741000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2471103847000. Starting simulation... +info: Entering event queue @ 2471225741000. Starting simulation... switching cpus -info: Entering event queue @ 2471103944000. Starting simulation... +info: Entering event queue @ 2471226221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2472103944000. Starting simulation... +info: Entering event queue @ 2472226221500. Starting simulation... switching cpus -info: Entering event queue @ 2472103960000. Starting simulation... +info: Entering event queue @ 2472226357000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2473103960000. Starting simulation... +info: Entering event queue @ 2473226357000. Starting simulation... switching cpus -info: Entering event queue @ 2473104036500. Starting simulation... +info: Entering event queue @ 2473226411000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2474104036500. Starting simulation... +info: Entering event queue @ 2474226411000. Starting simulation... switching cpus -info: Entering event queue @ 2474104223500. Starting simulation... +info: Entering event queue @ 2474226515000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2475104223500. Starting simulation... +info: Entering event queue @ 2475226515000. Starting simulation... switching cpus -info: Entering event queue @ 2475104380000. Starting simulation... +info: Entering event queue @ 2475226537000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2476104380000. Starting simulation... +info: Entering event queue @ 2476226537000. Starting simulation... switching cpus -info: Entering event queue @ 2476104409500. Starting simulation... +info: Entering event queue @ 2476226570000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2477104409500. Starting simulation... -info: Entering event queue @ 2477104413500. Starting simulation... -info: Entering event queue @ 2477104421500. Starting simulation... +info: Entering event queue @ 2477226570000. Starting simulation... switching cpus -info: Entering event queue @ 2477104426000. Starting simulation... +info: Entering event queue @ 2477230887000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2478104426000. Starting simulation... +info: Entering event queue @ 2478230887000. Starting simulation... +info: Entering event queue @ 2478231272000. Starting simulation... switching cpus -info: Entering event queue @ 2478104963000. Starting simulation... +info: Entering event queue @ 2478231279500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2479104963000. Starting simulation... +info: Entering event queue @ 2479231279500. Starting simulation... switching cpus -info: Entering event queue @ 2479105061000. Starting simulation... +info: Entering event queue @ 2479231321000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2480105061000. Starting simulation... +info: Entering event queue @ 2480231321000. Starting simulation... switching cpus -info: Entering event queue @ 2480105119000. Starting simulation... +info: Entering event queue @ 2480231467000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2481105119000. Starting simulation... +info: Entering event queue @ 2481231467000. Starting simulation... switching cpus -info: Entering event queue @ 2481105221000. Starting simulation... +info: Entering event queue @ 2481237971000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2482105221000. Starting simulation... +info: Entering event queue @ 2482237971000. Starting simulation... switching cpus -info: Entering event queue @ 2482105269000. Starting simulation... +info: Entering event queue @ 2482238135000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2483105269000. Starting simulation... +info: Entering event queue @ 2483238135000. Starting simulation... switching cpus -info: Entering event queue @ 2483105409000. Starting simulation... +info: Entering event queue @ 2483238269000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2484105409000. Starting simulation... +info: Entering event queue @ 2484238269000. Starting simulation... switching cpus -info: Entering event queue @ 2484105474000. Starting simulation... +info: Entering event queue @ 2484238311000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2485105474000. Starting simulation... +info: Entering event queue @ 2485238311000. Starting simulation... switching cpus -info: Entering event queue @ 2485105631000. Starting simulation... +info: Entering event queue @ 2485238411000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2486105631000. Starting simulation... +info: Entering event queue @ 2486238411000. Starting simulation... switching cpus -info: Entering event queue @ 2486105717000. Starting simulation... +info: Entering event queue @ 2486238487000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2487105717000. Starting simulation... +info: Entering event queue @ 2487238487000. Starting simulation... switching cpus -info: Entering event queue @ 2487105777000. Starting simulation... +info: Entering event queue @ 2487239689000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2488105777000. Starting simulation... -info: Entering event queue @ 2488109208500. Starting simulation... -info: Entering event queue @ 2488109213500. Starting simulation... +info: Entering event queue @ 2488239689000. Starting simulation... switching cpus -info: Entering event queue @ 2488109218000. Starting simulation... +info: Entering event queue @ 2488239724000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2489109218000. Starting simulation... +info: Entering event queue @ 2489239724000. Starting simulation... switching cpus -info: Entering event queue @ 2489113875500. Starting simulation... +info: Entering event queue @ 2489244495500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2490113875500. Starting simulation... +info: Entering event queue @ 2490244495500. Starting simulation... +info: Entering event queue @ 2490244503000. Starting simulation... switching cpus -info: Entering event queue @ 2490113878000. Starting simulation... +info: Entering event queue @ 2490244507500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2491113878000. Starting simulation... +info: Entering event queue @ 2491244507500. Starting simulation... switching cpus -info: Entering event queue @ 2491116979000. Starting simulation... +info: Entering event queue @ 2491244516000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2492116979000. Starting simulation... +info: Entering event queue @ 2492244516000. Starting simulation... switching cpus -info: Entering event queue @ 2492117002000. Starting simulation... +info: Entering event queue @ 2492244536000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2493117002000. Starting simulation... +info: Entering event queue @ 2493244536000. Starting simulation... switching cpus -info: Entering event queue @ 2493117162000. Starting simulation... +info: Entering event queue @ 2493251837000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2494117162000. Starting simulation... +info: Entering event queue @ 2494251837000. Starting simulation... switching cpus -info: Entering event queue @ 2494117254000. Starting simulation... +info: Entering event queue @ 2494251954000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2495117254000. Starting simulation... +info: Entering event queue @ 2495251954000. Starting simulation... switching cpus -info: Entering event queue @ 2495117340000. Starting simulation... +info: Entering event queue @ 2495252012000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2496117340000. Starting simulation... +info: Entering event queue @ 2496252012000. Starting simulation... switching cpus -info: Entering event queue @ 2496126635000. Starting simulation... +info: Entering event queue @ 2496255849000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2497126635000. Starting simulation... +info: Entering event queue @ 2497255849000. Starting simulation... switching cpus -info: Entering event queue @ 2497126690000. Starting simulation... +info: Entering event queue @ 2497255860000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2498126690000. Starting simulation... +info: Entering event queue @ 2498255860000. Starting simulation... switching cpus -info: Entering event queue @ 2498126787000. Starting simulation... +info: Entering event queue @ 2498256024000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2499126787000. Starting simulation... +info: Entering event queue @ 2499256024000. Starting simulation... switching cpus -info: Entering event queue @ 2499126938000. Starting simulation... +info: Entering event queue @ 2499256176000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2500126938000. Starting simulation... +info: Entering event queue @ 2500256176000. Starting simulation... switching cpus -info: Entering event queue @ 2500126982000. Starting simulation... +info: Entering event queue @ 2500256276000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2501126982000. Starting simulation... +info: Entering event queue @ 2501256276000. Starting simulation... +info: Entering event queue @ 2502962318000. Starting simulation... switching cpus -info: Entering event queue @ 2501127036000. Starting simulation... +info: Entering event queue @ 2502962320000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2502127036000. Starting simulation... -info: Entering event queue @ 2502839680000. Starting simulation... +info: Entering event queue @ 2503962320000. Starting simulation... switching cpus -info: Entering event queue @ 2502839682000. Starting simulation... +info: Entering event queue @ 2503962362000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2503839682000. Starting simulation... +info: Entering event queue @ 2504962362000. Starting simulation... switching cpus -info: Entering event queue @ 2503839688500. Starting simulation... +info: Entering event queue @ 2504962512000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2504839688500. Starting simulation... +info: Entering event queue @ 2505962512000. Starting simulation... +info: Entering event queue @ 2505962525000. Starting simulation... +info: Entering event queue @ 2505962534000. Starting simulation... +info: Entering event queue @ 2505962538500. Starting simulation... switching cpus -info: Entering event queue @ 2504839737000. Starting simulation... +info: Entering event queue @ 2505962539500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2505839737000. Starting simulation... +info: Entering event queue @ 2506962539500. Starting simulation... switching cpus -info: Entering event queue @ 2505839779500. Starting simulation... +info: Entering event queue @ 2506962568500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2506839779500. Starting simulation... +info: Entering event queue @ 2507962568500. Starting simulation... switching cpus -info: Entering event queue @ 2506839943000. Starting simulation... +info: Entering event queue @ 2507970193000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2507839943000. Starting simulation... +info: Entering event queue @ 2508970193000. Starting simulation... switching cpus -info: Entering event queue @ 2507840084000. Starting simulation... +info: Entering event queue @ 2508970326000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2508840084000. Starting simulation... +info: Entering event queue @ 2509970326000. Starting simulation... switching cpus -info: Entering event queue @ 2508844290000. Starting simulation... +info: Entering event queue @ 2509970419000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2509844290000. Starting simulation... +info: Entering event queue @ 2510970419000. Starting simulation... switching cpus -info: Entering event queue @ 2509844368000. Starting simulation... +info: Entering event queue @ 2510970429000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2510844368000. Starting simulation... +info: Entering event queue @ 2511970429000. Starting simulation... switching cpus -info: Entering event queue @ 2510844455000. Starting simulation... +info: Entering event queue @ 2511974054000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2511844455000. Starting simulation... +info: Entering event queue @ 2512974054000. Starting simulation... switching cpus -info: Entering event queue @ 2511844611000. Starting simulation... +info: Entering event queue @ 2512974121500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2512844611000. Starting simulation... +info: Entering event queue @ 2513974121500. Starting simulation... switching cpus -info: Entering event queue @ 2512844690000. Starting simulation... +info: Entering event queue @ 2513974129000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2513844690000. Starting simulation... +info: Entering event queue @ 2514974129000. Starting simulation... switching cpus -info: Entering event queue @ 2513853962000. Starting simulation... +info: Entering event queue @ 2514975356000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2514853962000. Starting simulation... +info: Entering event queue @ 2515975356000. Starting simulation... switching cpus -info: Entering event queue @ 2514854068000. Starting simulation... +info: Entering event queue @ 2515975454000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2515854068000. Starting simulation... +info: Entering event queue @ 2516975454000. Starting simulation... switching cpus -info: Entering event queue @ 2515854102000. Starting simulation... +info: Entering event queue @ 2516975552000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2516854102000. Starting simulation... +info: Entering event queue @ 2517975552000. Starting simulation... switching cpus -info: Entering event queue @ 2516855790000. Starting simulation... +info: Entering event queue @ 2517982622000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2517855790000. Starting simulation... +info: Entering event queue @ 2518982622000. Starting simulation... switching cpus -info: Entering event queue @ 2517855884500. Starting simulation... +info: Entering event queue @ 2518982687000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2518855884500. Starting simulation... -info: Entering event queue @ 2518859439500. Starting simulation... -info: Entering event queue @ 2518859449000. Starting simulation... -info: Entering event queue @ 2518859453500. Starting simulation... +info: Entering event queue @ 2519982687000. Starting simulation... switching cpus -info: Entering event queue @ 2518859454500. Starting simulation... +info: Entering event queue @ 2519982786000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2519859454500. Starting simulation... +info: Entering event queue @ 2520982786000. Starting simulation... +info: Entering event queue @ 2520988988500. Starting simulation... +info: Entering event queue @ 2520988994500. Starting simulation... switching cpus -info: Entering event queue @ 2519859612000. Starting simulation... +info: Entering event queue @ 2520988999000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2520859612000. Starting simulation... +info: Entering event queue @ 2521988999000. Starting simulation... switching cpus -info: Entering event queue @ 2520859743000. Starting simulation... +info: Entering event queue @ 2521989071000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2521859743000. Starting simulation... +info: Entering event queue @ 2522989071000. Starting simulation... switching cpus -info: Entering event queue @ 2521859796000. Starting simulation... +info: Entering event queue @ 2522989085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2522859796000. Starting simulation... +info: Entering event queue @ 2523989085500. Starting simulation... switching cpus -info: Entering event queue @ 2522859820000. Starting simulation... +info: Entering event queue @ 2523989143000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2523859820000. Starting simulation... +info: Entering event queue @ 2524989143000. Starting simulation... switching cpus -info: Entering event queue @ 2523859876000. Starting simulation... +info: Entering event queue @ 2524989219000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2524859876000. Starting simulation... +info: Entering event queue @ 2525989219000. Starting simulation... switching cpus -info: Entering event queue @ 2524859972500. Starting simulation... +info: Entering event queue @ 2525998131000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2525859972500. Starting simulation... +info: Entering event queue @ 2526998131000. Starting simulation... switching cpus -info: Entering event queue @ 2525859990000. Starting simulation... +info: Entering event queue @ 2527002132000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2526859990000. Starting simulation... +info: Entering event queue @ 2528002132000. Starting simulation... switching cpus -info: Entering event queue @ 2526860000500. Starting simulation... +info: Entering event queue @ 2528002139500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2527860000500. Starting simulation... +info: Entering event queue @ 2529002139500. Starting simulation... switching cpus -info: Entering event queue @ 2527860004000. Starting simulation... +info: Entering event queue @ 2529002278000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2528860004000. Starting simulation... +info: Entering event queue @ 2530002278000. Starting simulation... +info: Entering event queue @ 2530002328000. Starting simulation... switching cpus -info: Entering event queue @ 2528860008500. Starting simulation... +info: Entering event queue @ 2530002335500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2529860008500. Starting simulation... +info: Entering event queue @ 2531002335500. Starting simulation... switching cpus -info: Entering event queue @ 2529860052000. Starting simulation... +info: Entering event queue @ 2531002354000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2530860052000. Starting simulation... +info: Entering event queue @ 2532002354000. Starting simulation... switching cpus -info: Entering event queue @ 2530860057000. Starting simulation... +info: Entering event queue @ 2532006673000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2531860057000. Starting simulation... +info: Entering event queue @ 2533006673000. Starting simulation... switching cpus -info: Entering event queue @ 2531860059000. Starting simulation... +info: Entering event queue @ 2533015860500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2532860059000. Starting simulation... +info: Entering event queue @ 2534015860500. Starting simulation... +info: Entering event queue @ 2535698918000. Starting simulation... switching cpus -info: Entering event queue @ 2532860067500. Starting simulation... +info: Entering event queue @ 2535698920000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2533860067500. Starting simulation... +info: Entering event queue @ 2536698920000. Starting simulation... switching cpus -info: Entering event queue @ 2533860795000. Starting simulation... +info: Entering event queue @ 2536698927500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2534860795000. Starting simulation... -info: Entering event queue @ 2535576589000. Starting simulation... +info: Entering event queue @ 2537698927500. Starting simulation... switching cpus -info: Entering event queue @ 2535576591000. Starting simulation... +info: Entering event queue @ 2537698997000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2536576591000. Starting simulation... +info: Entering event queue @ 2538698997000. Starting simulation... +info: Entering event queue @ 2538699007500. Starting simulation... +info: Entering event queue @ 2538699018000. Starting simulation... switching cpus -info: Entering event queue @ 2536576653000. Starting simulation... +info: Entering event queue @ 2538699018500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2537576653000. Starting simulation... +info: Entering event queue @ 2539699018500. Starting simulation... +info: Entering event queue @ 2539704793500. Starting simulation... +info: Entering event queue @ 2539704800000. Starting simulation... switching cpus -info: Entering event queue @ 2537576734500. Starting simulation... +info: Entering event queue @ 2539704804500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2538576734500. Starting simulation... -info: Entering event queue @ 2538576753000. Starting simulation... +info: Entering event queue @ 2540704804500. Starting simulation... switching cpus -info: Entering event queue @ 2538576817500. Starting simulation... +info: Entering event queue @ 2540704925000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2539576817500. Starting simulation... -info: Entering event queue @ 2539576829500. Starting simulation... +info: Entering event queue @ 2541704925000. Starting simulation... +info: Entering event queue @ 2541705319000. Starting simulation... switching cpus -info: Entering event queue @ 2539576834000. Starting simulation... +info: Entering event queue @ 2541705326500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2542705326500. Starting simulation... +switching cpus +info: Entering event queue @ 2542705334000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 56b72ce02..da9e176fe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,163 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541275 # Number of seconds simulated -sim_ticks 2541275479000 # Number of ticks simulated -final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.543226 # Number of seconds simulated +sim_ticks 2543226083000 # Number of ticks simulated +final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58368 # Simulator instruction rate (inst/s) -host_op_rate 75104 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2459458086 # Simulator tick rate (ticks/s) -host_mem_usage 437960 # Number of bytes of host memory used -host_seconds 1033.27 # Real time elapsed on the host -sim_insts 60310144 # Number of instructions simulated -sim_ops 77602537 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 24298 # Simulator instruction rate (inst/s) +host_op_rate 31265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1024641665 # Simulator tick rate (ticks/s) +host_mem_usage 442376 # Number of bytes of host memory used +host_seconds 2482.06 # Real time elapsed on the host +sim_insts 60309820 # Number of instructions simulated +sim_ops 77602107 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 511168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4147472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 290304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4947228 # Number of bytes read from this memory +system.physmem.bytes_read::total 131010156 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 290304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 801472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3787712 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory +system.physmem.bytes_written::total 6803824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64838 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77307 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293538 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59183 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813211 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47620826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 116704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 200992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1630792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1945257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51513374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 200992 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529307 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47620826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2163937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 116704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293480 # Total number of read requests seen -system.physmem.writeReqs 813178 # Total number of write requests seen -system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782720 # Total number of bytes read from memory -system.physmem.bytesWritten 52043392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 200992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2160099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2601889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54188647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293538 # Total number of read requests seen +system.physmem.writeReqs 813211 # Total number of write requests seen +system.physmem.cpureqs 218552 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978786432 # Total number of bytes read from memory +system.physmem.bytesWritten 52045504 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131010156 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6803824 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955443 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955607 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955922 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50728 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 956157 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50189 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50732 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51231 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541274319500 # Total gap between requests +system.physmem.numWrRetry 32473 # Number of times wr buffer was full causing retry +system.physmem.totGap 2543224928500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154621 # Categorize read packet sizes +system.physmem.readPktSize::6 154679 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59150 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2723048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2699101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59183 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3605153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 59924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -168,282 +156,290 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2942 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2931 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35313 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32599 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see -system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467350000 # Total cycles spent in databus access -system.physmem.totBankLat 16704696250 # Total cycles spent in bank access -system.physmem.avgQLat 22669.51 # Average queueing delay per request -system.physmem.avgBankLat 1092.28 # Average bank access latency per request +system.physmem.wrQLenPdf::30 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32479 # What write queue length does an incoming req see +system.physmem.totQLat 346835420750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440002912000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467635000 # Total cycles spent in databus access +system.physmem.totBankLat 16699856250 # Total cycles spent in bank access +system.physmem.avgQLat 22678.58 # Average queueing delay per request +system.physmem.avgBankLat 1091.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28761.78 # Average memory access latency -system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28770.53 # Average memory access latency +system.physmem.avgRdBW 384.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.12 # Average write queue length over time -system.physmem.readRowHits 15218335 # Number of row buffer hits during reads -system.physmem.writeRowHits 794661 # Number of row buffer hits during writes +system.physmem.readRowHits 15218407 # Number of row buffer hits during reads +system.physmem.writeRowHits 794595 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157777.88 # Average gap between requests -system.l2c.replacements 64389 # number of replacements -system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use -system.l2c.total_refs 1903765 # Total number of references to valid blocks. -system.l2c.sampled_refs 129779 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.669284 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor +system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes +system.physmem.avgGap 157898.09 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64447 # number of replacements +system.l2c.tagsinuse 51415.469971 # Cycle average of tags in use +system.l2c.total_refs 1904213 # Total number of references to valid blocks. +system.l2c.sampled_refs 129841 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.665730 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2506268100000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36946.421058 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 20.318328 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5127.291089 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3277.380324 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 9.553076 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3076.231813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2944.101992 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563726 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000275 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5214.605130 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3261.076745 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 16.327658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2998.760808 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2957.959894 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563758 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000310 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078236 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000146 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046940 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044923 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784255 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 491964 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 214249 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30395 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 478610 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 173362 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434820 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608422 # number of Writeback hits -system.l2c.Writeback_hits::total 608422 # number of Writeback hits +system.l2c.occ_percent::cpu0.inst 0.079569 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.049760 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.045757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.045135 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784538 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7442 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 494450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 217567 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 29984 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6613 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 477029 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169593 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435728 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607829 # number of Writeback hits +system.l2c.Writeback_hits::total 607829 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57870 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55015 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112885 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491964 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 272119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30395 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 478610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 228377 # number of demand (read+write) hits -system.l2c.demand_hits::total 1547705 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32015 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7355 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491964 # number of overall hits -system.l2c.overall_hits::cpu0.data 272119 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30395 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6870 # number of overall hits -system.l2c.overall_hits::cpu1.inst 478610 # number of overall hits -system.l2c.overall_hits::cpu1.data 228377 # number of overall hits -system.l2c.overall_hits::total 1547705 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57675 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112832 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33050 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7442 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 494450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 275242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 29984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6613 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 477029 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 224750 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548560 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 33050 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7442 # number of overall hits +system.l2c.overall_hits::cpu0.inst 494450 # number of overall hits +system.l2c.overall_hits::cpu0.data 275242 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 29984 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6613 # number of overall hits +system.l2c.overall_hits::cpu1.inst 477029 # number of overall hits +system.l2c.overall_hits::cpu1.data 224750 # number of overall hits +system.l2c.overall_hits::total 1548560 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 33 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7751 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6089 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4640 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4614 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23136 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59818 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73396 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133214 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7877 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6086 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4540 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4624 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23181 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1632 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1283 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 59765 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73463 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133228 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 33 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 65907 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4640 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 78010 # number of demand (read+write) misses -system.l2c.demand_misses::total 156350 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7877 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 65851 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4540 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78087 # number of demand (read+write) misses +system.l2c.demand_misses::total 156409 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 33 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7751 # number of overall misses -system.l2c.overall_misses::cpu0.data 65907 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4640 # number of overall misses -system.l2c.overall_misses::cpu1.data 78010 # number of overall misses -system.l2c.overall_misses::total 156350 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1945000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7877 # number of overall misses +system.l2c.overall_misses::cpu0.data 65851 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4540 # number of overall misses +system.l2c.overall_misses::cpu1.data 78087 # number of overall misses +system.l2c.overall_misses::total 156409 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2765500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 430985000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 344391500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 737500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 265908000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 270917500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1315002500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 204500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 227500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 432000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3114638500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3663340000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6777978500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1945000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 434812500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 348876500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1306000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 265734500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 270200000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1323813000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 205500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 182500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 388000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3099799500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3655844500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6755644000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2765500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 430985000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3459030000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 737500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 265908000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3934257500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8092981000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1945000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 434812500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3448676000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1306000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 265734500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3926044500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8079457000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2765500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 430985000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3459030000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 737500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 265908000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3934257500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8092981000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32044 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 499715 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 220338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30406 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6870 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 483250 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 177976 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1457956 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608422 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608422 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1555 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 434812500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3448676000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1306000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 265734500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3926044500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8079457000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 33083 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7444 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 502327 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 223653 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30003 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 481569 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 174217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458909 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 607829 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 607829 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1650 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1294 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117688 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246099 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 499715 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 338026 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30406 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 483250 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 306387 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704055 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 499715 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 338026 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30406 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 483250 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 306387 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704055 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015869 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988424 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990607 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989452 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.090909 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.508276 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.571571 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541302 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.194976 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.254613 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015511 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.194976 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.254613 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 117440 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 128620 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246060 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 33083 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7444 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 502327 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341093 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30003 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 481569 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 302837 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704969 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 33083 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7444 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 502327 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341093 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30003 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 481569 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 302837 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704969 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000269 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027212 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009428 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026542 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015889 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989091 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991499 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.990149 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.508898 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.571163 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541445 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000269 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015681 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.193059 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009428 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.257852 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091737 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000269 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015681 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.193059 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009428 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.257852 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091737 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55603.793059 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56559.615700 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57307.758621 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58716.406589 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 56837.936549 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.051399 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 165.937272 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 148.555708 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52068.583035 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49911.984304 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50880.376687 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55200.266599 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57324.433125 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58531.828194 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58434.256055 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 57107.674389 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 125.919118 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 142.244739 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 133.104631 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 51866.468669 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49764.432435 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50707.388837 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51761.950752 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51655.959695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51761.950752 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51655.959695 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,166 +448,158 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59150 # number of writebacks -system.l2c.writebacks::total 59150 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 59183 # number of writebacks +system.l2c.writebacks::total 59183 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 33 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7741 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6051 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4634 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4593 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23061 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 59818 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73396 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133214 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7868 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4536 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4605 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23107 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1632 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1283 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 59765 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73463 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133228 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 33 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7741 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 65869 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4634 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 77989 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156275 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7868 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 65809 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4536 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 78068 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156335 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 33 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7741 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 65869 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4634 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 77989 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156275 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7868 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 65809 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4536 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 78068 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156335 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334226230 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267591443 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 598510 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 207854839 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212784313 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1024731614 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15371537 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13786326 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29157863 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2368364997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2749328891 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5117693888 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336517819 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 271517668 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 209058491 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 211521322 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1032131602 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 16321632 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12832782 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29154414 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354223480 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2740919006 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5095142486 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 334226230 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2635956440 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 598510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 207854839 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2962113204 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6142425502 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 336517819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2625741148 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 209058491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2952440328 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6127274088 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 334226230 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2635956440 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 598510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 207854839 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2962113204 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6142425502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 336517819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2625741148 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 209058491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2952440328 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6127274088 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84119678267 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82847227004 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166971957601 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10487963006 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13201284574 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23689247580 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83994636767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82967803004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166967492101 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10493457778 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13230278140 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23723735918 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94607641273 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96048511578 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190661205181 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027462 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025807 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015817 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990607 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989452 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508276 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571571 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541302 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091708 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091708 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94488094545 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96198081144 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190691228019 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027024 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026433 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015839 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989091 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991499 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.990149 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508898 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571163 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541445 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44222.681044 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46327.958415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44435.697238 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44923.505625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45932.968947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44667.486130 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10055.671772 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.775447 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39592.848256 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37458.838234 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38417.087453 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.168355 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.514237 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39391.340751 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37310.197052 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38243.781232 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,680 +622,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7621777 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits +system.cpu0.branchPred.lookups 7719049 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6144205 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 388400 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 5016002 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4082948 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.398452 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 737953 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39729 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26065013 # DTB read hits -system.cpu0.dtb.read_misses 39990 # DTB read misses -system.cpu0.dtb.write_hits 5895229 # DTB write hits -system.cpu0.dtb.write_misses 9395 # DTB write misses +system.cpu0.dtb.read_hits 26145640 # DTB read hits +system.cpu0.dtb.read_misses 41213 # DTB read misses +system.cpu0.dtb.write_hits 5906110 # DTB write hits +system.cpu0.dtb.write_misses 9202 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5753 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1471 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26105003 # DTB read accesses -system.cpu0.dtb.write_accesses 5904624 # DTB write accesses +system.cpu0.dtb.perms_faults 691 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26186853 # DTB read accesses +system.cpu0.dtb.write_accesses 5915312 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31960242 # DTB hits -system.cpu0.dtb.misses 49385 # DTB misses -system.cpu0.dtb.accesses 32009627 # DTB accesses -system.cpu0.itb.inst_hits 6121620 # ITB inst hits -system.cpu0.itb.inst_misses 7590 # ITB inst misses +system.cpu0.dtb.hits 32051750 # DTB hits +system.cpu0.dtb.misses 50415 # DTB misses +system.cpu0.dtb.accesses 32102165 # DTB accesses +system.cpu0.itb.inst_hits 6183534 # ITB inst hits +system.cpu0.itb.inst_misses 7751 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2745 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses -system.cpu0.itb.hits 6121620 # DTB hits -system.cpu0.itb.misses 7590 # DTB misses -system.cpu0.itb.accesses 6129210 # DTB accesses -system.cpu0.numCycles 238950356 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6191285 # ITB inst accesses +system.cpu0.itb.hits 6183534 # DTB hits +system.cpu0.itb.misses 7751 # DTB misses +system.cpu0.itb.accesses 6191285 # DTB accesses +system.cpu0.numCycles 239079415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15644570 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 48338125 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7719049 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4820901 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10703205 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2596540 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 94746 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49591987 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1964 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 53331 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101492 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6181495 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 400642 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3259 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77992242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.765373 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.123716 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67296980 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 702662 0.90% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 892389 1.14% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1243235 1.59% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1139067 1.46% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 581520 0.75% 92.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1338462 1.72% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 402047 0.52% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4395880 5.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77992242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.032287 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.202184 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16701716 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49328258 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9693840 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 556609 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1709696 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1049154 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91765 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56812427 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 306906 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1709696 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17642458 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18978880 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27077809 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9239108 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3342271 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53967560 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13437 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 629408 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2165949 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 513 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56184131 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 245540949 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 245492809 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48140 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40778039 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15406092 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 434005 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 385260 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6805574 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10494917 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6795022 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1080492 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1313371 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50078322 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1031134 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63522685 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 99823 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10628436 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26923896 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 250828 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77992242 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.814474 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519995 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55011307 70.53% 70.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7277871 9.33% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3728534 4.78% 84.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3132981 4.02% 88.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6315907 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1400012 1.80% 98.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 822343 1.05% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 235239 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 68048 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77992242 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 33040 0.74% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4225834 94.61% 95.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207543 4.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 193689 0.30% 0.30% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30176884 47.51% 47.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47977 0.08% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1219 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26869653 42.30% 90.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6233244 9.81% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued -system.cpu0.iq.rate 0.264557 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63522685 # Type of FU issued +system.cpu0.iq.rate 0.265697 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4466420 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070312 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 209641938 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61746831 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44505201 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12130 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6615 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5501 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67789033 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6383 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 329345 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2321629 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3668 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16120 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 899548 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17127140 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367757 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1709696 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14213295 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 236264 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51235944 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105063 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10494917 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6795022 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 726682 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58301 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3691 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16120 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 190260 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 151203 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 341463 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62339008 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26506413 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1183677 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117042 # number of nop insts executed -system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6029174 # Number of branches executed -system.cpu0.iew.exec_stores 6166956 # Number of stores executed -system.cpu0.iew.exec_rate 0.259636 # Inst execution rate -system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24341972 # num instructions producing a value -system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value +system.cpu0.iew.exec_nop 126488 # number of nop insts executed +system.cpu0.iew.exec_refs 32682490 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6088882 # Number of branches executed +system.cpu0.iew.exec_stores 6176077 # Number of stores executed +system.cpu0.iew.exec_rate 0.260746 # Inst execution rate +system.cpu0.iew.wb_sent 61801058 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44510702 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24520944 # num instructions producing a value +system.cpu0.iew.wb_consumers 44899908 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.186175 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546125 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10516243 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 780306 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 297973 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76282546 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.527732 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.509463 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61930092 81.19% 81.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6958991 9.12% 90.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2075873 2.72% 93.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1156776 1.52% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1044437 1.37% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 552027 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702446 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 372143 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1489761 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75954937 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31329293 # Number of instructions committed -system.cpu0.commit.committedOps 39986762 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76282546 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31604949 # Number of instructions committed +system.cpu0.commit.committedOps 40256713 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13987462 # Number of memory references committed -system.cpu0.commit.loads 8094208 # Number of loads committed -system.cpu0.commit.membars 212609 # Number of memory barriers committed -system.cpu0.commit.branches 5213704 # Number of branches committed -system.cpu0.commit.fp_insts 5481 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35328328 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514863 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1484760 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14068762 # Number of memory references committed +system.cpu0.commit.loads 8173288 # Number of loads committed +system.cpu0.commit.membars 214624 # Number of memory barriers committed +system.cpu0.commit.branches 5267155 # Number of branches committed +system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35547917 # Number of committed integer instructions. +system.cpu0.commit.function_calls 518151 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1489761 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123824951 # The number of ROB reads -system.cpu0.rob.rob_writes 102387078 # The number of ROB writes -system.cpu0.timesIdled 884056 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161311393 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289794473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31249850 # Number of Instructions Simulated -system.cpu0.committedOps 39907319 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31249850 # Number of Instructions Simulated -system.cpu0.cpi 7.646448 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.646448 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130780 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130780 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280856495 # number of integer regfile reads -system.cpu0.int_regfile_writes 45466199 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22714 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19802 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15537514 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430329 # number of misc regfile writes -system.cpu0.icache.replacements 983581 # number of replacements -system.cpu0.icache.tagsinuse 511.609112 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036717 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984093 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.215116 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.975852 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 154.633260 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.697218 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302018 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999237 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5578101 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5458616 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036717 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5578101 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5458616 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036717 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5578101 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5458616 # number of overall hits -system.cpu0.icache.overall_hits::total 11036717 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 541391 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 523221 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064612 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 541391 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 523221 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064612 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 541391 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 523221 # number of overall misses -system.cpu0.icache.overall_misses::total 1064612 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7337521992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6947086995 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14284608987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7337521992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6947086995 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14284608987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7337521992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6947086995 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14284608987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6119492 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981837 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12101329 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6119492 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5981837 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12101329 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6119492 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5981837 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12101329 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088470 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087468 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087975 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088470 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087468 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087975 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088470 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087468 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087975 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13553.091928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13277.538545 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13417.666706 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13417.666706 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13417.666706 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4893 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.100865 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 124585414 # The number of ROB reads +system.cpu0.rob.rob_writes 103297804 # The number of ROB writes +system.cpu0.timesIdled 884994 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161087173 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289793652 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31519096 # Number of Instructions Simulated +system.cpu0.committedOps 40170860 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31519096 # Number of Instructions Simulated +system.cpu0.cpi 7.585224 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.585224 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.131835 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.131835 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 282333154 # number of integer regfile reads +system.cpu0.int_regfile_writes 45811922 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22666 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19880 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15681131 # number of misc regfile reads +system.cpu0.misc_regfile_writes 434463 # number of misc regfile writes +system.cpu0.icache.replacements 984470 # number of replacements +system.cpu0.icache.tagsinuse 511.608417 # Cycle average of tags in use +system.cpu0.icache.total_refs 11039436 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984982 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.207754 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 358.593548 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.014869 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.700378 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.298857 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5636954 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5402482 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11039436 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5636954 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5402482 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11039436 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5636954 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5402482 # number of overall hits +system.cpu0.icache.overall_hits::total 11039436 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 544416 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 521534 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065950 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 544416 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 521534 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065950 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 544416 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 521534 # number of overall misses +system.cpu0.icache.overall_misses::total 1065950 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7382097491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6930257996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14312355487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7382097491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6930257996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14312355487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7382097491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6930257996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14312355487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6181370 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5924016 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12105386 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6181370 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5924016 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12105386 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6181370 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5924016 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12105386 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088074 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088037 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088056 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088074 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088037 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088056 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088074 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088037 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088056 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.662999 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.218977 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13426.854437 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13426.854437 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13426.854437 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 847 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.611399 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 847 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41083 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39415 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80498 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41083 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39415 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80498 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41083 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39415 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80498 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 500308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 483806 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984114 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 500308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 483806 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984114 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 500308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 483806 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984114 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5984214993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5663833496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648048489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5984214993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5663833496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11648048489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5984214993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5663833496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11648048489 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41493 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39456 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80949 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41493 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39456 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80949 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41493 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39456 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80949 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 502923 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 482078 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 985001 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 502923 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 482078 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 985001 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 502923 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 482078 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 985001 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6018484991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5644614996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11663099987 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6018484991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5644614996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11663099987 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6018484991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5644614996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11663099987 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081323 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081323 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081323 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11836.076399 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081369 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081369 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081369 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11840.698626 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643901 # number of replacements -system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533518 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644413 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.415710 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 643418 # number of replacements +system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21533730 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 643930 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.441104 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.189291 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.803424 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.621463 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.378522 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 319.254285 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 192.738436 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.623544 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.376442 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7127084 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6650362 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3774490 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3487348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261838 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125952 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117576 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243528 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127946 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119673 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10901574 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10137710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039284 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10901574 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10137710 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039284 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 437179 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 313532 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750711 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1386171 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1574804 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2960975 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6802 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6759 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7222864 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6555051 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777915 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3783291 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3477957 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261248 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126614 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117265 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243879 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128750 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 118867 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247617 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11006155 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10033008 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039163 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11006155 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10033008 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039163 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 443968 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 305583 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 749551 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1380597 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1580939 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961536 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6950 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6643 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13593 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1823350 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1888336 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711686 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1823350 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1888336 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711686 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6487702500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4845715000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11333417500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52314948357 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62070901782 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114385850139 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91825500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94465000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186290500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1824565 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1886522 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711087 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1824565 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1886522 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711087 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6592316000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4802887000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11395203000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52073406352 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62127905305 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114201311657 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94083500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 92681000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186764500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58802650857 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66916616782 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125719267639 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58802650857 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66916616782 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125719267639 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7564263 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6963894 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14528157 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160661 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062152 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222813 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132754 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124335 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257089 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119678 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12724924 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12026046 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750970 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12724924 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12026046 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750970 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057795 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045023 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051673 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268603 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.311094 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289644 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051238 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052748 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 58665722352 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66930792305 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125596514657 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 58665722352 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66930792305 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125596514657 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666832 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6860634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527466 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5163888 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5058896 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222784 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 133564 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123908 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128753 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 118872 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247625 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12830720 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11919530 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750250 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12830720 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11919530 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750250 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057908 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.044542 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.267356 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.312507 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289700 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052035 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053612 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052794 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000023 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143290 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.157021 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149961 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143290 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.157021 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149961 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14839.922549 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15455.248587 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15096.911461 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37740.616675 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39415.001347 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38631.143505 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13499.779477 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13976.179908 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13737.224393 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.142203 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.158272 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149941 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.142203 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.158272 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149941 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.628730 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15717.127589 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15202.705353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37718.035279 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39298.104041 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38561.513909 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13537.194245 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13951.678459 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13739.755757 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14090.909091 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33871.202370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33871.202370 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36391 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 16051 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3543 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 264 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.271239 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 60.799242 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33843.592095 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33843.592095 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 34838 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14844 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3534 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 260 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.857951 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 57.092308 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608422 # number of writebacks -system.cpu0.dcache.writebacks::total 608422 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 222914 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 141593 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 364507 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1266986 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1445051 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712037 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 671 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 680 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489900 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1586644 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076544 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489900 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1586644 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076544 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214265 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171939 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386204 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119185 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129753 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6131 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6079 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12210 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 607829 # number of writebacks +system.cpu0.dcache.writebacks::total 607829 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226509 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 137269 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363778 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1261567 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1451066 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712633 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 699 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1488076 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1588335 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076411 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1488076 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1588335 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076411 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217459 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 168314 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385773 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119030 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129873 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248903 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6254 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5944 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12198 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 333450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 301692 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 333450 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 301692 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2906449500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2315533500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5221983000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3953585991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4507381433 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460967424 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71518000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74200000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145718000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 336489 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 298187 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634676 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 336489 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 298187 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634676 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2948842500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2284266500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5233109000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3938983490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4499310442 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8438293932 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73127000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72549000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145676000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6860035491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6822914933 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13682950424 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6860035491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6822914933 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13682950424 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91872733500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90487640000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182360373500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14914514407 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18644008670 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33558523077 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6887825990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6783576942 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13671402932 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6887825990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6783576942 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13671402932 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91735466000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90620432500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182355898500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14921149436 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671847220 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592996656 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106787247907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109131648670 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215918896577 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024690 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023095 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025632 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048892 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047493 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106656615436 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109292279720 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948895156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024533 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026555 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023050 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025672 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024348 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046824 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047971 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047376 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000023 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025661 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025661 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13564.742258 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13467.180221 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.307392 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33171.842019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34738.167387 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33988.251790 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.981243 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.954927 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11934.316134 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13560.452775 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13571.458702 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13565.254696 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33092.358985 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34643.924773 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33901.937429 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.836585 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.417227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11942.613543 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,324 +1310,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7016100 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits +system.cpu1.branchPred.lookups 6924581 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5562771 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 336228 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4476731 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3769892 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.210823 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 665809 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34604 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25297638 # DTB read hits -system.cpu1.dtb.read_misses 36209 # DTB read misses -system.cpu1.dtb.write_hits 5817747 # DTB write hits -system.cpu1.dtb.write_misses 9250 # DTB write misses +system.cpu1.dtb.read_hits 25217799 # DTB read hits +system.cpu1.dtb.read_misses 35648 # DTB read misses +system.cpu1.dtb.write_hits 5810779 # DTB write hits +system.cpu1.dtb.write_misses 9529 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5398 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1388 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25333847 # DTB read accesses -system.cpu1.dtb.write_accesses 5826997 # DTB write accesses +system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25253447 # DTB read accesses +system.cpu1.dtb.write_accesses 5820308 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31115385 # DTB hits -system.cpu1.dtb.misses 45459 # DTB misses -system.cpu1.dtb.accesses 31160844 # DTB accesses -system.cpu1.itb.inst_hits 5983825 # ITB inst hits -system.cpu1.itb.inst_misses 6876 # ITB inst misses +system.cpu1.dtb.hits 31028578 # DTB hits +system.cpu1.dtb.misses 45177 # DTB misses +system.cpu1.dtb.accesses 31073755 # DTB accesses +system.cpu1.itb.inst_hits 5925943 # ITB inst hits +system.cpu1.itb.inst_misses 6573 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2476 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1382 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses -system.cpu1.itb.hits 5983825 # DTB hits -system.cpu1.itb.misses 6876 # DTB misses -system.cpu1.itb.accesses 5990701 # DTB accesses -system.cpu1.numCycles 234271094 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5932516 # ITB inst accesses +system.cpu1.itb.hits 5925943 # DTB hits +system.cpu1.itb.misses 6573 # DTB misses +system.cpu1.itb.accesses 5932516 # DTB accesses +system.cpu1.numCycles 234244847 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15045426 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46051404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6924581 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4435701 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10180178 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2576164 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79323 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47488838 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 962 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 40665 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94257 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 230 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5924019 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 441347 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74691954 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.768024 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.131487 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64519001 86.38% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 606919 0.81% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 824654 1.10% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1190723 1.59% 89.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1057088 1.42% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 528345 0.71% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1354186 1.81% 93.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 346670 0.46% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4264368 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74691954 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029561 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.196595 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16048040 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47278235 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9237318 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 448383 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1677844 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 921418 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 84751 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54328734 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 282420 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1677844 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16980429 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18581446 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25685933 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8674589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3089642 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51185611 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7172 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 483859 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2112197 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 97 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53156547 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 235159359 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 235117285 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42074 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37614805 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15541741 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 399062 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 353498 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6213195 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9696990 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6683769 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 865241 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1058674 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47161259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 954916 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60450494 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 77232 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10409443 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27466585 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252722 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74691954 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.809331 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520957 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53120438 71.12% 71.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6581682 8.81% 79.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3495899 4.68% 84.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2849080 3.81% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6224305 8.33% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1417719 1.90% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 735156 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 208377 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59298 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74691954 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 25658 0.59% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4148051 94.78% 95.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 202723 4.63% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 169977 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28184247 46.62% 46.90% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45636 0.08% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 892 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25945360 42.92% 89.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6104366 10.10% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued -system.cpu1.iq.rate 0.259266 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60450494 # Type of FU issued +system.cpu1.iq.rate 0.258065 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4376432 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072397 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200080953 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58533998 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41393677 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10638 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5781 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4780 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64651317 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5632 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 296486 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2215043 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3144 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14677 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 846684 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16976661 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457892 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1677844 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14002380 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 233104 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48212114 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96608 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9696990 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6683769 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 685390 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50588 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3685 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14677 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 163070 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 129112 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 292182 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59083319 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25544592 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1367175 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105670 # number of nop insts executed -system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5509079 # Number of branches executed -system.cpu1.iew.exec_stores 6058244 # Number of stores executed -system.cpu1.iew.exec_rate 0.253403 # Inst execution rate -system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22722145 # num instructions producing a value -system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value +system.cpu1.iew.exec_nop 95939 # number of nop insts executed +system.cpu1.iew.exec_refs 31597721 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5452623 # Number of branches executed +system.cpu1.iew.exec_stores 6053129 # Number of stores executed +system.cpu1.iew.exec_rate 0.252229 # Inst execution rate +system.cpu1.iew.wb_sent 58512296 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41398457 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22553116 # num instructions producing a value +system.cpu1.iew.wb_consumers 41520902 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.176732 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543175 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10281991 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 702194 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 252752 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73014110 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513541 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.493879 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59627220 81.67% 81.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6596697 9.03% 90.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1882997 2.58% 93.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 995941 1.36% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 953813 1.31% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 518436 0.71% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 701051 0.96% 97.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372117 0.51% 98.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1365838 1.87% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29131232 # Number of instructions committed -system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73014110 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 28855252 # Number of instructions committed +system.cpu1.commit.committedOps 37495775 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13400454 # Number of memory references committed -system.cpu1.commit.loads 7561112 # Number of loads committed -system.cpu1.commit.membars 191037 # Number of memory barriers committed -system.cpu1.commit.branches 4747981 # Number of branches committed -system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions. -system.cpu1.commit.function_calls 476457 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13319032 # Number of memory references committed +system.cpu1.commit.loads 7481947 # Number of loads committed +system.cpu1.commit.membars 189014 # Number of memory barriers committed +system.cpu1.commit.branches 4694468 # Number of branches committed +system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33309565 # Number of committed integer instructions. +system.cpu1.commit.function_calls 473164 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1365838 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119155388 # The number of ROB reads -system.cpu1.rob.rob_writes 98129561 # The number of ROB writes -system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29060294 # Number of Instructions Simulated -system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated -system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads -system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes +system.cpu1.rob.rob_reads 118557028 # The number of ROB reads +system.cpu1.rob.rob_writes 97285221 # The number of ROB writes +system.cpu1.timesIdled 872406 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159552893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285658129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 28790724 # Number of Instructions Simulated +system.cpu1.committedOps 37431247 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 28790724 # Number of Instructions Simulated +system.cpu1.cpi 8.136122 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.136122 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.122909 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.122909 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 267548470 # number of integer regfile reads +system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14600078 # number of misc regfile reads +system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,10 +1642,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192831582801 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192831582801 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 3515a4f01..8baae834f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -13,7 +13,7 @@ atags_addr=256 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 @@ -330,6 +330,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -355,25 +356,28 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -503,7 +507,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -782,6 +786,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 98bbe4187..c5c33b0cf 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -30,11 +31,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 6412bc7eb..bcd78ce1e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:22:22 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:56:16 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second @@ -15,10751 +15,10751 @@ Switching CPUs... Next CPU: TimingSimpleCPU info: Entering event queue @ 1000000000. Starting simulation... switching cpus -info: Entering event queue @ 1000161000. Starting simulation... +info: Entering event queue @ 1000020000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2000161000. Starting simulation... +info: Entering event queue @ 2000020000. Starting simulation... switching cpus -info: Entering event queue @ 2000162000. Starting simulation... +info: Entering event queue @ 2000027500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 3000162000. Starting simulation... +info: Entering event queue @ 3000027500. Starting simulation... switching cpus -info: Entering event queue @ 3000209500. Starting simulation... +info: Entering event queue @ 3000051500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 4000209500. Starting simulation... +info: Entering event queue @ 4000051500. Starting simulation... switching cpus -info: Entering event queue @ 4000253500. Starting simulation... +info: Entering event queue @ 4000072500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 5000253500. Starting simulation... +info: Entering event queue @ 5000072500. Starting simulation... switching cpus -info: Entering event queue @ 5000254500. Starting simulation... +info: Entering event queue @ 5000073000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 6000254500. Starting simulation... +info: Entering event queue @ 6000073000. Starting simulation... switching cpus -info: Entering event queue @ 6000255500. Starting simulation... +info: Entering event queue @ 6000074000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 7000255500. Starting simulation... +info: Entering event queue @ 7000074000. Starting simulation... switching cpus -info: Entering event queue @ 7000257500. Starting simulation... +info: Entering event queue @ 7000075000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 8000257500. Starting simulation... +info: Entering event queue @ 8000075000. Starting simulation... switching cpus -info: Entering event queue @ 8000258500. Starting simulation... +info: Entering event queue @ 8000075500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 9000258500. Starting simulation... +info: Entering event queue @ 9000075500. Starting simulation... switching cpus -info: Entering event queue @ 9000473000. Starting simulation... +info: Entering event queue @ 9000211000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 10000473000. Starting simulation... +info: Entering event queue @ 10000211000. Starting simulation... switching cpus -info: Entering event queue @ 10000475000. Starting simulation... +info: Entering event queue @ 10000212000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 11000475000. Starting simulation... +info: Entering event queue @ 11000212000. Starting simulation... switching cpus -info: Entering event queue @ 11000476000. Starting simulation... +info: Entering event queue @ 11000212500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 12000476000. Starting simulation... +info: Entering event queue @ 12000212500. Starting simulation... switching cpus -info: Entering event queue @ 12000477500. Starting simulation... +info: Entering event queue @ 12000213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 13000477500. Starting simulation... +info: Entering event queue @ 13000213500. Starting simulation... switching cpus -info: Entering event queue @ 13000479500. Starting simulation... +info: Entering event queue @ 13000214500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 14000479500. Starting simulation... +info: Entering event queue @ 14000214500. Starting simulation... +info: Entering event queue @ 14000227000. Starting simulation... switching cpus -info: Entering event queue @ 14000481500. Starting simulation... +info: Entering event queue @ 14000228500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 15000481500. Starting simulation... +info: Entering event queue @ 15000228500. Starting simulation... switching cpus -info: Entering event queue @ 15000483500. Starting simulation... +info: Entering event queue @ 15000236000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 16000483500. Starting simulation... +info: Entering event queue @ 16000236000. Starting simulation... +info: Entering event queue @ 16000253000. Starting simulation... switching cpus -info: Entering event queue @ 16000485500. Starting simulation... +info: Entering event queue @ 16000256500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 17000485500. Starting simulation... +info: Entering event queue @ 17000256500. Starting simulation... switching cpus -info: Entering event queue @ 17000486500. Starting simulation... +info: Entering event queue @ 17000257000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 18000486500. Starting simulation... -info: Entering event queue @ 18000493500. Starting simulation... +info: Entering event queue @ 18000257000. Starting simulation... switching cpus -info: Entering event queue @ 18000496000. Starting simulation... +info: Entering event queue @ 18000264500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 19000496000. Starting simulation... +info: Entering event queue @ 19000264500. Starting simulation... +info: Entering event queue @ 19000274500. Starting simulation... switching cpus -info: Entering event queue @ 19000497000. Starting simulation... +info: Entering event queue @ 19000277000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 20000497000. Starting simulation... +info: Entering event queue @ 20000277000. Starting simulation... switching cpus -info: Entering event queue @ 20000498000. Starting simulation... +info: Entering event queue @ 20000284500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 21000498000. Starting simulation... -info: Entering event queue @ 21000511500. Starting simulation... +info: Entering event queue @ 21000284500. Starting simulation... switching cpus -info: Entering event queue @ 21000513000. Starting simulation... +info: Entering event queue @ 21000285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 22000513000. Starting simulation... -info: Entering event queue @ 22000516500. Starting simulation... +info: Entering event queue @ 22000285500. Starting simulation... switching cpus -info: Entering event queue @ 22000518000. Starting simulation... +info: Entering event queue @ 22000293000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 23000518000. Starting simulation... +info: Entering event queue @ 23000293000. Starting simulation... +info: Entering event queue @ 23000303000. Starting simulation... switching cpus -info: Entering event queue @ 23000519000. Starting simulation... +info: Entering event queue @ 23000304500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 24000519000. Starting simulation... +info: Entering event queue @ 24000304500. Starting simulation... switching cpus -info: Entering event queue @ 24000634000. Starting simulation... +info: Entering event queue @ 24000312000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 25000634000. Starting simulation... -info: Entering event queue @ 25000647000. Starting simulation... +info: Entering event queue @ 25000312000. Starting simulation... switching cpus -info: Entering event queue @ 25000650500. Starting simulation... +info: Entering event queue @ 25000319500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 26000650500. Starting simulation... -info: Entering event queue @ 26000657000. Starting simulation... +info: Entering event queue @ 26000319500. Starting simulation... switching cpus -info: Entering event queue @ 26000658500. Starting simulation... +info: Entering event queue @ 26000327000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 27000658500. Starting simulation... -info: Entering event queue @ 27000664500. Starting simulation... +info: Entering event queue @ 27000327000. Starting simulation... switching cpus -info: Entering event queue @ 27000667000. Starting simulation... +info: Entering event queue @ 27000334500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 28000667000. Starting simulation... +info: Entering event queue @ 28000334500. Starting simulation... switching cpus -info: Entering event queue @ 28000668000. Starting simulation... +info: Entering event queue @ 28000342000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 29000668000. Starting simulation... +info: Entering event queue @ 29000342000. Starting simulation... +info: Entering event queue @ 29000349500. Starting simulation... switching cpus -info: Entering event queue @ 29000669000. Starting simulation... +info: Entering event queue @ 29000351500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 30000669000. Starting simulation... +info: Entering event queue @ 30000351500. Starting simulation... switching cpus -info: Entering event queue @ 30000671000. Starting simulation... +info: Entering event queue @ 30000359000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 31000671000. Starting simulation... -info: Entering event queue @ 31000679500. Starting simulation... +info: Entering event queue @ 31000359000. Starting simulation... switching cpus -info: Entering event queue @ 31000682000. Starting simulation... +info: Entering event queue @ 31000366500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 32000682000. Starting simulation... +info: Entering event queue @ 32000366500. Starting simulation... switching cpus -info: Entering event queue @ 32000683000. Starting simulation... +info: Entering event queue @ 32000374000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 33000683000. Starting simulation... +info: Entering event queue @ 33000374000. Starting simulation... switching cpus -info: Entering event queue @ 33000684000. Starting simulation... +info: Entering event queue @ 33000406500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 34000684000. Starting simulation... +info: Entering event queue @ 34000406500. Starting simulation... switching cpus -info: Entering event queue @ 34000685000. Starting simulation... +info: Entering event queue @ 34000414000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 35000685000. Starting simulation... -info: Entering event queue @ 35000871500. Starting simulation... +info: Entering event queue @ 35000414000. Starting simulation... +info: Entering event queue @ 35000437500. Starting simulation... switching cpus -info: Entering event queue @ 35000872500. Starting simulation... +info: Entering event queue @ 35000654750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 36000872500. Starting simulation... +info: Entering event queue @ 36000654750. Starting simulation... switching cpus -info: Entering event queue @ 36000875000. Starting simulation... +info: Entering event queue @ 36000663500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 37000875000. Starting simulation... +info: Entering event queue @ 37000663500. Starting simulation... switching cpus -info: Entering event queue @ 37001097000. Starting simulation... +info: Entering event queue @ 37000671000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 38001097000. Starting simulation... +info: Entering event queue @ 38000671000. Starting simulation... switching cpus -info: Entering event queue @ 38001098000. Starting simulation... +info: Entering event queue @ 38000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 39001098000. Starting simulation... +info: Entering event queue @ 39000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 40001098000. Starting simulation... +info: Entering event queue @ 40000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 41001098000. Starting simulation... +info: Entering event queue @ 41000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 42001098000. Starting simulation... +info: Entering event queue @ 42000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 43001098000. Starting simulation... +info: Entering event queue @ 43000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 44001098000. Starting simulation... +info: Entering event queue @ 44000678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 45001098000. Starting simulation... +info: Entering event queue @ 45000678500. Starting simulation... switching cpus -info: Entering event queue @ 45001099000. Starting simulation... +info: Entering event queue @ 45000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 46001099000. Starting simulation... +info: Entering event queue @ 46000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 47001099000. Starting simulation... +info: Entering event queue @ 47000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 48001099000. Starting simulation... +info: Entering event queue @ 48000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 49001099000. Starting simulation... +info: Entering event queue @ 49000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 50001099000. Starting simulation... +info: Entering event queue @ 50000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 51001099000. Starting simulation... +info: Entering event queue @ 51000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 52001099000. Starting simulation... +info: Entering event queue @ 52000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 53001099000. Starting simulation... +info: Entering event queue @ 53000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 54001099000. Starting simulation... +info: Entering event queue @ 54000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 55001099000. Starting simulation... +info: Entering event queue @ 55000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 56001099000. Starting simulation... +info: Entering event queue @ 56000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 57001099000. Starting simulation... +info: Entering event queue @ 57000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 58001099000. Starting simulation... +info: Entering event queue @ 58000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 59001099000. Starting simulation... +info: Entering event queue @ 59000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 60001099000. Starting simulation... +info: Entering event queue @ 60000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 61001099000. Starting simulation... +info: Entering event queue @ 61000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 62001099000. Starting simulation... +info: Entering event queue @ 62000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 63001099000. Starting simulation... +info: Entering event queue @ 63000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 64001099000. Starting simulation... +info: Entering event queue @ 64000686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 65001099000. Starting simulation... -info: Entering event queue @ 66306421000. Starting simulation... +info: Entering event queue @ 65000686000. Starting simulation... +info: Entering event queue @ 66499718000. Starting simulation... switching cpus -info: Entering event queue @ 66306423000. Starting simulation... +info: Entering event queue @ 66499720000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 67306423000. Starting simulation... +info: Entering event queue @ 67499720000. Starting simulation... switching cpus -info: Entering event queue @ 67306432500. Starting simulation... +info: Entering event queue @ 67499727500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 68306432500. Starting simulation... +info: Entering event queue @ 68499727500. Starting simulation... switching cpus -info: Entering event queue @ 68306442500. Starting simulation... +info: Entering event queue @ 68499737500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 69306442500. Starting simulation... +info: Entering event queue @ 69499737500. Starting simulation... switching cpus -info: Entering event queue @ 69306452500. Starting simulation... +info: Entering event queue @ 69499745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 70306452500. Starting simulation... +info: Entering event queue @ 70499745000. Starting simulation... switching cpus -info: Entering event queue @ 70306453500. Starting simulation... +info: Entering event queue @ 70499751500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 71306453500. Starting simulation... +info: Entering event queue @ 71499751500. Starting simulation... +info: Entering event queue @ 71499768500. Starting simulation... switching cpus -info: Entering event queue @ 71306514500. Starting simulation... +info: Entering event queue @ 71499859000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 72306514500. Starting simulation... +info: Entering event queue @ 72499859000. Starting simulation... +info: Entering event queue @ 72499881500. Starting simulation... switching cpus -info: Entering event queue @ 72306516500. Starting simulation... +info: Entering event queue @ 72499991500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 73306516500. Starting simulation... +info: Entering event queue @ 73499991500. Starting simulation... switching cpus -info: Entering event queue @ 73306518500. Starting simulation... +info: Entering event queue @ 73500001500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 74306518500. Starting simulation... +info: Entering event queue @ 74500001500. Starting simulation... +info: Entering event queue @ 74500025500. Starting simulation... switching cpus -info: Entering event queue @ 74306519500. Starting simulation... +info: Entering event queue @ 74500109000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 75306519500. Starting simulation... +info: Entering event queue @ 75500109000. Starting simulation... switching cpus -info: Entering event queue @ 75306520500. Starting simulation... +info: Entering event queue @ 75500119500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 76306520500. Starting simulation... -info: Entering event queue @ 76306542500. Starting simulation... +info: Entering event queue @ 76500119500. Starting simulation... switching cpus -info: Entering event queue @ 76306583500. Starting simulation... +info: Entering event queue @ 76500120500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 77306583500. Starting simulation... +info: Entering event queue @ 77500120500. Starting simulation... switching cpus -info: Entering event queue @ 77306585500. Starting simulation... +info: Entering event queue @ 77500128000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 78306585500. Starting simulation... +info: Entering event queue @ 78500128000. Starting simulation... switching cpus -info: Entering event queue @ 78306586500. Starting simulation... +info: Entering event queue @ 78500135500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 79306586500. Starting simulation... +info: Entering event queue @ 79500135500. Starting simulation... switching cpus -info: Entering event queue @ 79306587500. Starting simulation... +info: Entering event queue @ 79500143000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 80306587500. Starting simulation... +info: Entering event queue @ 80500143000. Starting simulation... switching cpus -info: Entering event queue @ 80306589500. Starting simulation... +info: Entering event queue @ 80500143500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 81306589500. Starting simulation... -info: Entering event queue @ 81306614500. Starting simulation... +info: Entering event queue @ 81500143500. Starting simulation... switching cpus -info: Entering event queue @ 81306676500. Starting simulation... +info: Entering event queue @ 81500151000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 82306676500. Starting simulation... -info: Entering event queue @ 82306698500. Starting simulation... +info: Entering event queue @ 82500151000. Starting simulation... switching cpus -info: Entering event queue @ 82306739500. Starting simulation... +info: Entering event queue @ 82500158500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 83306739500. Starting simulation... +info: Entering event queue @ 83500158500. Starting simulation... switching cpus -info: Entering event queue @ 83306740500. Starting simulation... +info: Entering event queue @ 83500166000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 84306740500. Starting simulation... +info: Entering event queue @ 84500166000. Starting simulation... switching cpus -info: Entering event queue @ 84306741500. Starting simulation... +info: Entering event queue @ 84500180500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 85306741500. Starting simulation... +info: Entering event queue @ 85500180500. Starting simulation... switching cpus -info: Entering event queue @ 85306742500. Starting simulation... +info: Entering event queue @ 85500229000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 86306742500. Starting simulation... +info: Entering event queue @ 86500229000. Starting simulation... switching cpus -info: Entering event queue @ 86306743500. Starting simulation... +info: Entering event queue @ 86500236500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 87306743500. Starting simulation... -info: Entering event queue @ 87306763500. Starting simulation... +info: Entering event queue @ 87500236500. Starting simulation... switching cpus -info: Entering event queue @ 87306822500. Starting simulation... +info: Entering event queue @ 87500244000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 88306822500. Starting simulation... +info: Entering event queue @ 88500244000. Starting simulation... switching cpus -info: Entering event queue @ 88306823500. Starting simulation... +info: Entering event queue @ 88500251500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 89306823500. Starting simulation... +info: Entering event queue @ 89500251500. Starting simulation... switching cpus -info: Entering event queue @ 89306824500. Starting simulation... +info: Entering event queue @ 89500259000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 90306824500. Starting simulation... -info: Entering event queue @ 90306840500. Starting simulation... +info: Entering event queue @ 90500259000. Starting simulation... switching cpus -info: Entering event queue @ 90306899500. Starting simulation... +info: Entering event queue @ 90500266500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 91306899500. Starting simulation... +info: Entering event queue @ 91500266500. Starting simulation... switching cpus -info: Entering event queue @ 91306906500. Starting simulation... +info: Entering event queue @ 91500274000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 92306906500. Starting simulation... +info: Entering event queue @ 92500274000. Starting simulation... switching cpus -info: Entering event queue @ 92306907500. Starting simulation... +info: Entering event queue @ 92500281500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 93306907500. Starting simulation... +info: Entering event queue @ 93500281500. Starting simulation... switching cpus -info: Entering event queue @ 93306908500. Starting simulation... +info: Entering event queue @ 93500292500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 94306908500. Starting simulation... +info: Entering event queue @ 94500292500. Starting simulation... +info: Entering event queue @ 94500313500. Starting simulation... switching cpus -info: Entering event queue @ 94306931500. Starting simulation... +info: Entering event queue @ 94500420000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 95306931500. Starting simulation... +info: Entering event queue @ 95500420000. Starting simulation... switching cpus -info: Entering event queue @ 95306933500. Starting simulation... +info: Entering event queue @ 95500427500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 96306933500. Starting simulation... +info: Entering event queue @ 96500427500. Starting simulation... switching cpus -info: Entering event queue @ 96307006500. Starting simulation... +info: Entering event queue @ 96500441500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 97307006500. Starting simulation... -info: Entering event queue @ 97307011500. Starting simulation... +info: Entering event queue @ 97500441500. Starting simulation... +info: Entering event queue @ 97500449000. Starting simulation... switching cpus -info: Entering event queue @ 97307013000. Starting simulation... +info: Entering event queue @ 97500450000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 98307013000. Starting simulation... -info: Entering event queue @ 99022063000. Starting simulation... +info: Entering event queue @ 98500450000. Starting simulation... +info: Entering event queue @ 99219551000. Starting simulation... switching cpus -info: Entering event queue @ 99022065000. Starting simulation... +info: Entering event queue @ 99219553000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 100022065000. Starting simulation... +info: Entering event queue @ 100219553000. Starting simulation... switching cpus -info: Entering event queue @ 100022065500. Starting simulation... +info: Entering event queue @ 100219553500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 101022065500. Starting simulation... +info: Entering event queue @ 101219553500. Starting simulation... switching cpus -info: Entering event queue @ 101022067500. Starting simulation... +info: Entering event queue @ 101219554000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 102022067500. Starting simulation... +info: Entering event queue @ 102219554000. Starting simulation... switching cpus -info: Entering event queue @ 102022068500. Starting simulation... +info: Entering event queue @ 102219560000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 103022068500. Starting simulation... +info: Entering event queue @ 103219560000. Starting simulation... switching cpus -info: Entering event queue @ 103022072000. Starting simulation... +info: Entering event queue @ 103219562000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 104022072000. Starting simulation... +info: Entering event queue @ 104219562000. Starting simulation... switching cpus -info: Entering event queue @ 104022073000. Starting simulation... +info: Entering event queue @ 104219563000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 105022073000. Starting simulation... +info: Entering event queue @ 105219563000. Starting simulation... switching cpus -info: Entering event queue @ 105022074500. Starting simulation... +info: Entering event queue @ 105219565000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 106022074500. Starting simulation... +info: Entering event queue @ 106219565000. Starting simulation... switching cpus -info: Entering event queue @ 106022075000. Starting simulation... +info: Entering event queue @ 106219567000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 107022075000. Starting simulation... -info: Entering event queue @ 107022087500. Starting simulation... +info: Entering event queue @ 107219567000. Starting simulation... switching cpus -info: Entering event queue @ 107022090000. Starting simulation... +info: Entering event queue @ 107219568000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 108022090000. Starting simulation... +info: Entering event queue @ 108219568000. Starting simulation... switching cpus -info: Entering event queue @ 108022090500. Starting simulation... +info: Entering event queue @ 108219614500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 109022090500. Starting simulation... +info: Entering event queue @ 109219614500. Starting simulation... switching cpus -info: Entering event queue @ 109022092500. Starting simulation... +info: Entering event queue @ 109219615500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 110022092500. Starting simulation... -info: Entering event queue @ 110022099500. Starting simulation... +info: Entering event queue @ 110219615500. Starting simulation... +info: Entering event queue @ 110219625000. Starting simulation... switching cpus -info: Entering event queue @ 110022103000. Starting simulation... +info: Entering event queue @ 110219627500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 111022103000. Starting simulation... +info: Entering event queue @ 111219627500. Starting simulation... switching cpus -info: Entering event queue @ 111022104000. Starting simulation... +info: Entering event queue @ 111219635000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 112219635000. Starting simulation... switching cpus -info: Entering event queue @ 112022104000. Starting simulation... +info: Entering event queue @ 112219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 113022104000. Starting simulation... +info: Entering event queue @ 113219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 114022104000. Starting simulation... +info: Entering event queue @ 114219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 115022104000. Starting simulation... +info: Entering event queue @ 115219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 116022104000. Starting simulation... +info: Entering event queue @ 116219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 117022104000. Starting simulation... +info: Entering event queue @ 117219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 118022104000. Starting simulation... +info: Entering event queue @ 118219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 119022104000. Starting simulation... +info: Entering event queue @ 119219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 120022104000. Starting simulation... +info: Entering event queue @ 120219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 121022104000. Starting simulation... +info: Entering event queue @ 121219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 122022104000. Starting simulation... +info: Entering event queue @ 122219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 123022104000. Starting simulation... +info: Entering event queue @ 123219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 124022104000. Starting simulation... +info: Entering event queue @ 124219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 125022104000. Starting simulation... +info: Entering event queue @ 125219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 126022104000. Starting simulation... +info: Entering event queue @ 126219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 127022104000. Starting simulation... +info: Entering event queue @ 127219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 128022104000. Starting simulation... +info: Entering event queue @ 128219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 129022104000. Starting simulation... +info: Entering event queue @ 129219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 130022104000. Starting simulation... +info: Entering event queue @ 130219642500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 131022104000. Starting simulation... -info: Entering event queue @ 131758663000. Starting simulation... +info: Entering event queue @ 131219642500. Starting simulation... +info: Entering event queue @ 131956130000. Starting simulation... switching cpus -info: Entering event queue @ 131758665000. Starting simulation... +info: Entering event queue @ 131956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 132758665000. Starting simulation... +info: Entering event queue @ 132956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 133758665000. Starting simulation... +info: Entering event queue @ 133956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 134758665000. Starting simulation... +info: Entering event queue @ 134956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 135758665000. Starting simulation... +info: Entering event queue @ 135956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 136758665000. Starting simulation... +info: Entering event queue @ 136956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 137758665000. Starting simulation... +info: Entering event queue @ 137956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 138758665000. Starting simulation... +info: Entering event queue @ 138956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 139758665000. Starting simulation... +info: Entering event queue @ 139956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 140758665000. Starting simulation... +info: Entering event queue @ 140956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 141758665000. Starting simulation... +info: Entering event queue @ 141956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 142758665000. Starting simulation... +info: Entering event queue @ 142956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 143758665000. Starting simulation... +info: Entering event queue @ 143956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 144758665000. Starting simulation... +info: Entering event queue @ 144956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 145758665000. Starting simulation... +info: Entering event queue @ 145956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 146758665000. Starting simulation... +info: Entering event queue @ 146956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 147758665000. Starting simulation... +info: Entering event queue @ 147956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 148758665000. Starting simulation... +info: Entering event queue @ 148956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 149758665000. Starting simulation... +info: Entering event queue @ 149956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 150758665000. Starting simulation... +info: Entering event queue @ 150956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 151758665000. Starting simulation... +info: Entering event queue @ 151956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 152758665000. Starting simulation... +info: Entering event queue @ 152956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 153758665000. Starting simulation... +info: Entering event queue @ 153956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 154758665000. Starting simulation... +info: Entering event queue @ 154956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 155758665000. Starting simulation... +info: Entering event queue @ 155956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 156758665000. Starting simulation... +info: Entering event queue @ 156956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 157758665000. Starting simulation... +info: Entering event queue @ 157956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 158758665000. Starting simulation... +info: Entering event queue @ 158956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 159758665000. Starting simulation... +info: Entering event queue @ 159956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 160758665000. Starting simulation... +info: Entering event queue @ 160956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 161758665000. Starting simulation... +info: Entering event queue @ 161956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 162758665000. Starting simulation... +info: Entering event queue @ 162956132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 163758665000. Starting simulation... -info: Entering event queue @ 164494807000. Starting simulation... +info: Entering event queue @ 163956132000. Starting simulation... +info: Entering event queue @ 164692730000. Starting simulation... switching cpus -info: Entering event queue @ 164494809000. Starting simulation... +info: Entering event queue @ 164692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 165494809000. Starting simulation... +info: Entering event queue @ 165692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 166494809000. Starting simulation... +info: Entering event queue @ 166692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 167494809000. Starting simulation... +info: Entering event queue @ 167692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 168494809000. Starting simulation... +info: Entering event queue @ 168692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 169494809000. Starting simulation... +info: Entering event queue @ 169692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 170494809000. Starting simulation... +info: Entering event queue @ 170692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 171494809000. Starting simulation... +info: Entering event queue @ 171692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 172494809000. Starting simulation... +info: Entering event queue @ 172692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 173494809000. Starting simulation... +info: Entering event queue @ 173692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 174494809000. Starting simulation... +info: Entering event queue @ 174692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 175494809000. Starting simulation... +info: Entering event queue @ 175692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 176494809000. Starting simulation... +info: Entering event queue @ 176692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 177494809000. Starting simulation... +info: Entering event queue @ 177692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 178494809000. Starting simulation... +info: Entering event queue @ 178692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 179494809000. Starting simulation... +info: Entering event queue @ 179692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 180494809000. Starting simulation... +info: Entering event queue @ 180692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 181494809000. Starting simulation... +info: Entering event queue @ 181692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 182494809000. Starting simulation... +info: Entering event queue @ 182692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 183494809000. Starting simulation... +info: Entering event queue @ 183692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 184494809000. Starting simulation... +info: Entering event queue @ 184692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 185494809000. Starting simulation... +info: Entering event queue @ 185692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 186494809000. Starting simulation... +info: Entering event queue @ 186692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 187494809000. Starting simulation... +info: Entering event queue @ 187692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 188494809000. Starting simulation... +info: Entering event queue @ 188692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 189494809000. Starting simulation... +info: Entering event queue @ 189692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 190494809000. Starting simulation... +info: Entering event queue @ 190692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 191494809000. Starting simulation... +info: Entering event queue @ 191692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 192494809000. Starting simulation... +info: Entering event queue @ 192692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 193494809000. Starting simulation... +info: Entering event queue @ 193692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 194494809000. Starting simulation... +info: Entering event queue @ 194692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 195494809000. Starting simulation... +info: Entering event queue @ 195692732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 196494809000. Starting simulation... -info: Entering event queue @ 197230954000. Starting simulation... +info: Entering event queue @ 196692732000. Starting simulation... +info: Entering event queue @ 197429351000. Starting simulation... switching cpus -info: Entering event queue @ 197230956000. Starting simulation... +info: Entering event queue @ 197429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 198230956000. Starting simulation... +info: Entering event queue @ 198429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 199230956000. Starting simulation... +info: Entering event queue @ 199429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 200230956000. Starting simulation... +info: Entering event queue @ 200429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 201230956000. Starting simulation... +info: Entering event queue @ 201429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 202230956000. Starting simulation... +info: Entering event queue @ 202429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 203230956000. Starting simulation... +info: Entering event queue @ 203429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 204230956000. Starting simulation... +info: Entering event queue @ 204429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 205230956000. Starting simulation... +info: Entering event queue @ 205429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 206230956000. Starting simulation... +info: Entering event queue @ 206429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 207230956000. Starting simulation... +info: Entering event queue @ 207429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 208230956000. Starting simulation... +info: Entering event queue @ 208429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 209230956000. Starting simulation... +info: Entering event queue @ 209429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 210230956000. Starting simulation... +info: Entering event queue @ 210429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 211230956000. Starting simulation... +info: Entering event queue @ 211429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 212230956000. Starting simulation... +info: Entering event queue @ 212429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 213230956000. Starting simulation... +info: Entering event queue @ 213429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 214230956000. Starting simulation... +info: Entering event queue @ 214429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 215230956000. Starting simulation... +info: Entering event queue @ 215429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 216230956000. Starting simulation... +info: Entering event queue @ 216429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 217230956000. Starting simulation... +info: Entering event queue @ 217429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 218230956000. Starting simulation... +info: Entering event queue @ 218429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 219230956000. Starting simulation... +info: Entering event queue @ 219429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 220230956000. Starting simulation... +info: Entering event queue @ 220429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 221230956000. Starting simulation... +info: Entering event queue @ 221429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 222230956000. Starting simulation... +info: Entering event queue @ 222429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 223230956000. Starting simulation... +info: Entering event queue @ 223429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 224230956000. Starting simulation... +info: Entering event queue @ 224429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 225230956000. Starting simulation... +info: Entering event queue @ 225429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 226230956000. Starting simulation... +info: Entering event queue @ 226429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 227230956000. Starting simulation... +info: Entering event queue @ 227429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 228230956000. Starting simulation... +info: Entering event queue @ 228429353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 229230956000. Starting simulation... -info: Entering event queue @ 229967245000. Starting simulation... +info: Entering event queue @ 229429353000. Starting simulation... +info: Entering event queue @ 230164914000. Starting simulation... switching cpus -info: Entering event queue @ 229967247000. Starting simulation... +info: Entering event queue @ 230164916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 230967247000. Starting simulation... +info: Entering event queue @ 231164916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 231967247000. Starting simulation... +info: Entering event queue @ 232164916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 232967247000. Starting simulation... +info: Entering event queue @ 233164916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 233967247000. Starting simulation... +info: Entering event queue @ 234164916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 234967247000. Starting simulation... +info: Entering event queue @ 235164916000. Starting simulation... switching cpus -info: Entering event queue @ 234967248000. Starting simulation... +info: Entering event queue @ 235164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 235967248000. Starting simulation... +info: Entering event queue @ 236164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 236967248000. Starting simulation... +info: Entering event queue @ 237164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 237967248000. Starting simulation... +info: Entering event queue @ 238164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 238967248000. Starting simulation... +info: Entering event queue @ 239164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 239967248000. Starting simulation... +info: Entering event queue @ 240164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 240967248000. Starting simulation... +info: Entering event queue @ 241164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 241967248000. Starting simulation... +info: Entering event queue @ 242164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 242967248000. Starting simulation... +info: Entering event queue @ 243164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 243967248000. Starting simulation... +info: Entering event queue @ 244164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 244967248000. Starting simulation... +info: Entering event queue @ 245164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 245967248000. Starting simulation... +info: Entering event queue @ 246164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 246967248000. Starting simulation... +info: Entering event queue @ 247164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 247967248000. Starting simulation... +info: Entering event queue @ 248164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 248967248000. Starting simulation... +info: Entering event queue @ 249164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 249967248000. Starting simulation... +info: Entering event queue @ 250164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 250967248000. Starting simulation... +info: Entering event queue @ 251164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 251967248000. Starting simulation... +info: Entering event queue @ 252164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 252967248000. Starting simulation... +info: Entering event queue @ 253164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 253967248000. Starting simulation... +info: Entering event queue @ 254164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 254967248000. Starting simulation... +info: Entering event queue @ 255164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 255967248000. Starting simulation... +info: Entering event queue @ 256164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 256967248000. Starting simulation... +info: Entering event queue @ 257164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 257967248000. Starting simulation... +info: Entering event queue @ 258164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 258967248000. Starting simulation... +info: Entering event queue @ 259164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 259967248000. Starting simulation... +info: Entering event queue @ 260164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 260967248000. Starting simulation... +info: Entering event queue @ 261164923500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 261967248000. Starting simulation... -info: Entering event queue @ 262703389000. Starting simulation... +info: Entering event queue @ 262164923500. Starting simulation... +info: Entering event queue @ 262901514000. Starting simulation... switching cpus -info: Entering event queue @ 262703391000. Starting simulation... +info: Entering event queue @ 262901516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 263703391000. Starting simulation... +info: Entering event queue @ 263901516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 264901516000. Starting simulation... switching cpus -info: Entering event queue @ 264703391000. Starting simulation... +info: Entering event queue @ 264901593000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 265703391000. Starting simulation... -info: Entering event queue @ 265703411000. Starting simulation... +info: Entering event queue @ 265901593000. Starting simulation... switching cpus -info: Entering event queue @ 265703413500. Starting simulation... +info: Entering event queue @ 265901798500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 266703413500. Starting simulation... +info: Entering event queue @ 266901798500. Starting simulation... switching cpus -info: Entering event queue @ 266703416000. Starting simulation... +info: Entering event queue @ 266901833000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 267703416000. Starting simulation... +info: Entering event queue @ 267901833000. Starting simulation... switching cpus -info: Entering event queue @ 267703417000. Starting simulation... +info: Entering event queue @ 267901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 268703417000. Starting simulation... +info: Entering event queue @ 268901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 269703417000. Starting simulation... +info: Entering event queue @ 269901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 270703417000. Starting simulation... +info: Entering event queue @ 270901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 271703417000. Starting simulation... +info: Entering event queue @ 271901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 272703417000. Starting simulation... +info: Entering event queue @ 272901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 273703417000. Starting simulation... +info: Entering event queue @ 273901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 274703417000. Starting simulation... +info: Entering event queue @ 274901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 275703417000. Starting simulation... +info: Entering event queue @ 275901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 276703417000. Starting simulation... +info: Entering event queue @ 276901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 277703417000. Starting simulation... +info: Entering event queue @ 277901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 278703417000. Starting simulation... +info: Entering event queue @ 278901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 279703417000. Starting simulation... +info: Entering event queue @ 279901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 280703417000. Starting simulation... +info: Entering event queue @ 280901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 281703417000. Starting simulation... +info: Entering event queue @ 281901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 282703417000. Starting simulation... +info: Entering event queue @ 282901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 283703417000. Starting simulation... +info: Entering event queue @ 283901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 284703417000. Starting simulation... +info: Entering event queue @ 284901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 285703417000. Starting simulation... +info: Entering event queue @ 285901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 286703417000. Starting simulation... +info: Entering event queue @ 286901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 287703417000. Starting simulation... +info: Entering event queue @ 287901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 288703417000. Starting simulation... +info: Entering event queue @ 288901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 289703417000. Starting simulation... +info: Entering event queue @ 289901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 290703417000. Starting simulation... +info: Entering event queue @ 290901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 291703417000. Starting simulation... +info: Entering event queue @ 291901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 292703417000. Starting simulation... +info: Entering event queue @ 292901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 293703417000. Starting simulation... +info: Entering event queue @ 293901840500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 294703417000. Starting simulation... -info: Entering event queue @ 295439680000. Starting simulation... +info: Entering event queue @ 294901840500. Starting simulation... +info: Entering event queue @ 295638135000. Starting simulation... switching cpus -info: Entering event queue @ 295439682000. Starting simulation... +info: Entering event queue @ 295638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 296439682000. Starting simulation... +info: Entering event queue @ 296638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 297439682000. Starting simulation... +info: Entering event queue @ 297638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 298439682000. Starting simulation... +info: Entering event queue @ 298638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 299439682000. Starting simulation... +info: Entering event queue @ 299638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 300439682000. Starting simulation... +info: Entering event queue @ 300638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 301439682000. Starting simulation... +info: Entering event queue @ 301638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 302439682000. Starting simulation... +info: Entering event queue @ 302638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 303439682000. Starting simulation... +info: Entering event queue @ 303638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 304439682000. Starting simulation... +info: Entering event queue @ 304638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 305439682000. Starting simulation... +info: Entering event queue @ 305638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 306439682000. Starting simulation... +info: Entering event queue @ 306638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 307439682000. Starting simulation... +info: Entering event queue @ 307638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 308439682000. Starting simulation... +info: Entering event queue @ 308638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 309439682000. Starting simulation... +info: Entering event queue @ 309638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 310439682000. Starting simulation... +info: Entering event queue @ 310638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 311439682000. Starting simulation... +info: Entering event queue @ 311638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 312439682000. Starting simulation... +info: Entering event queue @ 312638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 313439682000. Starting simulation... +info: Entering event queue @ 313638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 314439682000. Starting simulation... +info: Entering event queue @ 314638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 315439682000. Starting simulation... +info: Entering event queue @ 315638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 316439682000. Starting simulation... +info: Entering event queue @ 316638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 317439682000. Starting simulation... +info: Entering event queue @ 317638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 318439682000. Starting simulation... +info: Entering event queue @ 318638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 319439682000. Starting simulation... +info: Entering event queue @ 319638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 320439682000. Starting simulation... +info: Entering event queue @ 320638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 321439682000. Starting simulation... +info: Entering event queue @ 321638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 322439682000. Starting simulation... +info: Entering event queue @ 322638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 323439682000. Starting simulation... +info: Entering event queue @ 323638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 324439682000. Starting simulation... +info: Entering event queue @ 324638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 325439682000. Starting simulation... +info: Entering event queue @ 325638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 326439682000. Starting simulation... +info: Entering event queue @ 326638137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 327439682000. Starting simulation... -info: Entering event queue @ 328175821000. Starting simulation... +info: Entering event queue @ 327638137000. Starting simulation... +info: Entering event queue @ 328373547000. Starting simulation... switching cpus -info: Entering event queue @ 328175823000. Starting simulation... +info: Entering event queue @ 328373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 329175823000. Starting simulation... +info: Entering event queue @ 329373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 330175823000. Starting simulation... +info: Entering event queue @ 330373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 331175823000. Starting simulation... +info: Entering event queue @ 331373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 332175823000. Starting simulation... +info: Entering event queue @ 332373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 333175823000. Starting simulation... +info: Entering event queue @ 333373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 334175823000. Starting simulation... +info: Entering event queue @ 334373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 335175823000. Starting simulation... +info: Entering event queue @ 335373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 336175823000. Starting simulation... +info: Entering event queue @ 336373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 337175823000. Starting simulation... +info: Entering event queue @ 337373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 338175823000. Starting simulation... +info: Entering event queue @ 338373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 339175823000. Starting simulation... +info: Entering event queue @ 339373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 340175823000. Starting simulation... +info: Entering event queue @ 340373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 341175823000. Starting simulation... +info: Entering event queue @ 341373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 342175823000. Starting simulation... +info: Entering event queue @ 342373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 343175823000. Starting simulation... +info: Entering event queue @ 343373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 344175823000. Starting simulation... +info: Entering event queue @ 344373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 345175823000. Starting simulation... +info: Entering event queue @ 345373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 346175823000. Starting simulation... +info: Entering event queue @ 346373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 347175823000. Starting simulation... +info: Entering event queue @ 347373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 348175823000. Starting simulation... +info: Entering event queue @ 348373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 349175823000. Starting simulation... +info: Entering event queue @ 349373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 350175823000. Starting simulation... +info: Entering event queue @ 350373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 351175823000. Starting simulation... +info: Entering event queue @ 351373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 352175823000. Starting simulation... +info: Entering event queue @ 352373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 353175823000. Starting simulation... +info: Entering event queue @ 353373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 354175823000. Starting simulation... +info: Entering event queue @ 354373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 355175823000. Starting simulation... +info: Entering event queue @ 355373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 356175823000. Starting simulation... +info: Entering event queue @ 356373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 357175823000. Starting simulation... +info: Entering event queue @ 357373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 358175823000. Starting simulation... +info: Entering event queue @ 358373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 359175823000. Starting simulation... +info: Entering event queue @ 359373549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 360175823000. Starting simulation... -info: Entering event queue @ 360912115000. Starting simulation... +info: Entering event queue @ 360373549000. Starting simulation... +info: Entering event queue @ 361110147000. Starting simulation... switching cpus -info: Entering event queue @ 360912117000. Starting simulation... +info: Entering event queue @ 361110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 361912117000. Starting simulation... +info: Entering event queue @ 362110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 362912117000. Starting simulation... +info: Entering event queue @ 363110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 363912117000. Starting simulation... +info: Entering event queue @ 364110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 364912117000. Starting simulation... +info: Entering event queue @ 365110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 365912117000. Starting simulation... +info: Entering event queue @ 366110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 366912117000. Starting simulation... +info: Entering event queue @ 367110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 367912117000. Starting simulation... +info: Entering event queue @ 368110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 368912117000. Starting simulation... +info: Entering event queue @ 369110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 369912117000. Starting simulation... +info: Entering event queue @ 370110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 370912117000. Starting simulation... +info: Entering event queue @ 371110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 371912117000. Starting simulation... +info: Entering event queue @ 372110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 372912117000. Starting simulation... +info: Entering event queue @ 373110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 373912117000. Starting simulation... +info: Entering event queue @ 374110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 374912117000. Starting simulation... +info: Entering event queue @ 375110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 375912117000. Starting simulation... +info: Entering event queue @ 376110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 376912117000. Starting simulation... +info: Entering event queue @ 377110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 377912117000. Starting simulation... +info: Entering event queue @ 378110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 378912117000. Starting simulation... +info: Entering event queue @ 379110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 379912117000. Starting simulation... +info: Entering event queue @ 380110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 380912117000. Starting simulation... +info: Entering event queue @ 381110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 381912117000. Starting simulation... +info: Entering event queue @ 382110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 382912117000. Starting simulation... +info: Entering event queue @ 383110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 383912117000. Starting simulation... +info: Entering event queue @ 384110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 384912117000. Starting simulation... +info: Entering event queue @ 385110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 385912117000. Starting simulation... +info: Entering event queue @ 386110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 386912117000. Starting simulation... +info: Entering event queue @ 387110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 387912117000. Starting simulation... +info: Entering event queue @ 388110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 388912117000. Starting simulation... +info: Entering event queue @ 389110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 389912117000. Starting simulation... +info: Entering event queue @ 390110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 390912117000. Starting simulation... +info: Entering event queue @ 391110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 391912117000. Starting simulation... +info: Entering event queue @ 392110149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 392912117000. Starting simulation... -info: Entering event queue @ 393648256000. Starting simulation... +info: Entering event queue @ 393110149000. Starting simulation... +info: Entering event queue @ 393846726000. Starting simulation... switching cpus -info: Entering event queue @ 393648258000. Starting simulation... +info: Entering event queue @ 393846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 394648258000. Starting simulation... +info: Entering event queue @ 394846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 395648258000. Starting simulation... +info: Entering event queue @ 395846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 396648258000. Starting simulation... +info: Entering event queue @ 396846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 397648258000. Starting simulation... +info: Entering event queue @ 397846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 398648258000. Starting simulation... +info: Entering event queue @ 398846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 399648258000. Starting simulation... +info: Entering event queue @ 399846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 400648258000. Starting simulation... +info: Entering event queue @ 400846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 401648258000. Starting simulation... +info: Entering event queue @ 401846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 402648258000. Starting simulation... +info: Entering event queue @ 402846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 403648258000. Starting simulation... +info: Entering event queue @ 403846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 404648258000. Starting simulation... +info: Entering event queue @ 404846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 405648258000. Starting simulation... +info: Entering event queue @ 405846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 406648258000. Starting simulation... +info: Entering event queue @ 406846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 407648258000. Starting simulation... +info: Entering event queue @ 407846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 408648258000. Starting simulation... +info: Entering event queue @ 408846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 409648258000. Starting simulation... +info: Entering event queue @ 409846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 410648258000. Starting simulation... +info: Entering event queue @ 410846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 411648258000. Starting simulation... +info: Entering event queue @ 411846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 412648258000. Starting simulation... +info: Entering event queue @ 412846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 413648258000. Starting simulation... +info: Entering event queue @ 413846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 414648258000. Starting simulation... +info: Entering event queue @ 414846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 415648258000. Starting simulation... +info: Entering event queue @ 415846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 416648258000. Starting simulation... +info: Entering event queue @ 416846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 417648258000. Starting simulation... +info: Entering event queue @ 417846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 418648258000. Starting simulation... +info: Entering event queue @ 418846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 419648258000. Starting simulation... +info: Entering event queue @ 419846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 420648258000. Starting simulation... +info: Entering event queue @ 420846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 421648258000. Starting simulation... +info: Entering event queue @ 421846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 422648258000. Starting simulation... +info: Entering event queue @ 422846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 423648258000. Starting simulation... +info: Entering event queue @ 423846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 424648258000. Starting simulation... +info: Entering event queue @ 424846728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 425648258000. Starting simulation... -info: Entering event queue @ 426384856000. Starting simulation... +info: Entering event queue @ 425846728000. Starting simulation... +info: Entering event queue @ 426582138000. Starting simulation... switching cpus -info: Entering event queue @ 426384858000. Starting simulation... +info: Entering event queue @ 426582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 427384858000. Starting simulation... +info: Entering event queue @ 427582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 428384858000. Starting simulation... +info: Entering event queue @ 428582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 429384858000. Starting simulation... +info: Entering event queue @ 429582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 430384858000. Starting simulation... +info: Entering event queue @ 430582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 431384858000. Starting simulation... +info: Entering event queue @ 431582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 432384858000. Starting simulation... +info: Entering event queue @ 432582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 433384858000. Starting simulation... +info: Entering event queue @ 433582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 434384858000. Starting simulation... +info: Entering event queue @ 434582140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 435384858000. Starting simulation... +info: Entering event queue @ 435582140000. Starting simulation... switching cpus -info: Entering event queue @ 435384859000. Starting simulation... +info: Entering event queue @ 435582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 436384859000. Starting simulation... +info: Entering event queue @ 436582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 437384859000. Starting simulation... +info: Entering event queue @ 437582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 438384859000. Starting simulation... +info: Entering event queue @ 438582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 439384859000. Starting simulation... +info: Entering event queue @ 439582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 440384859000. Starting simulation... +info: Entering event queue @ 440582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 441384859000. Starting simulation... +info: Entering event queue @ 441582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 442384859000. Starting simulation... +info: Entering event queue @ 442582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 443384859000. Starting simulation... +info: Entering event queue @ 443582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 444384859000. Starting simulation... +info: Entering event queue @ 444582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 445384859000. Starting simulation... +info: Entering event queue @ 445582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 446384859000. Starting simulation... +info: Entering event queue @ 446582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 447384859000. Starting simulation... +info: Entering event queue @ 447582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 448384859000. Starting simulation... +info: Entering event queue @ 448582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 449384859000. Starting simulation... +info: Entering event queue @ 449582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 450384859000. Starting simulation... +info: Entering event queue @ 450582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 451384859000. Starting simulation... +info: Entering event queue @ 451582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 452384859000. Starting simulation... +info: Entering event queue @ 452582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 453384859000. Starting simulation... +info: Entering event queue @ 453582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 454384859000. Starting simulation... +info: Entering event queue @ 454582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 455384859000. Starting simulation... +info: Entering event queue @ 455582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 456384859000. Starting simulation... +info: Entering event queue @ 456582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 457384859000. Starting simulation... +info: Entering event queue @ 457582147500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 458384859000. Starting simulation... -info: Entering event queue @ 459121147000. Starting simulation... +info: Entering event queue @ 458582147500. Starting simulation... +info: Entering event queue @ 459318738000. Starting simulation... switching cpus -info: Entering event queue @ 459121149000. Starting simulation... +info: Entering event queue @ 459318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 460121149000. Starting simulation... +info: Entering event queue @ 460318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 461121149000. Starting simulation... +info: Entering event queue @ 461318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 462121149000. Starting simulation... +info: Entering event queue @ 462318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 463121149000. Starting simulation... +info: Entering event queue @ 463318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 464121149000. Starting simulation... +info: Entering event queue @ 464318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 465121149000. Starting simulation... +info: Entering event queue @ 465318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 466121149000. Starting simulation... +info: Entering event queue @ 466318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 467121149000. Starting simulation... +info: Entering event queue @ 467318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 468121149000. Starting simulation... +info: Entering event queue @ 468318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 469121149000. Starting simulation... +info: Entering event queue @ 469318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 470121149000. Starting simulation... +info: Entering event queue @ 470318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 471121149000. Starting simulation... +info: Entering event queue @ 471318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 472121149000. Starting simulation... +info: Entering event queue @ 472318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 473121149000. Starting simulation... +info: Entering event queue @ 473318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 474121149000. Starting simulation... +info: Entering event queue @ 474318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 475121149000. Starting simulation... +info: Entering event queue @ 475318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 476121149000. Starting simulation... +info: Entering event queue @ 476318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 477121149000. Starting simulation... +info: Entering event queue @ 477318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 478121149000. Starting simulation... +info: Entering event queue @ 478318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 479121149000. Starting simulation... +info: Entering event queue @ 479318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 480121149000. Starting simulation... +info: Entering event queue @ 480318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 481121149000. Starting simulation... +info: Entering event queue @ 481318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 482121149000. Starting simulation... +info: Entering event queue @ 482318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 483121149000. Starting simulation... +info: Entering event queue @ 483318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 484121149000. Starting simulation... +info: Entering event queue @ 484318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 485121149000. Starting simulation... +info: Entering event queue @ 485318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 486121149000. Starting simulation... +info: Entering event queue @ 486318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 487121149000. Starting simulation... +info: Entering event queue @ 487318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 488121149000. Starting simulation... +info: Entering event queue @ 488318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 489121149000. Starting simulation... +info: Entering event queue @ 489318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 490121149000. Starting simulation... +info: Entering event queue @ 490318740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 491121149000. Starting simulation... -info: Entering event queue @ 491857291000. Starting simulation... +info: Entering event queue @ 491318740000. Starting simulation... +info: Entering event queue @ 492055355000. Starting simulation... switching cpus -info: Entering event queue @ 491857293000. Starting simulation... +info: Entering event queue @ 492055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 492857293000. Starting simulation... +info: Entering event queue @ 493055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 493857293000. Starting simulation... +info: Entering event queue @ 494055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 494857293000. Starting simulation... +info: Entering event queue @ 495055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 495857293000. Starting simulation... +info: Entering event queue @ 496055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 496857293000. Starting simulation... +info: Entering event queue @ 497055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 497857293000. Starting simulation... +info: Entering event queue @ 498055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 498857293000. Starting simulation... +info: Entering event queue @ 499055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 499857293000. Starting simulation... +info: Entering event queue @ 500055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 500857293000. Starting simulation... +info: Entering event queue @ 501055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 501857293000. Starting simulation... +info: Entering event queue @ 502055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 502857293000. Starting simulation... +info: Entering event queue @ 503055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 503857293000. Starting simulation... +info: Entering event queue @ 504055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 504857293000. Starting simulation... +info: Entering event queue @ 505055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 505857293000. Starting simulation... +info: Entering event queue @ 506055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 506857293000. Starting simulation... +info: Entering event queue @ 507055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 507857293000. Starting simulation... +info: Entering event queue @ 508055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 508857293000. Starting simulation... +info: Entering event queue @ 509055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 509857293000. Starting simulation... +info: Entering event queue @ 510055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 510857293000. Starting simulation... +info: Entering event queue @ 511055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 511857293000. Starting simulation... +info: Entering event queue @ 512055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 512857293000. Starting simulation... +info: Entering event queue @ 513055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 513857293000. Starting simulation... +info: Entering event queue @ 514055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 514857293000. Starting simulation... +info: Entering event queue @ 515055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 515857293000. Starting simulation... +info: Entering event queue @ 516055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 516857293000. Starting simulation... +info: Entering event queue @ 517055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 517857293000. Starting simulation... +info: Entering event queue @ 518055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 518857293000. Starting simulation... +info: Entering event queue @ 519055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 519857293000. Starting simulation... +info: Entering event queue @ 520055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 520857293000. Starting simulation... +info: Entering event queue @ 521055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 521857293000. Starting simulation... +info: Entering event queue @ 522055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 522857293000. Starting simulation... +info: Entering event queue @ 523055357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 523857293000. Starting simulation... -info: Entering event queue @ 524593582000. Starting simulation... +info: Entering event queue @ 524055357000. Starting simulation... +info: Entering event queue @ 524790922000. Starting simulation... switching cpus -info: Entering event queue @ 524593584000. Starting simulation... +info: Entering event queue @ 524790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 525593584000. Starting simulation... +info: Entering event queue @ 525790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 526593584000. Starting simulation... +info: Entering event queue @ 526790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 527593584000. Starting simulation... +info: Entering event queue @ 527790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 528593584000. Starting simulation... +info: Entering event queue @ 528790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 529593584000. Starting simulation... +info: Entering event queue @ 529790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 530593584000. Starting simulation... +info: Entering event queue @ 530790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 531593584000. Starting simulation... +info: Entering event queue @ 531790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 532593584000. Starting simulation... +info: Entering event queue @ 532790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 533593584000. Starting simulation... +info: Entering event queue @ 533790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 534593584000. Starting simulation... +info: Entering event queue @ 534790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 535593584000. Starting simulation... +info: Entering event queue @ 535790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 536593584000. Starting simulation... +info: Entering event queue @ 536790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 537593584000. Starting simulation... +info: Entering event queue @ 537790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 538593584000. Starting simulation... +info: Entering event queue @ 538790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 539593584000. Starting simulation... +info: Entering event queue @ 539790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 540593584000. Starting simulation... +info: Entering event queue @ 540790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 541593584000. Starting simulation... +info: Entering event queue @ 541790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 542593584000. Starting simulation... +info: Entering event queue @ 542790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 543593584000. Starting simulation... +info: Entering event queue @ 543790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 544593584000. Starting simulation... +info: Entering event queue @ 544790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 545593584000. Starting simulation... +info: Entering event queue @ 545790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 546593584000. Starting simulation... +info: Entering event queue @ 546790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 547593584000. Starting simulation... +info: Entering event queue @ 547790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 548593584000. Starting simulation... +info: Entering event queue @ 548790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 549593584000. Starting simulation... +info: Entering event queue @ 549790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 550593584000. Starting simulation... +info: Entering event queue @ 550790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 551593584000. Starting simulation... +info: Entering event queue @ 551790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 552593584000. Starting simulation... +info: Entering event queue @ 552790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 553593584000. Starting simulation... +info: Entering event queue @ 553790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 554593584000. Starting simulation... +info: Entering event queue @ 554790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 555593584000. Starting simulation... +info: Entering event queue @ 555790924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 556593584000. Starting simulation... -info: Entering event queue @ 557329726000. Starting simulation... +info: Entering event queue @ 556790924000. Starting simulation... +info: Entering event queue @ 557527522000. Starting simulation... switching cpus -info: Entering event queue @ 557329728000. Starting simulation... +info: Entering event queue @ 557527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 558329728000. Starting simulation... +info: Entering event queue @ 558527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 559329728000. Starting simulation... +info: Entering event queue @ 559527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 560329728000. Starting simulation... +info: Entering event queue @ 560527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 561329728000. Starting simulation... +info: Entering event queue @ 561527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 562329728000. Starting simulation... +info: Entering event queue @ 562527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 563329728000. Starting simulation... +info: Entering event queue @ 563527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 564329728000. Starting simulation... +info: Entering event queue @ 564527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 565329728000. Starting simulation... +info: Entering event queue @ 565527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 566329728000. Starting simulation... +info: Entering event queue @ 566527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 567329728000. Starting simulation... +info: Entering event queue @ 567527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 568329728000. Starting simulation... +info: Entering event queue @ 568527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 569329728000. Starting simulation... +info: Entering event queue @ 569527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 570329728000. Starting simulation... +info: Entering event queue @ 570527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 571329728000. Starting simulation... +info: Entering event queue @ 571527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 572329728000. Starting simulation... +info: Entering event queue @ 572527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 573329728000. Starting simulation... +info: Entering event queue @ 573527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 574329728000. Starting simulation... +info: Entering event queue @ 574527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 575329728000. Starting simulation... +info: Entering event queue @ 575527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 576329728000. Starting simulation... +info: Entering event queue @ 576527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 577329728000. Starting simulation... +info: Entering event queue @ 577527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 578329728000. Starting simulation... +info: Entering event queue @ 578527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 579329728000. Starting simulation... +info: Entering event queue @ 579527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 580329728000. Starting simulation... +info: Entering event queue @ 580527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 581329728000. Starting simulation... +info: Entering event queue @ 581527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 582329728000. Starting simulation... +info: Entering event queue @ 582527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 583329728000. Starting simulation... +info: Entering event queue @ 583527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 584329728000. Starting simulation... +info: Entering event queue @ 584527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 585329728000. Starting simulation... +info: Entering event queue @ 585527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 586329728000. Starting simulation... +info: Entering event queue @ 586527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 587329728000. Starting simulation... +info: Entering event queue @ 587527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 588329728000. Starting simulation... +info: Entering event queue @ 588527524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 589329728000. Starting simulation... -info: Entering event queue @ 590065873000. Starting simulation... +info: Entering event queue @ 589527524000. Starting simulation... +info: Entering event queue @ 590264122000. Starting simulation... switching cpus -info: Entering event queue @ 590065875000. Starting simulation... +info: Entering event queue @ 590264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 591065875000. Starting simulation... +info: Entering event queue @ 591264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 592065875000. Starting simulation... +info: Entering event queue @ 592264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 593065875000. Starting simulation... +info: Entering event queue @ 593264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 594065875000. Starting simulation... +info: Entering event queue @ 594264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 595065875000. Starting simulation... +info: Entering event queue @ 595264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 596065875000. Starting simulation... +info: Entering event queue @ 596264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 597065875000. Starting simulation... +info: Entering event queue @ 597264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 598065875000. Starting simulation... +info: Entering event queue @ 598264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 599065875000. Starting simulation... +info: Entering event queue @ 599264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 600065875000. Starting simulation... +info: Entering event queue @ 600264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 601065875000. Starting simulation... +info: Entering event queue @ 601264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 602065875000. Starting simulation... +info: Entering event queue @ 602264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 603065875000. Starting simulation... +info: Entering event queue @ 603264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 604065875000. Starting simulation... +info: Entering event queue @ 604264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 605065875000. Starting simulation... +info: Entering event queue @ 605264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 606065875000. Starting simulation... +info: Entering event queue @ 606264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 607065875000. Starting simulation... +info: Entering event queue @ 607264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 608065875000. Starting simulation... +info: Entering event queue @ 608264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 609065875000. Starting simulation... +info: Entering event queue @ 609264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 610065875000. Starting simulation... +info: Entering event queue @ 610264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 611065875000. Starting simulation... +info: Entering event queue @ 611264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 612065875000. Starting simulation... +info: Entering event queue @ 612264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 613065875000. Starting simulation... +info: Entering event queue @ 613264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 614065875000. Starting simulation... +info: Entering event queue @ 614264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 615065875000. Starting simulation... +info: Entering event queue @ 615264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 616065875000. Starting simulation... +info: Entering event queue @ 616264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 617065875000. Starting simulation... +info: Entering event queue @ 617264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 618065875000. Starting simulation... +info: Entering event queue @ 618264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 619065875000. Starting simulation... +info: Entering event queue @ 619264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 620065875000. Starting simulation... +info: Entering event queue @ 620264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 621065875000. Starting simulation... +info: Entering event queue @ 621264124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 622065875000. Starting simulation... -info: Entering event queue @ 622802473000. Starting simulation... +info: Entering event queue @ 622264124000. Starting simulation... +info: Entering event queue @ 623000743000. Starting simulation... switching cpus -info: Entering event queue @ 622802475000. Starting simulation... +info: Entering event queue @ 623000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 623802475000. Starting simulation... +info: Entering event queue @ 624000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 624802475000. Starting simulation... +info: Entering event queue @ 625000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 625802475000. Starting simulation... +info: Entering event queue @ 626000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 626802475000. Starting simulation... +info: Entering event queue @ 627000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 627802475000. Starting simulation... +info: Entering event queue @ 628000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 628802475000. Starting simulation... +info: Entering event queue @ 629000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 629802475000. Starting simulation... +info: Entering event queue @ 630000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 630802475000. Starting simulation... +info: Entering event queue @ 631000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 631802475000. Starting simulation... +info: Entering event queue @ 632000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 632802475000. Starting simulation... +info: Entering event queue @ 633000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 633802475000. Starting simulation... +info: Entering event queue @ 634000745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 634802475000. Starting simulation... +info: Entering event queue @ 635000745000. Starting simulation... switching cpus -info: Entering event queue @ 634802476000. Starting simulation... +info: Entering event queue @ 635000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 635802476000. Starting simulation... +info: Entering event queue @ 636000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 636802476000. Starting simulation... +info: Entering event queue @ 637000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 637802476000. Starting simulation... +info: Entering event queue @ 638000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 638802476000. Starting simulation... +info: Entering event queue @ 639000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 639802476000. Starting simulation... +info: Entering event queue @ 640000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 640802476000. Starting simulation... +info: Entering event queue @ 641000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 641802476000. Starting simulation... +info: Entering event queue @ 642000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 642802476000. Starting simulation... +info: Entering event queue @ 643000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 643802476000. Starting simulation... +info: Entering event queue @ 644000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 644802476000. Starting simulation... +info: Entering event queue @ 645000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 645802476000. Starting simulation... +info: Entering event queue @ 646000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 646802476000. Starting simulation... +info: Entering event queue @ 647000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 647802476000. Starting simulation... +info: Entering event queue @ 648000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 648802476000. Starting simulation... +info: Entering event queue @ 649000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 649802476000. Starting simulation... +info: Entering event queue @ 650000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 650802476000. Starting simulation... +info: Entering event queue @ 651000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 651802476000. Starting simulation... +info: Entering event queue @ 652000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 652802476000. Starting simulation... +info: Entering event queue @ 653000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 653802476000. Starting simulation... +info: Entering event queue @ 654000752500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 654802476000. Starting simulation... -info: Entering event queue @ 655538305000. Starting simulation... +info: Entering event queue @ 655000752500. Starting simulation... +info: Entering event queue @ 655736155000. Starting simulation... switching cpus -info: Entering event queue @ 655538307000. Starting simulation... +info: Entering event queue @ 655736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 656538307000. Starting simulation... +info: Entering event queue @ 656736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 657538307000. Starting simulation... +info: Entering event queue @ 657736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 658538307000. Starting simulation... +info: Entering event queue @ 658736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 659538307000. Starting simulation... +info: Entering event queue @ 659736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 660538307000. Starting simulation... +info: Entering event queue @ 660736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 661538307000. Starting simulation... +info: Entering event queue @ 661736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 662538307000. Starting simulation... +info: Entering event queue @ 662736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 663538307000. Starting simulation... +info: Entering event queue @ 663736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 664538307000. Starting simulation... +info: Entering event queue @ 664736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 665538307000. Starting simulation... +info: Entering event queue @ 665736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 666538307000. Starting simulation... +info: Entering event queue @ 666736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 667538307000. Starting simulation... +info: Entering event queue @ 667736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 668538307000. Starting simulation... +info: Entering event queue @ 668736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 669538307000. Starting simulation... +info: Entering event queue @ 669736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 670538307000. Starting simulation... +info: Entering event queue @ 670736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 671538307000. Starting simulation... +info: Entering event queue @ 671736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 672538307000. Starting simulation... +info: Entering event queue @ 672736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 673538307000. Starting simulation... +info: Entering event queue @ 673736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 674538307000. Starting simulation... +info: Entering event queue @ 674736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 675538307000. Starting simulation... +info: Entering event queue @ 675736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 676538307000. Starting simulation... +info: Entering event queue @ 676736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 677538307000. Starting simulation... +info: Entering event queue @ 677736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 678538307000. Starting simulation... +info: Entering event queue @ 678736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 679538307000. Starting simulation... +info: Entering event queue @ 679736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 680538307000. Starting simulation... +info: Entering event queue @ 680736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 681538307000. Starting simulation... +info: Entering event queue @ 681736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 682538307000. Starting simulation... +info: Entering event queue @ 682736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 683538307000. Starting simulation... +info: Entering event queue @ 683736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 684538307000. Starting simulation... +info: Entering event queue @ 684736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 685538307000. Starting simulation... +info: Entering event queue @ 685736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 686538307000. Starting simulation... +info: Entering event queue @ 686736157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 687538307000. Starting simulation... -info: Entering event queue @ 688274905000. Starting simulation... +info: Entering event queue @ 687736157000. Starting simulation... +info: Entering event queue @ 688472755000. Starting simulation... switching cpus -info: Entering event queue @ 688274907000. Starting simulation... +info: Entering event queue @ 688472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 689274907000. Starting simulation... +info: Entering event queue @ 689472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 690274907000. Starting simulation... +info: Entering event queue @ 690472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 691274907000. Starting simulation... +info: Entering event queue @ 691472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 692274907000. Starting simulation... +info: Entering event queue @ 692472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 693274907000. Starting simulation... +info: Entering event queue @ 693472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 694274907000. Starting simulation... +info: Entering event queue @ 694472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 695274907000. Starting simulation... +info: Entering event queue @ 695472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 696274907000. Starting simulation... +info: Entering event queue @ 696472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 697274907000. Starting simulation... +info: Entering event queue @ 697472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 698274907000. Starting simulation... +info: Entering event queue @ 698472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 699274907000. Starting simulation... +info: Entering event queue @ 699472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 700274907000. Starting simulation... +info: Entering event queue @ 700472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 701274907000. Starting simulation... +info: Entering event queue @ 701472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 702274907000. Starting simulation... +info: Entering event queue @ 702472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 703274907000. Starting simulation... +info: Entering event queue @ 703472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 704274907000. Starting simulation... +info: Entering event queue @ 704472757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 705274907000. Starting simulation... +info: Entering event queue @ 705472757000. Starting simulation... switching cpus -info: Entering event queue @ 705274908000. Starting simulation... +info: Entering event queue @ 705472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 706274908000. Starting simulation... +info: Entering event queue @ 706472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 707274908000. Starting simulation... +info: Entering event queue @ 707472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 708274908000. Starting simulation... +info: Entering event queue @ 708472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 709274908000. Starting simulation... +info: Entering event queue @ 709472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 710274908000. Starting simulation... +info: Entering event queue @ 710472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 711274908000. Starting simulation... +info: Entering event queue @ 711472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 712274908000. Starting simulation... +info: Entering event queue @ 712472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 713274908000. Starting simulation... +info: Entering event queue @ 713472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 714274908000. Starting simulation... +info: Entering event queue @ 714472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 715274908000. Starting simulation... +info: Entering event queue @ 715472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 716274908000. Starting simulation... +info: Entering event queue @ 716472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 717274908000. Starting simulation... +info: Entering event queue @ 717472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 718274908000. Starting simulation... +info: Entering event queue @ 718472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 719274908000. Starting simulation... +info: Entering event queue @ 719472764500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 720274908000. Starting simulation... -info: Entering event queue @ 721011196000. Starting simulation... +info: Entering event queue @ 720472764500. Starting simulation... +info: Entering event queue @ 721209334000. Starting simulation... switching cpus -info: Entering event queue @ 721011198000. Starting simulation... +info: Entering event queue @ 721209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 722011198000. Starting simulation... +info: Entering event queue @ 722209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 723011198000. Starting simulation... +info: Entering event queue @ 723209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 724011198000. Starting simulation... +info: Entering event queue @ 724209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 725011198000. Starting simulation... +info: Entering event queue @ 725209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 726011198000. Starting simulation... +info: Entering event queue @ 726209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 727011198000. Starting simulation... +info: Entering event queue @ 727209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 728011198000. Starting simulation... +info: Entering event queue @ 728209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 729011198000. Starting simulation... +info: Entering event queue @ 729209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 730011198000. Starting simulation... +info: Entering event queue @ 730209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 731011198000. Starting simulation... +info: Entering event queue @ 731209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 732011198000. Starting simulation... +info: Entering event queue @ 732209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 733011198000. Starting simulation... +info: Entering event queue @ 733209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 734011198000. Starting simulation... +info: Entering event queue @ 734209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 735011198000. Starting simulation... +info: Entering event queue @ 735209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 736011198000. Starting simulation... +info: Entering event queue @ 736209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 737011198000. Starting simulation... +info: Entering event queue @ 737209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 738011198000. Starting simulation... +info: Entering event queue @ 738209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 739011198000. Starting simulation... +info: Entering event queue @ 739209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 740011198000. Starting simulation... +info: Entering event queue @ 740209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 741011198000. Starting simulation... +info: Entering event queue @ 741209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 742011198000. Starting simulation... +info: Entering event queue @ 742209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 743011198000. Starting simulation... +info: Entering event queue @ 743209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 744011198000. Starting simulation... +info: Entering event queue @ 744209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 745011198000. Starting simulation... +info: Entering event queue @ 745209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 746011198000. Starting simulation... +info: Entering event queue @ 746209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 747011198000. Starting simulation... +info: Entering event queue @ 747209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 748011198000. Starting simulation... +info: Entering event queue @ 748209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 749011198000. Starting simulation... +info: Entering event queue @ 749209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 750011198000. Starting simulation... +info: Entering event queue @ 750209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 751011198000. Starting simulation... +info: Entering event queue @ 751209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 752011198000. Starting simulation... +info: Entering event queue @ 752209336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 753011198000. Starting simulation... -info: Entering event queue @ 753747337000. Starting simulation... +info: Entering event queue @ 753209336000. Starting simulation... +info: Entering event queue @ 753944939000. Starting simulation... switching cpus -info: Entering event queue @ 753747339000. Starting simulation... +info: Entering event queue @ 753944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 754747339000. Starting simulation... +info: Entering event queue @ 754944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 755747339000. Starting simulation... +info: Entering event queue @ 755944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 756747339000. Starting simulation... +info: Entering event queue @ 756944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 757747339000. Starting simulation... +info: Entering event queue @ 757944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 758747339000. Starting simulation... +info: Entering event queue @ 758944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 759747339000. Starting simulation... +info: Entering event queue @ 759944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 760747339000. Starting simulation... +info: Entering event queue @ 760944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 761747339000. Starting simulation... +info: Entering event queue @ 761944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 762747339000. Starting simulation... +info: Entering event queue @ 762944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 763747339000. Starting simulation... +info: Entering event queue @ 763944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 764747339000. Starting simulation... +info: Entering event queue @ 764944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 765747339000. Starting simulation... +info: Entering event queue @ 765944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 766747339000. Starting simulation... +info: Entering event queue @ 766944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 767747339000. Starting simulation... +info: Entering event queue @ 767944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 768747339000. Starting simulation... +info: Entering event queue @ 768944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 769747339000. Starting simulation... +info: Entering event queue @ 769944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 770747339000. Starting simulation... +info: Entering event queue @ 770944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 771747339000. Starting simulation... +info: Entering event queue @ 771944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 772747339000. Starting simulation... +info: Entering event queue @ 772944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 773747339000. Starting simulation... +info: Entering event queue @ 773944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 774747339000. Starting simulation... +info: Entering event queue @ 774944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 775747339000. Starting simulation... +info: Entering event queue @ 775944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 776747339000. Starting simulation... +info: Entering event queue @ 776944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 777747339000. Starting simulation... +info: Entering event queue @ 777944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 778747339000. Starting simulation... +info: Entering event queue @ 778944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 779747339000. Starting simulation... +info: Entering event queue @ 779944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 780747339000. Starting simulation... +info: Entering event queue @ 780944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 781747339000. Starting simulation... +info: Entering event queue @ 781944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 782747339000. Starting simulation... +info: Entering event queue @ 782944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 783747339000. Starting simulation... +info: Entering event queue @ 783944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 784747339000. Starting simulation... +info: Entering event queue @ 784944941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 785747339000. Starting simulation... -info: Entering event queue @ 786483631000. Starting simulation... +info: Entering event queue @ 785944941000. Starting simulation... +info: Entering event queue @ 786681539000. Starting simulation... switching cpus -info: Entering event queue @ 786483633000. Starting simulation... +info: Entering event queue @ 786681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 787483633000. Starting simulation... +info: Entering event queue @ 787681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 788483633000. Starting simulation... +info: Entering event queue @ 788681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 789483633000. Starting simulation... +info: Entering event queue @ 789681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 790483633000. Starting simulation... +info: Entering event queue @ 790681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 791483633000. Starting simulation... +info: Entering event queue @ 791681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 792483633000. Starting simulation... +info: Entering event queue @ 792681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 793483633000. Starting simulation... +info: Entering event queue @ 793681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 794483633000. Starting simulation... +info: Entering event queue @ 794681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 795483633000. Starting simulation... +info: Entering event queue @ 795681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 796483633000. Starting simulation... +info: Entering event queue @ 796681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 797483633000. Starting simulation... +info: Entering event queue @ 797681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 798483633000. Starting simulation... +info: Entering event queue @ 798681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 799483633000. Starting simulation... +info: Entering event queue @ 799681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 800483633000. Starting simulation... +info: Entering event queue @ 800681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 801483633000. Starting simulation... +info: Entering event queue @ 801681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 802483633000. Starting simulation... +info: Entering event queue @ 802681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 803483633000. Starting simulation... +info: Entering event queue @ 803681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 804483633000. Starting simulation... +info: Entering event queue @ 804681541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 805483633000. Starting simulation... +info: Entering event queue @ 805681541000. Starting simulation... switching cpus -info: Entering event queue @ 805483634000. Starting simulation... +info: Entering event queue @ 805681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 806483634000. Starting simulation... +info: Entering event queue @ 806681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 807483634000. Starting simulation... +info: Entering event queue @ 807681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 808483634000. Starting simulation... +info: Entering event queue @ 808681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 809483634000. Starting simulation... +info: Entering event queue @ 809681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 810483634000. Starting simulation... +info: Entering event queue @ 810681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 811483634000. Starting simulation... +info: Entering event queue @ 811681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 812483634000. Starting simulation... +info: Entering event queue @ 812681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 813483634000. Starting simulation... +info: Entering event queue @ 813681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 814483634000. Starting simulation... +info: Entering event queue @ 814681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 815483634000. Starting simulation... +info: Entering event queue @ 815681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 816483634000. Starting simulation... +info: Entering event queue @ 816681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 817483634000. Starting simulation... +info: Entering event queue @ 817681548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 818483634000. Starting simulation... -info: Entering event queue @ 819219772000. Starting simulation... +info: Entering event queue @ 818681548500. Starting simulation... +info: Entering event queue @ 819418118000. Starting simulation... switching cpus -info: Entering event queue @ 819219774000. Starting simulation... +info: Entering event queue @ 819418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 820219774000. Starting simulation... +info: Entering event queue @ 820418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 821219774000. Starting simulation... +info: Entering event queue @ 821418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 822219774000. Starting simulation... +info: Entering event queue @ 822418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 823219774000. Starting simulation... +info: Entering event queue @ 823418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 824219774000. Starting simulation... +info: Entering event queue @ 824418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 825219774000. Starting simulation... +info: Entering event queue @ 825418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 826219774000. Starting simulation... +info: Entering event queue @ 826418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 827219774000. Starting simulation... +info: Entering event queue @ 827418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 828219774000. Starting simulation... +info: Entering event queue @ 828418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 829219774000. Starting simulation... +info: Entering event queue @ 829418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 830219774000. Starting simulation... +info: Entering event queue @ 830418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 831219774000. Starting simulation... +info: Entering event queue @ 831418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 832219774000. Starting simulation... +info: Entering event queue @ 832418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 833219774000. Starting simulation... +info: Entering event queue @ 833418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 834219774000. Starting simulation... +info: Entering event queue @ 834418120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 835219774000. Starting simulation... +info: Entering event queue @ 835418120000. Starting simulation... switching cpus -info: Entering event queue @ 835219775000. Starting simulation... +info: Entering event queue @ 835418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 836219775000. Starting simulation... +info: Entering event queue @ 836418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 837219775000. Starting simulation... +info: Entering event queue @ 837418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 838219775000. Starting simulation... +info: Entering event queue @ 838418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 839219775000. Starting simulation... +info: Entering event queue @ 839418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 840219775000. Starting simulation... +info: Entering event queue @ 840418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 841219775000. Starting simulation... +info: Entering event queue @ 841418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 842219775000. Starting simulation... +info: Entering event queue @ 842418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 843219775000. Starting simulation... +info: Entering event queue @ 843418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 844219775000. Starting simulation... +info: Entering event queue @ 844418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 845219775000. Starting simulation... +info: Entering event queue @ 845418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 846219775000. Starting simulation... +info: Entering event queue @ 846418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 847219775000. Starting simulation... +info: Entering event queue @ 847418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 848219775000. Starting simulation... +info: Entering event queue @ 848418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 849219775000. Starting simulation... +info: Entering event queue @ 849418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 850219775000. Starting simulation... +info: Entering event queue @ 850418127500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 851219775000. Starting simulation... -info: Entering event queue @ 851956063000. Starting simulation... +info: Entering event queue @ 851418127500. Starting simulation... +info: Entering event queue @ 852153530000. Starting simulation... switching cpus -info: Entering event queue @ 851956065000. Starting simulation... +info: Entering event queue @ 852153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 852956065000. Starting simulation... +info: Entering event queue @ 853153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 853956065000. Starting simulation... +info: Entering event queue @ 854153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 854956065000. Starting simulation... +info: Entering event queue @ 855153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 855956065000. Starting simulation... +info: Entering event queue @ 856153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 856956065000. Starting simulation... +info: Entering event queue @ 857153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 857956065000. Starting simulation... +info: Entering event queue @ 858153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 858956065000. Starting simulation... +info: Entering event queue @ 859153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 859956065000. Starting simulation... +info: Entering event queue @ 860153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 860956065000. Starting simulation... +info: Entering event queue @ 861153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 861956065000. Starting simulation... +info: Entering event queue @ 862153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 862956065000. Starting simulation... +info: Entering event queue @ 863153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 863956065000. Starting simulation... +info: Entering event queue @ 864153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 864956065000. Starting simulation... +info: Entering event queue @ 865153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 865956065000. Starting simulation... +info: Entering event queue @ 866153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 866956065000. Starting simulation... +info: Entering event queue @ 867153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 867956065000. Starting simulation... +info: Entering event queue @ 868153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 868956065000. Starting simulation... +info: Entering event queue @ 869153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 869956065000. Starting simulation... +info: Entering event queue @ 870153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 870956065000. Starting simulation... +info: Entering event queue @ 871153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 871956065000. Starting simulation... +info: Entering event queue @ 872153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 872956065000. Starting simulation... +info: Entering event queue @ 873153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 873956065000. Starting simulation... +info: Entering event queue @ 874153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 874956065000. Starting simulation... +info: Entering event queue @ 875153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 875956065000. Starting simulation... +info: Entering event queue @ 876153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 876956065000. Starting simulation... +info: Entering event queue @ 877153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 877956065000. Starting simulation... +info: Entering event queue @ 878153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 878956065000. Starting simulation... +info: Entering event queue @ 879153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 879956065000. Starting simulation... +info: Entering event queue @ 880153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 880956065000. Starting simulation... +info: Entering event queue @ 881153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 881956065000. Starting simulation... +info: Entering event queue @ 882153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 882956065000. Starting simulation... +info: Entering event queue @ 883153532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 883956065000. Starting simulation... -info: Entering event queue @ 884692663000. Starting simulation... +info: Entering event queue @ 884153532000. Starting simulation... +info: Entering event queue @ 884890130000. Starting simulation... switching cpus -info: Entering event queue @ 884692665000. Starting simulation... +info: Entering event queue @ 884890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 885692665000. Starting simulation... +info: Entering event queue @ 885890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 886692665000. Starting simulation... +info: Entering event queue @ 886890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 887692665000. Starting simulation... +info: Entering event queue @ 887890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 888692665000. Starting simulation... +info: Entering event queue @ 888890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 889692665000. Starting simulation... +info: Entering event queue @ 889890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 890692665000. Starting simulation... +info: Entering event queue @ 890890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 891692665000. Starting simulation... +info: Entering event queue @ 891890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 892692665000. Starting simulation... +info: Entering event queue @ 892890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 893692665000. Starting simulation... +info: Entering event queue @ 893890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 894692665000. Starting simulation... +info: Entering event queue @ 894890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 895692665000. Starting simulation... +info: Entering event queue @ 895890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 896692665000. Starting simulation... +info: Entering event queue @ 896890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 897692665000. Starting simulation... +info: Entering event queue @ 897890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 898692665000. Starting simulation... +info: Entering event queue @ 898890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 899692665000. Starting simulation... +info: Entering event queue @ 899890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 900692665000. Starting simulation... +info: Entering event queue @ 900890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 901692665000. Starting simulation... +info: Entering event queue @ 901890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 902692665000. Starting simulation... +info: Entering event queue @ 902890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 903692665000. Starting simulation... +info: Entering event queue @ 903890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 904692665000. Starting simulation... +info: Entering event queue @ 904890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 905692665000. Starting simulation... +info: Entering event queue @ 905890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 906692665000. Starting simulation... +info: Entering event queue @ 906890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 907692665000. Starting simulation... +info: Entering event queue @ 907890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 908692665000. Starting simulation... +info: Entering event queue @ 908890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 909692665000. Starting simulation... +info: Entering event queue @ 909890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 910692665000. Starting simulation... +info: Entering event queue @ 910890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 911692665000. Starting simulation... +info: Entering event queue @ 911890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 912692665000. Starting simulation... +info: Entering event queue @ 912890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 913692665000. Starting simulation... +info: Entering event queue @ 913890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 914692665000. Starting simulation... +info: Entering event queue @ 914890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 915692665000. Starting simulation... +info: Entering event queue @ 915890132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 916692665000. Starting simulation... -info: Entering event queue @ 917428807000. Starting simulation... +info: Entering event queue @ 916890132000. Starting simulation... +info: Entering event queue @ 917626751000. Starting simulation... switching cpus -info: Entering event queue @ 917428809000. Starting simulation... +info: Entering event queue @ 917626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 918428809000. Starting simulation... +info: Entering event queue @ 918626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 919428809000. Starting simulation... +info: Entering event queue @ 919626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 920428809000. Starting simulation... +info: Entering event queue @ 920626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 921428809000. Starting simulation... +info: Entering event queue @ 921626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 922428809000. Starting simulation... +info: Entering event queue @ 922626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 923428809000. Starting simulation... +info: Entering event queue @ 923626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 924428809000. Starting simulation... +info: Entering event queue @ 924626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 925428809000. Starting simulation... +info: Entering event queue @ 925626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 926428809000. Starting simulation... +info: Entering event queue @ 926626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 927428809000. Starting simulation... +info: Entering event queue @ 927626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 928428809000. Starting simulation... +info: Entering event queue @ 928626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 929428809000. Starting simulation... +info: Entering event queue @ 929626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 930428809000. Starting simulation... +info: Entering event queue @ 930626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 931428809000. Starting simulation... +info: Entering event queue @ 931626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 932428809000. Starting simulation... +info: Entering event queue @ 932626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 933428809000. Starting simulation... +info: Entering event queue @ 933626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 934428809000. Starting simulation... +info: Entering event queue @ 934626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 935428809000. Starting simulation... +info: Entering event queue @ 935626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 936428809000. Starting simulation... +info: Entering event queue @ 936626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 937428809000. Starting simulation... +info: Entering event queue @ 937626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 938428809000. Starting simulation... +info: Entering event queue @ 938626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 939428809000. Starting simulation... +info: Entering event queue @ 939626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 940428809000. Starting simulation... +info: Entering event queue @ 940626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 941428809000. Starting simulation... +info: Entering event queue @ 941626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 942428809000. Starting simulation... +info: Entering event queue @ 942626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 943428809000. Starting simulation... +info: Entering event queue @ 943626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 944428809000. Starting simulation... +info: Entering event queue @ 944626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 945428809000. Starting simulation... +info: Entering event queue @ 945626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 946428809000. Starting simulation... +info: Entering event queue @ 946626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 947428809000. Starting simulation... +info: Entering event queue @ 947626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 948428809000. Starting simulation... +info: Entering event queue @ 948626753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 949428809000. Starting simulation... -info: Entering event queue @ 950164954000. Starting simulation... +info: Entering event queue @ 949626753000. Starting simulation... +info: Entering event queue @ 950363351000. Starting simulation... switching cpus -info: Entering event queue @ 950164956000. Starting simulation... +info: Entering event queue @ 950363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 951164956000. Starting simulation... +info: Entering event queue @ 951363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 952164956000. Starting simulation... +info: Entering event queue @ 952363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 953164956000. Starting simulation... +info: Entering event queue @ 953363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 954164956000. Starting simulation... +info: Entering event queue @ 954363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 955164956000. Starting simulation... +info: Entering event queue @ 955363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 956164956000. Starting simulation... +info: Entering event queue @ 956363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 957164956000. Starting simulation... +info: Entering event queue @ 957363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 958164956000. Starting simulation... +info: Entering event queue @ 958363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 959164956000. Starting simulation... +info: Entering event queue @ 959363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 960164956000. Starting simulation... +info: Entering event queue @ 960363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 961164956000. Starting simulation... +info: Entering event queue @ 961363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 962164956000. Starting simulation... +info: Entering event queue @ 962363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 963164956000. Starting simulation... +info: Entering event queue @ 963363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 964164956000. Starting simulation... +info: Entering event queue @ 964363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 965164956000. Starting simulation... +info: Entering event queue @ 965363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 966164956000. Starting simulation... +info: Entering event queue @ 966363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 967164956000. Starting simulation... +info: Entering event queue @ 967363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 968164956000. Starting simulation... +info: Entering event queue @ 968363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 969164956000. Starting simulation... +info: Entering event queue @ 969363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 970164956000. Starting simulation... +info: Entering event queue @ 970363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 971164956000. Starting simulation... +info: Entering event queue @ 971363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 972164956000. Starting simulation... +info: Entering event queue @ 972363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 973164956000. Starting simulation... +info: Entering event queue @ 973363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 974164956000. Starting simulation... +info: Entering event queue @ 974363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 975164956000. Starting simulation... +info: Entering event queue @ 975363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 976164956000. Starting simulation... +info: Entering event queue @ 976363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 977164956000. Starting simulation... +info: Entering event queue @ 977363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 978164956000. Starting simulation... +info: Entering event queue @ 978363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 979164956000. Starting simulation... +info: Entering event queue @ 979363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 980164956000. Starting simulation... +info: Entering event queue @ 980363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 981164956000. Starting simulation... +info: Entering event queue @ 981363353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 982164956000. Starting simulation... -info: Entering event queue @ 982901245000. Starting simulation... +info: Entering event queue @ 982363353000. Starting simulation... +info: Entering event queue @ 983098914000. Starting simulation... switching cpus -info: Entering event queue @ 982901247000. Starting simulation... +info: Entering event queue @ 983098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 983901247000. Starting simulation... +info: Entering event queue @ 984098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 984901247000. Starting simulation... +info: Entering event queue @ 985098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 985901247000. Starting simulation... +info: Entering event queue @ 986098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 986901247000. Starting simulation... +info: Entering event queue @ 987098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 987901247000. Starting simulation... +info: Entering event queue @ 988098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 988901247000. Starting simulation... +info: Entering event queue @ 989098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 989901247000. Starting simulation... +info: Entering event queue @ 990098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 990901247000. Starting simulation... +info: Entering event queue @ 991098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 991901247000. Starting simulation... +info: Entering event queue @ 992098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 992901247000. Starting simulation... +info: Entering event queue @ 993098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 993901247000. Starting simulation... +info: Entering event queue @ 994098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 994901247000. Starting simulation... +info: Entering event queue @ 995098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 995901247000. Starting simulation... +info: Entering event queue @ 996098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 996901247000. Starting simulation... +info: Entering event queue @ 997098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 997901247000. Starting simulation... +info: Entering event queue @ 998098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 998901247000. Starting simulation... +info: Entering event queue @ 999098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 999901247000. Starting simulation... +info: Entering event queue @ 1000098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1000901247000. Starting simulation... +info: Entering event queue @ 1001098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1001901247000. Starting simulation... +info: Entering event queue @ 1002098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1002901247000. Starting simulation... +info: Entering event queue @ 1003098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1003901247000. Starting simulation... +info: Entering event queue @ 1004098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1004901247000. Starting simulation... +info: Entering event queue @ 1005098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1005901247000. Starting simulation... +info: Entering event queue @ 1006098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1006901247000. Starting simulation... +info: Entering event queue @ 1007098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1007901247000. Starting simulation... +info: Entering event queue @ 1008098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1008901247000. Starting simulation... +info: Entering event queue @ 1009098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1009901247000. Starting simulation... +info: Entering event queue @ 1010098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1010901247000. Starting simulation... +info: Entering event queue @ 1011098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1011901247000. Starting simulation... +info: Entering event queue @ 1012098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1012901247000. Starting simulation... +info: Entering event queue @ 1013098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1013901247000. Starting simulation... +info: Entering event queue @ 1014098916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1014901247000. Starting simulation... -info: Entering event queue @ 1015637389000. Starting simulation... +info: Entering event queue @ 1015098916000. Starting simulation... +info: Entering event queue @ 1015835514000. Starting simulation... switching cpus -info: Entering event queue @ 1015637391000. Starting simulation... +info: Entering event queue @ 1015835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1016637391000. Starting simulation... +info: Entering event queue @ 1016835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1017637391000. Starting simulation... +info: Entering event queue @ 1017835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1018637391000. Starting simulation... +info: Entering event queue @ 1018835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1019637391000. Starting simulation... +info: Entering event queue @ 1019835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1020637391000. Starting simulation... +info: Entering event queue @ 1020835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1021637391000. Starting simulation... +info: Entering event queue @ 1021835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1022637391000. Starting simulation... +info: Entering event queue @ 1022835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1023637391000. Starting simulation... +info: Entering event queue @ 1023835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1024637391000. Starting simulation... +info: Entering event queue @ 1024835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1025637391000. Starting simulation... +info: Entering event queue @ 1025835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1026637391000. Starting simulation... +info: Entering event queue @ 1026835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1027637391000. Starting simulation... +info: Entering event queue @ 1027835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1028637391000. Starting simulation... +info: Entering event queue @ 1028835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1029637391000. Starting simulation... +info: Entering event queue @ 1029835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1030637391000. Starting simulation... +info: Entering event queue @ 1030835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1031637391000. Starting simulation... +info: Entering event queue @ 1031835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1032637391000. Starting simulation... +info: Entering event queue @ 1032835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1033637391000. Starting simulation... +info: Entering event queue @ 1033835516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1034637391000. Starting simulation... +info: Entering event queue @ 1034835516000. Starting simulation... switching cpus -info: Entering event queue @ 1034637391500. Starting simulation... +info: Entering event queue @ 1034835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1035637391500. Starting simulation... switching cpus -info: Entering event queue @ 1035637392500. Starting simulation... +info: Entering event queue @ 1035835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1036637392500. Starting simulation... +info: Entering event queue @ 1036835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1037637392500. Starting simulation... +info: Entering event queue @ 1037835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1038637392500. Starting simulation... +info: Entering event queue @ 1038835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1039637392500. Starting simulation... +info: Entering event queue @ 1039835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1040637392500. Starting simulation... +info: Entering event queue @ 1040835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1041637392500. Starting simulation... +info: Entering event queue @ 1041835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1042637392500. Starting simulation... +info: Entering event queue @ 1042835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1043637392500. Starting simulation... +info: Entering event queue @ 1043835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1044637392500. Starting simulation... +info: Entering event queue @ 1044835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1045637392500. Starting simulation... +info: Entering event queue @ 1045835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1046637392500. Starting simulation... +info: Entering event queue @ 1046835523500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1047637392500. Starting simulation... -info: Entering event queue @ 1048373680000. Starting simulation... +info: Entering event queue @ 1047835523500. Starting simulation... +info: Entering event queue @ 1048572135000. Starting simulation... switching cpus -info: Entering event queue @ 1048373682000. Starting simulation... +info: Entering event queue @ 1048572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1049373682000. Starting simulation... +info: Entering event queue @ 1049572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1050373682000. Starting simulation... +info: Entering event queue @ 1050572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1051373682000. Starting simulation... +info: Entering event queue @ 1051572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1052373682000. Starting simulation... +info: Entering event queue @ 1052572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1053373682000. Starting simulation... +info: Entering event queue @ 1053572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1054373682000. Starting simulation... +info: Entering event queue @ 1054572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1055373682000. Starting simulation... +info: Entering event queue @ 1055572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1056373682000. Starting simulation... +info: Entering event queue @ 1056572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1057373682000. Starting simulation... +info: Entering event queue @ 1057572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1058373682000. Starting simulation... +info: Entering event queue @ 1058572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1059373682000. Starting simulation... +info: Entering event queue @ 1059572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1060373682000. Starting simulation... +info: Entering event queue @ 1060572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1061373682000. Starting simulation... +info: Entering event queue @ 1061572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1062373682000. Starting simulation... +info: Entering event queue @ 1062572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1063373682000. Starting simulation... +info: Entering event queue @ 1063572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1064373682000. Starting simulation... +info: Entering event queue @ 1064572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1065373682000. Starting simulation... +info: Entering event queue @ 1065572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1066373682000. Starting simulation... +info: Entering event queue @ 1066572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1067373682000. Starting simulation... +info: Entering event queue @ 1067572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1068373682000. Starting simulation... +info: Entering event queue @ 1068572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1069373682000. Starting simulation... +info: Entering event queue @ 1069572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1070373682000. Starting simulation... +info: Entering event queue @ 1070572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1071373682000. Starting simulation... +info: Entering event queue @ 1071572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1072373682000. Starting simulation... +info: Entering event queue @ 1072572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1073373682000. Starting simulation... +info: Entering event queue @ 1073572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1074373682000. Starting simulation... +info: Entering event queue @ 1074572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1075373682000. Starting simulation... +info: Entering event queue @ 1075572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1076373682000. Starting simulation... +info: Entering event queue @ 1076572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1077373682000. Starting simulation... +info: Entering event queue @ 1077572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1078373682000. Starting simulation... +info: Entering event queue @ 1078572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1079373682000. Starting simulation... +info: Entering event queue @ 1079572137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1080373682000. Starting simulation... -info: Entering event queue @ 1081109821000. Starting simulation... +info: Entering event queue @ 1080572137000. Starting simulation... +info: Entering event queue @ 1081307547000. Starting simulation... switching cpus -info: Entering event queue @ 1081109823000. Starting simulation... +info: Entering event queue @ 1081307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1082109823000. Starting simulation... +info: Entering event queue @ 1082307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1083109823000. Starting simulation... +info: Entering event queue @ 1083307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1084109823000. Starting simulation... +info: Entering event queue @ 1084307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1085109823000. Starting simulation... +info: Entering event queue @ 1085307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1086109823000. Starting simulation... +info: Entering event queue @ 1086307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1087109823000. Starting simulation... +info: Entering event queue @ 1087307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1088109823000. Starting simulation... +info: Entering event queue @ 1088307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1089109823000. Starting simulation... +info: Entering event queue @ 1089307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1090109823000. Starting simulation... +info: Entering event queue @ 1090307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1091109823000. Starting simulation... +info: Entering event queue @ 1091307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1092109823000. Starting simulation... +info: Entering event queue @ 1092307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1093109823000. Starting simulation... +info: Entering event queue @ 1093307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1094109823000. Starting simulation... +info: Entering event queue @ 1094307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1095109823000. Starting simulation... +info: Entering event queue @ 1095307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1096109823000. Starting simulation... +info: Entering event queue @ 1096307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1097109823000. Starting simulation... +info: Entering event queue @ 1097307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1098109823000. Starting simulation... +info: Entering event queue @ 1098307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1099109823000. Starting simulation... +info: Entering event queue @ 1099307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1100109823000. Starting simulation... +info: Entering event queue @ 1100307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1101109823000. Starting simulation... +info: Entering event queue @ 1101307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1102109823000. Starting simulation... +info: Entering event queue @ 1102307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1103109823000. Starting simulation... +info: Entering event queue @ 1103307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1104109823000. Starting simulation... +info: Entering event queue @ 1104307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1105109823000. Starting simulation... +info: Entering event queue @ 1105307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1106109823000. Starting simulation... +info: Entering event queue @ 1106307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1107109823000. Starting simulation... +info: Entering event queue @ 1107307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1108109823000. Starting simulation... +info: Entering event queue @ 1108307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1109109823000. Starting simulation... +info: Entering event queue @ 1109307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1110109823000. Starting simulation... +info: Entering event queue @ 1110307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1111109823000. Starting simulation... +info: Entering event queue @ 1111307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1112109823000. Starting simulation... +info: Entering event queue @ 1112307549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1113109823000. Starting simulation... -info: Entering event queue @ 1113846115000. Starting simulation... +info: Entering event queue @ 1113307549000. Starting simulation... +info: Entering event queue @ 1114044147000. Starting simulation... switching cpus -info: Entering event queue @ 1113846117000. Starting simulation... +info: Entering event queue @ 1114044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1114846117000. Starting simulation... +info: Entering event queue @ 1115044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1115846117000. Starting simulation... +info: Entering event queue @ 1116044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1116846117000. Starting simulation... +info: Entering event queue @ 1117044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1117846117000. Starting simulation... +info: Entering event queue @ 1118044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1118846117000. Starting simulation... +info: Entering event queue @ 1119044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1119846117000. Starting simulation... +info: Entering event queue @ 1120044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1120846117000. Starting simulation... +info: Entering event queue @ 1121044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1121846117000. Starting simulation... +info: Entering event queue @ 1122044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1122846117000. Starting simulation... +info: Entering event queue @ 1123044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1123846117000. Starting simulation... +info: Entering event queue @ 1124044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1124846117000. Starting simulation... +info: Entering event queue @ 1125044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1125846117000. Starting simulation... +info: Entering event queue @ 1126044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1126846117000. Starting simulation... +info: Entering event queue @ 1127044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1127846117000. Starting simulation... +info: Entering event queue @ 1128044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1128846117000. Starting simulation... +info: Entering event queue @ 1129044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1129846117000. Starting simulation... +info: Entering event queue @ 1130044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1130846117000. Starting simulation... +info: Entering event queue @ 1131044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1131846117000. Starting simulation... +info: Entering event queue @ 1132044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1132846117000. Starting simulation... +info: Entering event queue @ 1133044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1133846117000. Starting simulation... +info: Entering event queue @ 1134044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1134846117000. Starting simulation... +info: Entering event queue @ 1135044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1135846117000. Starting simulation... +info: Entering event queue @ 1136044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1136846117000. Starting simulation... +info: Entering event queue @ 1137044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1137846117000. Starting simulation... +info: Entering event queue @ 1138044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1138846117000. Starting simulation... +info: Entering event queue @ 1139044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1139846117000. Starting simulation... +info: Entering event queue @ 1140044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1140846117000. Starting simulation... +info: Entering event queue @ 1141044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1141846117000. Starting simulation... +info: Entering event queue @ 1142044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1142846117000. Starting simulation... +info: Entering event queue @ 1143044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1143846117000. Starting simulation... +info: Entering event queue @ 1144044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1144846117000. Starting simulation... +info: Entering event queue @ 1145044149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1145846117000. Starting simulation... -info: Entering event queue @ 1146582256000. Starting simulation... +info: Entering event queue @ 1146044149000. Starting simulation... +info: Entering event queue @ 1146780726000. Starting simulation... switching cpus -info: Entering event queue @ 1146582258000. Starting simulation... +info: Entering event queue @ 1146780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1147582258000. Starting simulation... +info: Entering event queue @ 1147780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1148582258000. Starting simulation... +info: Entering event queue @ 1148780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1149582258000. Starting simulation... +info: Entering event queue @ 1149780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1150582258000. Starting simulation... +info: Entering event queue @ 1150780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1151582258000. Starting simulation... +info: Entering event queue @ 1151780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1152582258000. Starting simulation... +info: Entering event queue @ 1152780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1153582258000. Starting simulation... +info: Entering event queue @ 1153780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1154582258000. Starting simulation... +info: Entering event queue @ 1154780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1155582258000. Starting simulation... +info: Entering event queue @ 1155780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1156582258000. Starting simulation... +info: Entering event queue @ 1156780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1157582258000. Starting simulation... +info: Entering event queue @ 1157780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1158582258000. Starting simulation... +info: Entering event queue @ 1158780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1159582258000. Starting simulation... +info: Entering event queue @ 1159780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1160582258000. Starting simulation... +info: Entering event queue @ 1160780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1161582258000. Starting simulation... +info: Entering event queue @ 1161780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1162582258000. Starting simulation... +info: Entering event queue @ 1162780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1163582258000. Starting simulation... +info: Entering event queue @ 1163780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1164582258000. Starting simulation... +info: Entering event queue @ 1164780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1165582258000. Starting simulation... +info: Entering event queue @ 1165780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1166582258000. Starting simulation... +info: Entering event queue @ 1166780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1167582258000. Starting simulation... +info: Entering event queue @ 1167780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1168582258000. Starting simulation... +info: Entering event queue @ 1168780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1169582258000. Starting simulation... +info: Entering event queue @ 1169780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1170582258000. Starting simulation... +info: Entering event queue @ 1170780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1171582258000. Starting simulation... +info: Entering event queue @ 1171780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1172582258000. Starting simulation... +info: Entering event queue @ 1172780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1173582258000. Starting simulation... +info: Entering event queue @ 1173780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1174582258000. Starting simulation... +info: Entering event queue @ 1174780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1175582258000. Starting simulation... +info: Entering event queue @ 1175780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1176582258000. Starting simulation... +info: Entering event queue @ 1176780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1177582258000. Starting simulation... +info: Entering event queue @ 1177780728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1178582258000. Starting simulation... -info: Entering event queue @ 1179318856000. Starting simulation... +info: Entering event queue @ 1178780728000. Starting simulation... +info: Entering event queue @ 1179516138000. Starting simulation... switching cpus -info: Entering event queue @ 1179318858000. Starting simulation... +info: Entering event queue @ 1179516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1180318858000. Starting simulation... +info: Entering event queue @ 1180516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1181318858000. Starting simulation... +info: Entering event queue @ 1181516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1182318858000. Starting simulation... +info: Entering event queue @ 1182516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1183318858000. Starting simulation... +info: Entering event queue @ 1183516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1184318858000. Starting simulation... +info: Entering event queue @ 1184516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1185318858000. Starting simulation... +info: Entering event queue @ 1185516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1186318858000. Starting simulation... +info: Entering event queue @ 1186516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1187318858000. Starting simulation... +info: Entering event queue @ 1187516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1188318858000. Starting simulation... +info: Entering event queue @ 1188516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1189318858000. Starting simulation... +info: Entering event queue @ 1189516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1190318858000. Starting simulation... +info: Entering event queue @ 1190516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1191318858000. Starting simulation... +info: Entering event queue @ 1191516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1192318858000. Starting simulation... +info: Entering event queue @ 1192516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1193318858000. Starting simulation... +info: Entering event queue @ 1193516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1194318858000. Starting simulation... +info: Entering event queue @ 1194516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1195318858000. Starting simulation... +info: Entering event queue @ 1195516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1196318858000. Starting simulation... +info: Entering event queue @ 1196516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1197318858000. Starting simulation... +info: Entering event queue @ 1197516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1198318858000. Starting simulation... +info: Entering event queue @ 1198516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1199318858000. Starting simulation... +info: Entering event queue @ 1199516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1200318858000. Starting simulation... +info: Entering event queue @ 1200516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1201318858000. Starting simulation... +info: Entering event queue @ 1201516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1202318858000. Starting simulation... +info: Entering event queue @ 1202516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1203318858000. Starting simulation... +info: Entering event queue @ 1203516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1204318858000. Starting simulation... +info: Entering event queue @ 1204516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1205318858000. Starting simulation... +info: Entering event queue @ 1205516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1206318858000. Starting simulation... +info: Entering event queue @ 1206516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1207318858000. Starting simulation... +info: Entering event queue @ 1207516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1208318858000. Starting simulation... +info: Entering event queue @ 1208516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1209318858000. Starting simulation... +info: Entering event queue @ 1209516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1210318858000. Starting simulation... +info: Entering event queue @ 1210516140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1211318858000. Starting simulation... -info: Entering event queue @ 1212055147000. Starting simulation... +info: Entering event queue @ 1211516140000. Starting simulation... +info: Entering event queue @ 1212252738000. Starting simulation... switching cpus -info: Entering event queue @ 1212055149000. Starting simulation... +info: Entering event queue @ 1212252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1213055149000. Starting simulation... +info: Entering event queue @ 1213252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1214055149000. Starting simulation... +info: Entering event queue @ 1214252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1215055149000. Starting simulation... +info: Entering event queue @ 1215252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1216055149000. Starting simulation... +info: Entering event queue @ 1216252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1217055149000. Starting simulation... +info: Entering event queue @ 1217252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1218055149000. Starting simulation... +info: Entering event queue @ 1218252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1219055149000. Starting simulation... +info: Entering event queue @ 1219252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1220055149000. Starting simulation... +info: Entering event queue @ 1220252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1221055149000. Starting simulation... +info: Entering event queue @ 1221252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1222055149000. Starting simulation... +info: Entering event queue @ 1222252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1223055149000. Starting simulation... +info: Entering event queue @ 1223252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1224055149000. Starting simulation... +info: Entering event queue @ 1224252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1225055149000. Starting simulation... +info: Entering event queue @ 1225252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1226055149000. Starting simulation... +info: Entering event queue @ 1226252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1227055149000. Starting simulation... +info: Entering event queue @ 1227252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1228055149000. Starting simulation... +info: Entering event queue @ 1228252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1229055149000. Starting simulation... +info: Entering event queue @ 1229252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1230055149000. Starting simulation... +info: Entering event queue @ 1230252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1231055149000. Starting simulation... +info: Entering event queue @ 1231252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1232055149000. Starting simulation... +info: Entering event queue @ 1232252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1233055149000. Starting simulation... +info: Entering event queue @ 1233252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1234055149000. Starting simulation... +info: Entering event queue @ 1234252740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1235055149000. Starting simulation... +info: Entering event queue @ 1235252740000. Starting simulation... switching cpus -info: Entering event queue @ 1235055150000. Starting simulation... +info: Entering event queue @ 1235252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1236055150000. Starting simulation... +info: Entering event queue @ 1236252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1237055150000. Starting simulation... +info: Entering event queue @ 1237252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1238055150000. Starting simulation... +info: Entering event queue @ 1238252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1239055150000. Starting simulation... +info: Entering event queue @ 1239252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1240055150000. Starting simulation... +info: Entering event queue @ 1240252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1241055150000. Starting simulation... +info: Entering event queue @ 1241252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1242055150000. Starting simulation... +info: Entering event queue @ 1242252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1243055150000. Starting simulation... +info: Entering event queue @ 1243252747500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1244055150000. Starting simulation... -info: Entering event queue @ 1244791291000. Starting simulation... +info: Entering event queue @ 1244252747500. Starting simulation... +info: Entering event queue @ 1244989355000. Starting simulation... switching cpus -info: Entering event queue @ 1244791293000. Starting simulation... +info: Entering event queue @ 1244989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1245791293000. Starting simulation... +info: Entering event queue @ 1245989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1246791293000. Starting simulation... +info: Entering event queue @ 1246989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1247791293000. Starting simulation... +info: Entering event queue @ 1247989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1248791293000. Starting simulation... +info: Entering event queue @ 1248989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1249791293000. Starting simulation... +info: Entering event queue @ 1249989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1250791293000. Starting simulation... +info: Entering event queue @ 1250989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1251791293000. Starting simulation... +info: Entering event queue @ 1251989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1252791293000. Starting simulation... +info: Entering event queue @ 1252989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1253791293000. Starting simulation... +info: Entering event queue @ 1253989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1254791293000. Starting simulation... +info: Entering event queue @ 1254989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1255791293000. Starting simulation... +info: Entering event queue @ 1255989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1256791293000. Starting simulation... +info: Entering event queue @ 1256989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1257791293000. Starting simulation... +info: Entering event queue @ 1257989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1258791293000. Starting simulation... +info: Entering event queue @ 1258989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1259791293000. Starting simulation... +info: Entering event queue @ 1259989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1260791293000. Starting simulation... +info: Entering event queue @ 1260989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1261791293000. Starting simulation... +info: Entering event queue @ 1261989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1262791293000. Starting simulation... +info: Entering event queue @ 1262989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1263791293000. Starting simulation... +info: Entering event queue @ 1263989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1264791293000. Starting simulation... +info: Entering event queue @ 1264989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1265791293000. Starting simulation... +info: Entering event queue @ 1265989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1266791293000. Starting simulation... +info: Entering event queue @ 1266989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1267791293000. Starting simulation... +info: Entering event queue @ 1267989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1268791293000. Starting simulation... +info: Entering event queue @ 1268989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1269791293000. Starting simulation... +info: Entering event queue @ 1269989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1270791293000. Starting simulation... +info: Entering event queue @ 1270989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1271791293000. Starting simulation... +info: Entering event queue @ 1271989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1272791293000. Starting simulation... +info: Entering event queue @ 1272989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1273791293000. Starting simulation... +info: Entering event queue @ 1273989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1274791293000. Starting simulation... +info: Entering event queue @ 1274989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1275791293000. Starting simulation... +info: Entering event queue @ 1275989357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1276791293000. Starting simulation... -info: Entering event queue @ 1277527582000. Starting simulation... +info: Entering event queue @ 1276989357000. Starting simulation... +info: Entering event queue @ 1277724922000. Starting simulation... switching cpus -info: Entering event queue @ 1277527584000. Starting simulation... +info: Entering event queue @ 1277724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1278527584000. Starting simulation... +info: Entering event queue @ 1278724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1279527584000. Starting simulation... +info: Entering event queue @ 1279724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1280527584000. Starting simulation... +info: Entering event queue @ 1280724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1281527584000. Starting simulation... +info: Entering event queue @ 1281724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1282527584000. Starting simulation... +info: Entering event queue @ 1282724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1283527584000. Starting simulation... +info: Entering event queue @ 1283724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1284527584000. Starting simulation... +info: Entering event queue @ 1284724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1285527584000. Starting simulation... +info: Entering event queue @ 1285724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1286527584000. Starting simulation... +info: Entering event queue @ 1286724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1287527584000. Starting simulation... +info: Entering event queue @ 1287724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1288527584000. Starting simulation... +info: Entering event queue @ 1288724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1289527584000. Starting simulation... +info: Entering event queue @ 1289724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1290527584000. Starting simulation... +info: Entering event queue @ 1290724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1291527584000. Starting simulation... +info: Entering event queue @ 1291724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1292527584000. Starting simulation... +info: Entering event queue @ 1292724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1293527584000. Starting simulation... +info: Entering event queue @ 1293724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1294527584000. Starting simulation... +info: Entering event queue @ 1294724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1295527584000. Starting simulation... +info: Entering event queue @ 1295724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1296527584000. Starting simulation... +info: Entering event queue @ 1296724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1297527584000. Starting simulation... +info: Entering event queue @ 1297724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1298527584000. Starting simulation... +info: Entering event queue @ 1298724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1299527584000. Starting simulation... +info: Entering event queue @ 1299724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1300527584000. Starting simulation... +info: Entering event queue @ 1300724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1301527584000. Starting simulation... +info: Entering event queue @ 1301724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1302527584000. Starting simulation... +info: Entering event queue @ 1302724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1303527584000. Starting simulation... +info: Entering event queue @ 1303724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1304527584000. Starting simulation... +info: Entering event queue @ 1304724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1305527584000. Starting simulation... +info: Entering event queue @ 1305724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1306527584000. Starting simulation... +info: Entering event queue @ 1306724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1307527584000. Starting simulation... +info: Entering event queue @ 1307724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1308527584000. Starting simulation... +info: Entering event queue @ 1308724924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1309527584000. Starting simulation... -info: Entering event queue @ 1310263726000. Starting simulation... +info: Entering event queue @ 1309724924000. Starting simulation... +info: Entering event queue @ 1310461522000. Starting simulation... switching cpus -info: Entering event queue @ 1310263728000. Starting simulation... +info: Entering event queue @ 1310461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1311263728000. Starting simulation... +info: Entering event queue @ 1311461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1312263728000. Starting simulation... +info: Entering event queue @ 1312461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1313263728000. Starting simulation... +info: Entering event queue @ 1313461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1314263728000. Starting simulation... +info: Entering event queue @ 1314461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1315263728000. Starting simulation... +info: Entering event queue @ 1315461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1316263728000. Starting simulation... +info: Entering event queue @ 1316461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1317263728000. Starting simulation... +info: Entering event queue @ 1317461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1318263728000. Starting simulation... +info: Entering event queue @ 1318461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1319263728000. Starting simulation... +info: Entering event queue @ 1319461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1320263728000. Starting simulation... +info: Entering event queue @ 1320461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1321263728000. Starting simulation... +info: Entering event queue @ 1321461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1322263728000. Starting simulation... +info: Entering event queue @ 1322461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1323263728000. Starting simulation... +info: Entering event queue @ 1323461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1324263728000. Starting simulation... +info: Entering event queue @ 1324461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1325263728000. Starting simulation... +info: Entering event queue @ 1325461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1326263728000. Starting simulation... +info: Entering event queue @ 1326461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1327263728000. Starting simulation... +info: Entering event queue @ 1327461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1328263728000. Starting simulation... +info: Entering event queue @ 1328461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1329263728000. Starting simulation... +info: Entering event queue @ 1329461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1330263728000. Starting simulation... +info: Entering event queue @ 1330461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1331263728000. Starting simulation... +info: Entering event queue @ 1331461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1332263728000. Starting simulation... +info: Entering event queue @ 1332461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1333263728000. Starting simulation... +info: Entering event queue @ 1333461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1334263728000. Starting simulation... +info: Entering event queue @ 1334461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1335263728000. Starting simulation... +info: Entering event queue @ 1335461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1336263728000. Starting simulation... +info: Entering event queue @ 1336461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1337263728000. Starting simulation... +info: Entering event queue @ 1337461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1338263728000. Starting simulation... +info: Entering event queue @ 1338461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1339263728000. Starting simulation... +info: Entering event queue @ 1339461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1340263728000. Starting simulation... +info: Entering event queue @ 1340461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1341263728000. Starting simulation... +info: Entering event queue @ 1341461524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1342263728000. Starting simulation... -info: Entering event queue @ 1342999873000. Starting simulation... +info: Entering event queue @ 1342461524000. Starting simulation... +info: Entering event queue @ 1343198143000. Starting simulation... switching cpus -info: Entering event queue @ 1342999875000. Starting simulation... +info: Entering event queue @ 1343198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1343999875000. Starting simulation... +info: Entering event queue @ 1344198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1344999875000. Starting simulation... +info: Entering event queue @ 1345198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1345999875000. Starting simulation... +info: Entering event queue @ 1346198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1346999875000. Starting simulation... +info: Entering event queue @ 1347198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1347999875000. Starting simulation... +info: Entering event queue @ 1348198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1348999875000. Starting simulation... +info: Entering event queue @ 1349198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1349999875000. Starting simulation... +info: Entering event queue @ 1350198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1350999875000. Starting simulation... +info: Entering event queue @ 1351198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1351999875000. Starting simulation... +info: Entering event queue @ 1352198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1352999875000. Starting simulation... +info: Entering event queue @ 1353198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1353999875000. Starting simulation... +info: Entering event queue @ 1354198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1354999875000. Starting simulation... +info: Entering event queue @ 1355198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1355999875000. Starting simulation... +info: Entering event queue @ 1356198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1356999875000. Starting simulation... +info: Entering event queue @ 1357198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1357999875000. Starting simulation... +info: Entering event queue @ 1358198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1358999875000. Starting simulation... +info: Entering event queue @ 1359198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1359999875000. Starting simulation... +info: Entering event queue @ 1360198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1360999875000. Starting simulation... +info: Entering event queue @ 1361198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1361999875000. Starting simulation... +info: Entering event queue @ 1362198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1362999875000. Starting simulation... +info: Entering event queue @ 1363198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1363999875000. Starting simulation... +info: Entering event queue @ 1364198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1364999875000. Starting simulation... +info: Entering event queue @ 1365198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1365999875000. Starting simulation... +info: Entering event queue @ 1366198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1366999875000. Starting simulation... +info: Entering event queue @ 1367198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1367999875000. Starting simulation... +info: Entering event queue @ 1368198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1368999875000. Starting simulation... +info: Entering event queue @ 1369198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1369999875000. Starting simulation... +info: Entering event queue @ 1370198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1370999875000. Starting simulation... +info: Entering event queue @ 1371198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1371999875000. Starting simulation... +info: Entering event queue @ 1372198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1372999875000. Starting simulation... +info: Entering event queue @ 1373198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1373999875000. Starting simulation... +info: Entering event queue @ 1374198145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1374999875000. Starting simulation... -info: Entering event queue @ 1375736473000. Starting simulation... +info: Entering event queue @ 1375198145000. Starting simulation... +info: Entering event queue @ 1375934743000. Starting simulation... switching cpus -info: Entering event queue @ 1375736475000. Starting simulation... +info: Entering event queue @ 1375934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1376736475000. Starting simulation... +info: Entering event queue @ 1376934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1377736475000. Starting simulation... +info: Entering event queue @ 1377934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1378736475000. Starting simulation... +info: Entering event queue @ 1378934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1379736475000. Starting simulation... +info: Entering event queue @ 1379934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1380736475000. Starting simulation... +info: Entering event queue @ 1380934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1381736475000. Starting simulation... +info: Entering event queue @ 1381934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1382736475000. Starting simulation... +info: Entering event queue @ 1382934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1383736475000. Starting simulation... +info: Entering event queue @ 1383934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1384736475000. Starting simulation... +info: Entering event queue @ 1384934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1385736475000. Starting simulation... +info: Entering event queue @ 1385934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1386736475000. Starting simulation... +info: Entering event queue @ 1386934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1387736475000. Starting simulation... +info: Entering event queue @ 1387934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1388736475000. Starting simulation... +info: Entering event queue @ 1388934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1389736475000. Starting simulation... +info: Entering event queue @ 1389934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1390736475000. Starting simulation... +info: Entering event queue @ 1390934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1391736475000. Starting simulation... +info: Entering event queue @ 1391934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1392736475000. Starting simulation... +info: Entering event queue @ 1392934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1393736475000. Starting simulation... +info: Entering event queue @ 1393934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1394736475000. Starting simulation... +info: Entering event queue @ 1394934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1395736475000. Starting simulation... +info: Entering event queue @ 1395934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1396736475000. Starting simulation... +info: Entering event queue @ 1396934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1397736475000. Starting simulation... +info: Entering event queue @ 1397934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1398736475000. Starting simulation... +info: Entering event queue @ 1398934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1399736475000. Starting simulation... +info: Entering event queue @ 1399934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1400736475000. Starting simulation... +info: Entering event queue @ 1400934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1401736475000. Starting simulation... +info: Entering event queue @ 1401934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1402736475000. Starting simulation... +info: Entering event queue @ 1402934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1403736475000. Starting simulation... +info: Entering event queue @ 1403934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1404736475000. Starting simulation... +info: Entering event queue @ 1404934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1405736475000. Starting simulation... +info: Entering event queue @ 1405934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1406736475000. Starting simulation... +info: Entering event queue @ 1406934745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1407736475000. Starting simulation... -info: Entering event queue @ 1408472305000. Starting simulation... +info: Entering event queue @ 1407934745000. Starting simulation... +info: Entering event queue @ 1408670155000. Starting simulation... switching cpus -info: Entering event queue @ 1408472307000. Starting simulation... +info: Entering event queue @ 1408670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1409472307000. Starting simulation... +info: Entering event queue @ 1409670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1410472307000. Starting simulation... +info: Entering event queue @ 1410670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1411472307000. Starting simulation... +info: Entering event queue @ 1411670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1412472307000. Starting simulation... +info: Entering event queue @ 1412670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1413472307000. Starting simulation... +info: Entering event queue @ 1413670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1414472307000. Starting simulation... +info: Entering event queue @ 1414670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1415472307000. Starting simulation... +info: Entering event queue @ 1415670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1416472307000. Starting simulation... +info: Entering event queue @ 1416670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1417472307000. Starting simulation... +info: Entering event queue @ 1417670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1418472307000. Starting simulation... +info: Entering event queue @ 1418670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1419472307000. Starting simulation... +info: Entering event queue @ 1419670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1420472307000. Starting simulation... +info: Entering event queue @ 1420670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1421472307000. Starting simulation... +info: Entering event queue @ 1421670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1422472307000. Starting simulation... +info: Entering event queue @ 1422670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1423472307000. Starting simulation... +info: Entering event queue @ 1423670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1424472307000. Starting simulation... +info: Entering event queue @ 1424670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1425472307000. Starting simulation... +info: Entering event queue @ 1425670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1426472307000. Starting simulation... +info: Entering event queue @ 1426670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1427472307000. Starting simulation... +info: Entering event queue @ 1427670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1428472307000. Starting simulation... +info: Entering event queue @ 1428670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1429472307000. Starting simulation... +info: Entering event queue @ 1429670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1430472307000. Starting simulation... +info: Entering event queue @ 1430670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1431472307000. Starting simulation... +info: Entering event queue @ 1431670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1432472307000. Starting simulation... +info: Entering event queue @ 1432670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1433472307000. Starting simulation... +info: Entering event queue @ 1433670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1434472307000. Starting simulation... +info: Entering event queue @ 1434670157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1435472307000. Starting simulation... +info: Entering event queue @ 1435670157000. Starting simulation... switching cpus -info: Entering event queue @ 1435472308000. Starting simulation... +info: Entering event queue @ 1435670164500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1436472308000. Starting simulation... +info: Entering event queue @ 1436670164500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1437472308000. Starting simulation... +info: Entering event queue @ 1437670164500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1438472308000. Starting simulation... +info: Entering event queue @ 1438670164500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1439472308000. Starting simulation... +info: Entering event queue @ 1439670164500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1440472308000. Starting simulation... -info: Entering event queue @ 1441208905000. Starting simulation... +info: Entering event queue @ 1440670164500. Starting simulation... +info: Entering event queue @ 1441406755000. Starting simulation... switching cpus -info: Entering event queue @ 1441208907000. Starting simulation... +info: Entering event queue @ 1441406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1442208907000. Starting simulation... +info: Entering event queue @ 1442406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1443208907000. Starting simulation... +info: Entering event queue @ 1443406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1444208907000. Starting simulation... +info: Entering event queue @ 1444406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1445208907000. Starting simulation... +info: Entering event queue @ 1445406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1446208907000. Starting simulation... +info: Entering event queue @ 1446406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1447208907000. Starting simulation... +info: Entering event queue @ 1447406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1448208907000. Starting simulation... +info: Entering event queue @ 1448406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1449208907000. Starting simulation... +info: Entering event queue @ 1449406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1450208907000. Starting simulation... +info: Entering event queue @ 1450406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1451208907000. Starting simulation... +info: Entering event queue @ 1451406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1452208907000. Starting simulation... +info: Entering event queue @ 1452406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1453208907000. Starting simulation... +info: Entering event queue @ 1453406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1454208907000. Starting simulation... +info: Entering event queue @ 1454406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1455208907000. Starting simulation... +info: Entering event queue @ 1455406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1456208907000. Starting simulation... +info: Entering event queue @ 1456406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1457208907000. Starting simulation... +info: Entering event queue @ 1457406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1458208907000. Starting simulation... +info: Entering event queue @ 1458406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1459208907000. Starting simulation... +info: Entering event queue @ 1459406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1460208907000. Starting simulation... +info: Entering event queue @ 1460406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1461208907000. Starting simulation... +info: Entering event queue @ 1461406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1462208907000. Starting simulation... +info: Entering event queue @ 1462406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1463208907000. Starting simulation... +info: Entering event queue @ 1463406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1464208907000. Starting simulation... +info: Entering event queue @ 1464406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1465208907000. Starting simulation... +info: Entering event queue @ 1465406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1466208907000. Starting simulation... +info: Entering event queue @ 1466406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1467208907000. Starting simulation... +info: Entering event queue @ 1467406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1468208907000. Starting simulation... +info: Entering event queue @ 1468406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1469208907000. Starting simulation... +info: Entering event queue @ 1469406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1470208907000. Starting simulation... +info: Entering event queue @ 1470406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1471208907000. Starting simulation... +info: Entering event queue @ 1471406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1472208907000. Starting simulation... +info: Entering event queue @ 1472406757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1473208907000. Starting simulation... -info: Entering event queue @ 1473945196000. Starting simulation... +info: Entering event queue @ 1473406757000. Starting simulation... +info: Entering event queue @ 1474143334000. Starting simulation... switching cpus -info: Entering event queue @ 1473945198000. Starting simulation... +info: Entering event queue @ 1474143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1474945198000. Starting simulation... +info: Entering event queue @ 1475143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1475945198000. Starting simulation... +info: Entering event queue @ 1476143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1476945198000. Starting simulation... +info: Entering event queue @ 1477143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1477945198000. Starting simulation... +info: Entering event queue @ 1478143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1478945198000. Starting simulation... +info: Entering event queue @ 1479143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1479945198000. Starting simulation... +info: Entering event queue @ 1480143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1480945198000. Starting simulation... +info: Entering event queue @ 1481143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1481945198000. Starting simulation... +info: Entering event queue @ 1482143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1482945198000. Starting simulation... +info: Entering event queue @ 1483143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1483945198000. Starting simulation... +info: Entering event queue @ 1484143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1484945198000. Starting simulation... +info: Entering event queue @ 1485143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1485945198000. Starting simulation... +info: Entering event queue @ 1486143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1486945198000. Starting simulation... +info: Entering event queue @ 1487143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1487945198000. Starting simulation... +info: Entering event queue @ 1488143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1488945198000. Starting simulation... +info: Entering event queue @ 1489143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1489945198000. Starting simulation... +info: Entering event queue @ 1490143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1490945198000. Starting simulation... +info: Entering event queue @ 1491143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1491945198000. Starting simulation... +info: Entering event queue @ 1492143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1492945198000. Starting simulation... +info: Entering event queue @ 1493143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1493945198000. Starting simulation... +info: Entering event queue @ 1494143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1494945198000. Starting simulation... +info: Entering event queue @ 1495143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1495945198000. Starting simulation... +info: Entering event queue @ 1496143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1496945198000. Starting simulation... +info: Entering event queue @ 1497143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1497945198000. Starting simulation... +info: Entering event queue @ 1498143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1498945198000. Starting simulation... +info: Entering event queue @ 1499143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1499945198000. Starting simulation... +info: Entering event queue @ 1500143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1500945198000. Starting simulation... +info: Entering event queue @ 1501143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1501945198000. Starting simulation... +info: Entering event queue @ 1502143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1502945198000. Starting simulation... +info: Entering event queue @ 1503143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1503945198000. Starting simulation... +info: Entering event queue @ 1504143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1504945198000. Starting simulation... +info: Entering event queue @ 1505143336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1505945198000. Starting simulation... -info: Entering event queue @ 1506681337000. Starting simulation... +info: Entering event queue @ 1506143336000. Starting simulation... +info: Entering event queue @ 1506878939000. Starting simulation... switching cpus -info: Entering event queue @ 1506681339000. Starting simulation... +info: Entering event queue @ 1506878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1507681339000. Starting simulation... +info: Entering event queue @ 1507878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1508681339000. Starting simulation... +info: Entering event queue @ 1508878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1509681339000. Starting simulation... +info: Entering event queue @ 1509878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1510681339000. Starting simulation... +info: Entering event queue @ 1510878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1511681339000. Starting simulation... +info: Entering event queue @ 1511878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1512681339000. Starting simulation... +info: Entering event queue @ 1512878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1513681339000. Starting simulation... +info: Entering event queue @ 1513878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1514681339000. Starting simulation... +info: Entering event queue @ 1514878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1515681339000. Starting simulation... +info: Entering event queue @ 1515878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1516681339000. Starting simulation... +info: Entering event queue @ 1516878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1517681339000. Starting simulation... +info: Entering event queue @ 1517878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1518681339000. Starting simulation... +info: Entering event queue @ 1518878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1519681339000. Starting simulation... +info: Entering event queue @ 1519878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1520681339000. Starting simulation... +info: Entering event queue @ 1520878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1521681339000. Starting simulation... +info: Entering event queue @ 1521878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1522681339000. Starting simulation... +info: Entering event queue @ 1522878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1523681339000. Starting simulation... +info: Entering event queue @ 1523878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1524681339000. Starting simulation... +info: Entering event queue @ 1524878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1525681339000. Starting simulation... +info: Entering event queue @ 1525878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1526681339000. Starting simulation... +info: Entering event queue @ 1526878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1527681339000. Starting simulation... +info: Entering event queue @ 1527878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1528681339000. Starting simulation... +info: Entering event queue @ 1528878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1529681339000. Starting simulation... +info: Entering event queue @ 1529878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1530681339000. Starting simulation... +info: Entering event queue @ 1530878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1531681339000. Starting simulation... +info: Entering event queue @ 1531878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1532681339000. Starting simulation... +info: Entering event queue @ 1532878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1533681339000. Starting simulation... +info: Entering event queue @ 1533878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1534681339000. Starting simulation... +info: Entering event queue @ 1534878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1535681339000. Starting simulation... +info: Entering event queue @ 1535878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1536681339000. Starting simulation... +info: Entering event queue @ 1536878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1537681339000. Starting simulation... +info: Entering event queue @ 1537878941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1538681339000. Starting simulation... -info: Entering event queue @ 1539417631000. Starting simulation... +info: Entering event queue @ 1538878941000. Starting simulation... +info: Entering event queue @ 1539615539000. Starting simulation... switching cpus -info: Entering event queue @ 1539417633000. Starting simulation... +info: Entering event queue @ 1539615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1540417633000. Starting simulation... +info: Entering event queue @ 1540615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1541417633000. Starting simulation... +info: Entering event queue @ 1541615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1542417633000. Starting simulation... +info: Entering event queue @ 1542615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1543417633000. Starting simulation... +info: Entering event queue @ 1543615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1544417633000. Starting simulation... +info: Entering event queue @ 1544615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1545417633000. Starting simulation... +info: Entering event queue @ 1545615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1546417633000. Starting simulation... +info: Entering event queue @ 1546615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1547417633000. Starting simulation... +info: Entering event queue @ 1547615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1548417633000. Starting simulation... +info: Entering event queue @ 1548615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1549417633000. Starting simulation... +info: Entering event queue @ 1549615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1550417633000. Starting simulation... +info: Entering event queue @ 1550615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1551417633000. Starting simulation... +info: Entering event queue @ 1551615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1552417633000. Starting simulation... +info: Entering event queue @ 1552615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1553417633000. Starting simulation... +info: Entering event queue @ 1553615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1554417633000. Starting simulation... +info: Entering event queue @ 1554615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1555417633000. Starting simulation... +info: Entering event queue @ 1555615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1556417633000. Starting simulation... +info: Entering event queue @ 1556615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1557417633000. Starting simulation... +info: Entering event queue @ 1557615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1558417633000. Starting simulation... +info: Entering event queue @ 1558615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1559417633000. Starting simulation... +info: Entering event queue @ 1559615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1560417633000. Starting simulation... +info: Entering event queue @ 1560615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1561417633000. Starting simulation... +info: Entering event queue @ 1561615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1562417633000. Starting simulation... +info: Entering event queue @ 1562615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1563417633000. Starting simulation... +info: Entering event queue @ 1563615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1564417633000. Starting simulation... +info: Entering event queue @ 1564615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1565417633000. Starting simulation... +info: Entering event queue @ 1565615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1566417633000. Starting simulation... +info: Entering event queue @ 1566615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1567417633000. Starting simulation... +info: Entering event queue @ 1567615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1568417633000. Starting simulation... +info: Entering event queue @ 1568615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1569417633000. Starting simulation... +info: Entering event queue @ 1569615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1570417633000. Starting simulation... +info: Entering event queue @ 1570615541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1571417633000. Starting simulation... -info: Entering event queue @ 1572153772000. Starting simulation... +info: Entering event queue @ 1571615541000. Starting simulation... +info: Entering event queue @ 1572352118000. Starting simulation... switching cpus -info: Entering event queue @ 1572153774000. Starting simulation... +info: Entering event queue @ 1572352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1573153774000. Starting simulation... +info: Entering event queue @ 1573352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1574153774000. Starting simulation... +info: Entering event queue @ 1574352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1575153774000. Starting simulation... +info: Entering event queue @ 1575352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1576153774000. Starting simulation... +info: Entering event queue @ 1576352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1577153774000. Starting simulation... +info: Entering event queue @ 1577352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1578153774000. Starting simulation... +info: Entering event queue @ 1578352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1579153774000. Starting simulation... +info: Entering event queue @ 1579352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1580153774000. Starting simulation... +info: Entering event queue @ 1580352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1581153774000. Starting simulation... +info: Entering event queue @ 1581352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1582153774000. Starting simulation... +info: Entering event queue @ 1582352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1583153774000. Starting simulation... +info: Entering event queue @ 1583352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1584153774000. Starting simulation... +info: Entering event queue @ 1584352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1585153774000. Starting simulation... +info: Entering event queue @ 1585352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1586153774000. Starting simulation... +info: Entering event queue @ 1586352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1587153774000. Starting simulation... +info: Entering event queue @ 1587352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1588153774000. Starting simulation... +info: Entering event queue @ 1588352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1589153774000. Starting simulation... +info: Entering event queue @ 1589352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1590153774000. Starting simulation... +info: Entering event queue @ 1590352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1591153774000. Starting simulation... +info: Entering event queue @ 1591352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1592153774000. Starting simulation... +info: Entering event queue @ 1592352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1593153774000. Starting simulation... +info: Entering event queue @ 1593352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1594153774000. Starting simulation... +info: Entering event queue @ 1594352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1595153774000. Starting simulation... +info: Entering event queue @ 1595352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1596153774000. Starting simulation... +info: Entering event queue @ 1596352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1597153774000. Starting simulation... +info: Entering event queue @ 1597352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1598153774000. Starting simulation... +info: Entering event queue @ 1598352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1599153774000. Starting simulation... +info: Entering event queue @ 1599352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1600153774000. Starting simulation... +info: Entering event queue @ 1600352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1601153774000. Starting simulation... +info: Entering event queue @ 1601352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1602153774000. Starting simulation... +info: Entering event queue @ 1602352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1603153774000. Starting simulation... +info: Entering event queue @ 1603352120000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1604153774000. Starting simulation... -info: Entering event queue @ 1604890063000. Starting simulation... +info: Entering event queue @ 1604352120000. Starting simulation... +info: Entering event queue @ 1605087530000. Starting simulation... switching cpus -info: Entering event queue @ 1604890065000. Starting simulation... +info: Entering event queue @ 1605087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1605890065000. Starting simulation... +info: Entering event queue @ 1606087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1606890065000. Starting simulation... +info: Entering event queue @ 1607087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1607890065000. Starting simulation... +info: Entering event queue @ 1608087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1608890065000. Starting simulation... +info: Entering event queue @ 1609087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1609890065000. Starting simulation... +info: Entering event queue @ 1610087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1610890065000. Starting simulation... +info: Entering event queue @ 1611087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1611890065000. Starting simulation... +info: Entering event queue @ 1612087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1612890065000. Starting simulation... +info: Entering event queue @ 1613087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1613890065000. Starting simulation... +info: Entering event queue @ 1614087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1614890065000. Starting simulation... +info: Entering event queue @ 1615087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1615890065000. Starting simulation... +info: Entering event queue @ 1616087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1616890065000. Starting simulation... +info: Entering event queue @ 1617087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1617890065000. Starting simulation... +info: Entering event queue @ 1618087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1618890065000. Starting simulation... +info: Entering event queue @ 1619087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1619890065000. Starting simulation... +info: Entering event queue @ 1620087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1620890065000. Starting simulation... +info: Entering event queue @ 1621087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1621890065000. Starting simulation... +info: Entering event queue @ 1622087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1622890065000. Starting simulation... +info: Entering event queue @ 1623087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1623890065000. Starting simulation... +info: Entering event queue @ 1624087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1624890065000. Starting simulation... +info: Entering event queue @ 1625087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1625890065000. Starting simulation... +info: Entering event queue @ 1626087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1626890065000. Starting simulation... +info: Entering event queue @ 1627087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1627890065000. Starting simulation... +info: Entering event queue @ 1628087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1628890065000. Starting simulation... +info: Entering event queue @ 1629087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1629890065000. Starting simulation... +info: Entering event queue @ 1630087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1630890065000. Starting simulation... +info: Entering event queue @ 1631087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1631890065000. Starting simulation... +info: Entering event queue @ 1632087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1632890065000. Starting simulation... +info: Entering event queue @ 1633087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1633890065000. Starting simulation... +info: Entering event queue @ 1634087532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1634890065000. Starting simulation... +info: Entering event queue @ 1635087532000. Starting simulation... switching cpus -info: Entering event queue @ 1634890066000. Starting simulation... +info: Entering event queue @ 1635087539500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1635890066000. Starting simulation... +info: Entering event queue @ 1636087539500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1636890066000. Starting simulation... -info: Entering event queue @ 1637626663000. Starting simulation... +info: Entering event queue @ 1637087539500. Starting simulation... +info: Entering event queue @ 1637824130000. Starting simulation... switching cpus -info: Entering event queue @ 1637626665000. Starting simulation... +info: Entering event queue @ 1637824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1638626665000. Starting simulation... +info: Entering event queue @ 1638824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1639626665000. Starting simulation... +info: Entering event queue @ 1639824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1640626665000. Starting simulation... +info: Entering event queue @ 1640824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1641626665000. Starting simulation... +info: Entering event queue @ 1641824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1642626665000. Starting simulation... +info: Entering event queue @ 1642824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1643626665000. Starting simulation... +info: Entering event queue @ 1643824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1644626665000. Starting simulation... +info: Entering event queue @ 1644824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1645626665000. Starting simulation... +info: Entering event queue @ 1645824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1646626665000. Starting simulation... +info: Entering event queue @ 1646824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1647626665000. Starting simulation... +info: Entering event queue @ 1647824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1648626665000. Starting simulation... +info: Entering event queue @ 1648824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1649626665000. Starting simulation... +info: Entering event queue @ 1649824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1650626665000. Starting simulation... +info: Entering event queue @ 1650824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1651626665000. Starting simulation... +info: Entering event queue @ 1651824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1652626665000. Starting simulation... +info: Entering event queue @ 1652824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1653626665000. Starting simulation... +info: Entering event queue @ 1653824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1654626665000. Starting simulation... +info: Entering event queue @ 1654824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1655626665000. Starting simulation... +info: Entering event queue @ 1655824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1656626665000. Starting simulation... +info: Entering event queue @ 1656824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1657626665000. Starting simulation... +info: Entering event queue @ 1657824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1658626665000. Starting simulation... +info: Entering event queue @ 1658824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1659626665000. Starting simulation... +info: Entering event queue @ 1659824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1660626665000. Starting simulation... +info: Entering event queue @ 1660824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1661626665000. Starting simulation... +info: Entering event queue @ 1661824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1662626665000. Starting simulation... +info: Entering event queue @ 1662824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1663626665000. Starting simulation... +info: Entering event queue @ 1663824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1664626665000. Starting simulation... +info: Entering event queue @ 1664824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1665626665000. Starting simulation... +info: Entering event queue @ 1665824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1666626665000. Starting simulation... +info: Entering event queue @ 1666824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1667626665000. Starting simulation... +info: Entering event queue @ 1667824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1668626665000. Starting simulation... +info: Entering event queue @ 1668824132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1669626665000. Starting simulation... -info: Entering event queue @ 1670362807000. Starting simulation... +info: Entering event queue @ 1669824132000. Starting simulation... +info: Entering event queue @ 1670560751000. Starting simulation... switching cpus -info: Entering event queue @ 1670362809000. Starting simulation... +info: Entering event queue @ 1670560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1671362809000. Starting simulation... +info: Entering event queue @ 1671560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1672362809000. Starting simulation... +info: Entering event queue @ 1672560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1673362809000. Starting simulation... +info: Entering event queue @ 1673560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1674362809000. Starting simulation... +info: Entering event queue @ 1674560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1675362809000. Starting simulation... +info: Entering event queue @ 1675560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1676362809000. Starting simulation... +info: Entering event queue @ 1676560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1677362809000. Starting simulation... +info: Entering event queue @ 1677560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1678362809000. Starting simulation... +info: Entering event queue @ 1678560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1679362809000. Starting simulation... +info: Entering event queue @ 1679560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1680362809000. Starting simulation... +info: Entering event queue @ 1680560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1681362809000. Starting simulation... +info: Entering event queue @ 1681560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1682362809000. Starting simulation... +info: Entering event queue @ 1682560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1683362809000. Starting simulation... +info: Entering event queue @ 1683560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1684362809000. Starting simulation... +info: Entering event queue @ 1684560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1685362809000. Starting simulation... +info: Entering event queue @ 1685560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1686362809000. Starting simulation... +info: Entering event queue @ 1686560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1687362809000. Starting simulation... +info: Entering event queue @ 1687560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1688362809000. Starting simulation... +info: Entering event queue @ 1688560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1689362809000. Starting simulation... +info: Entering event queue @ 1689560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1690362809000. Starting simulation... +info: Entering event queue @ 1690560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1691362809000. Starting simulation... +info: Entering event queue @ 1691560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1692362809000. Starting simulation... +info: Entering event queue @ 1692560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1693362809000. Starting simulation... +info: Entering event queue @ 1693560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1694362809000. Starting simulation... +info: Entering event queue @ 1694560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1695362809000. Starting simulation... +info: Entering event queue @ 1695560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1696362809000. Starting simulation... +info: Entering event queue @ 1696560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1697362809000. Starting simulation... +info: Entering event queue @ 1697560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1698362809000. Starting simulation... +info: Entering event queue @ 1698560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1699362809000. Starting simulation... +info: Entering event queue @ 1699560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1700362809000. Starting simulation... +info: Entering event queue @ 1700560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1701362809000. Starting simulation... +info: Entering event queue @ 1701560753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1702362809000. Starting simulation... -info: Entering event queue @ 1703098954000. Starting simulation... +info: Entering event queue @ 1702560753000. Starting simulation... +info: Entering event queue @ 1703297351000. Starting simulation... switching cpus -info: Entering event queue @ 1703098956000. Starting simulation... +info: Entering event queue @ 1703297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1704098956000. Starting simulation... +info: Entering event queue @ 1704297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1705098956000. Starting simulation... +info: Entering event queue @ 1705297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1706098956000. Starting simulation... +info: Entering event queue @ 1706297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1707098956000. Starting simulation... +info: Entering event queue @ 1707297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1708098956000. Starting simulation... +info: Entering event queue @ 1708297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1709098956000. Starting simulation... +info: Entering event queue @ 1709297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1710098956000. Starting simulation... +info: Entering event queue @ 1710297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1711098956000. Starting simulation... +info: Entering event queue @ 1711297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1712098956000. Starting simulation... +info: Entering event queue @ 1712297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1713098956000. Starting simulation... +info: Entering event queue @ 1713297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1714098956000. Starting simulation... +info: Entering event queue @ 1714297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1715098956000. Starting simulation... +info: Entering event queue @ 1715297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1716098956000. Starting simulation... +info: Entering event queue @ 1716297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1717098956000. Starting simulation... +info: Entering event queue @ 1717297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1718098956000. Starting simulation... +info: Entering event queue @ 1718297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1719098956000. Starting simulation... +info: Entering event queue @ 1719297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1720098956000. Starting simulation... +info: Entering event queue @ 1720297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1721098956000. Starting simulation... +info: Entering event queue @ 1721297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1722098956000. Starting simulation... +info: Entering event queue @ 1722297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1723098956000. Starting simulation... +info: Entering event queue @ 1723297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1724098956000. Starting simulation... +info: Entering event queue @ 1724297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1725098956000. Starting simulation... +info: Entering event queue @ 1725297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1726098956000. Starting simulation... +info: Entering event queue @ 1726297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1727098956000. Starting simulation... +info: Entering event queue @ 1727297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1728098956000. Starting simulation... +info: Entering event queue @ 1728297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1729098956000. Starting simulation... +info: Entering event queue @ 1729297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1730098956000. Starting simulation... +info: Entering event queue @ 1730297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1731098956000. Starting simulation... +info: Entering event queue @ 1731297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1732098956000. Starting simulation... +info: Entering event queue @ 1732297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1733098956000. Starting simulation... +info: Entering event queue @ 1733297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1734098956000. Starting simulation... +info: Entering event queue @ 1734297353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1735098956000. Starting simulation... -info: Entering event queue @ 1735835245000. Starting simulation... +info: Entering event queue @ 1735297353000. Starting simulation... +info: Entering event queue @ 1736032914000. Starting simulation... switching cpus -info: Entering event queue @ 1735835247000. Starting simulation... +info: Entering event queue @ 1736032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1736835247000. Starting simulation... +info: Entering event queue @ 1737032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1737835247000. Starting simulation... +info: Entering event queue @ 1738032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1738835247000. Starting simulation... +info: Entering event queue @ 1739032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1739835247000. Starting simulation... +info: Entering event queue @ 1740032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1740835247000. Starting simulation... +info: Entering event queue @ 1741032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1741835247000. Starting simulation... +info: Entering event queue @ 1742032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1742835247000. Starting simulation... +info: Entering event queue @ 1743032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1743835247000. Starting simulation... +info: Entering event queue @ 1744032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1744835247000. Starting simulation... +info: Entering event queue @ 1745032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1745835247000. Starting simulation... +info: Entering event queue @ 1746032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1746835247000. Starting simulation... +info: Entering event queue @ 1747032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1747835247000. Starting simulation... +info: Entering event queue @ 1748032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1748835247000. Starting simulation... +info: Entering event queue @ 1749032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1749835247000. Starting simulation... +info: Entering event queue @ 1750032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1750835247000. Starting simulation... +info: Entering event queue @ 1751032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1751835247000. Starting simulation... +info: Entering event queue @ 1752032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1752835247000. Starting simulation... +info: Entering event queue @ 1753032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1753835247000. Starting simulation... +info: Entering event queue @ 1754032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1754835247000. Starting simulation... +info: Entering event queue @ 1755032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1755835247000. Starting simulation... +info: Entering event queue @ 1756032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1756835247000. Starting simulation... +info: Entering event queue @ 1757032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1757835247000. Starting simulation... +info: Entering event queue @ 1758032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1758835247000. Starting simulation... +info: Entering event queue @ 1759032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1759835247000. Starting simulation... +info: Entering event queue @ 1760032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1760835247000. Starting simulation... +info: Entering event queue @ 1761032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1761835247000. Starting simulation... +info: Entering event queue @ 1762032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1762835247000. Starting simulation... +info: Entering event queue @ 1763032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1763835247000. Starting simulation... +info: Entering event queue @ 1764032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1764835247000. Starting simulation... +info: Entering event queue @ 1765032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1765835247000. Starting simulation... +info: Entering event queue @ 1766032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1766835247000. Starting simulation... +info: Entering event queue @ 1767032916000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1767835247000. Starting simulation... -info: Entering event queue @ 1768571389000. Starting simulation... +info: Entering event queue @ 1768032916000. Starting simulation... +info: Entering event queue @ 1768769514000. Starting simulation... switching cpus -info: Entering event queue @ 1768571391000. Starting simulation... +info: Entering event queue @ 1768769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1769571391000. Starting simulation... +info: Entering event queue @ 1769769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1770571391000. Starting simulation... +info: Entering event queue @ 1770769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1771571391000. Starting simulation... +info: Entering event queue @ 1771769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1772571391000. Starting simulation... +info: Entering event queue @ 1772769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1773571391000. Starting simulation... +info: Entering event queue @ 1773769516000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 1774769516000. Starting simulation... switching cpus -info: Entering event queue @ 1774571391000. Starting simulation... +info: Entering event queue @ 1774769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1775571391000. Starting simulation... +info: Entering event queue @ 1775769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1776571391000. Starting simulation... +info: Entering event queue @ 1776769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1777571391000. Starting simulation... +info: Entering event queue @ 1777769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1778571391000. Starting simulation... +info: Entering event queue @ 1778769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1779571391000. Starting simulation... +info: Entering event queue @ 1779769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1780571391000. Starting simulation... +info: Entering event queue @ 1780769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1781571391000. Starting simulation... +info: Entering event queue @ 1781769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1782571391000. Starting simulation... +info: Entering event queue @ 1782769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1783571391000. Starting simulation... +info: Entering event queue @ 1783769517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 1784769517000. Starting simulation... switching cpus -info: Entering event queue @ 1784571391000. Starting simulation... +info: Entering event queue @ 1784769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1785571391000. Starting simulation... +info: Entering event queue @ 1785769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1786571391000. Starting simulation... +info: Entering event queue @ 1786769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1787571391000. Starting simulation... +info: Entering event queue @ 1787769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1788571391000. Starting simulation... +info: Entering event queue @ 1788769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1789571391000. Starting simulation... +info: Entering event queue @ 1789769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1790571391000. Starting simulation... +info: Entering event queue @ 1790769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1791571391000. Starting simulation... +info: Entering event queue @ 1791769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1792571391000. Starting simulation... +info: Entering event queue @ 1792769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1793571391000. Starting simulation... +info: Entering event queue @ 1793769518000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 1794769518000. Starting simulation... switching cpus -info: Entering event queue @ 1794571391000. Starting simulation... +info: Entering event queue @ 1794769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1795571391000. Starting simulation... +info: Entering event queue @ 1795769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1796571391000. Starting simulation... +info: Entering event queue @ 1796769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1797571391000. Starting simulation... +info: Entering event queue @ 1797769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1798571391000. Starting simulation... +info: Entering event queue @ 1798769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1799571391000. Starting simulation... +info: Entering event queue @ 1799769519000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1800571391000. Starting simulation... -info: Entering event queue @ 1801307680000. Starting simulation... +info: Entering event queue @ 1800769519000. Starting simulation... +info: Entering event queue @ 1801506135000. Starting simulation... switching cpus -info: Entering event queue @ 1801307682000. Starting simulation... +info: Entering event queue @ 1801506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1802307682000. Starting simulation... +info: Entering event queue @ 1802506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1803307682000. Starting simulation... +info: Entering event queue @ 1803506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1804307682000. Starting simulation... +info: Entering event queue @ 1804506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1805307682000. Starting simulation... +info: Entering event queue @ 1805506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1806307682000. Starting simulation... +info: Entering event queue @ 1806506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1807307682000. Starting simulation... +info: Entering event queue @ 1807506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1808307682000. Starting simulation... +info: Entering event queue @ 1808506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1809307682000. Starting simulation... +info: Entering event queue @ 1809506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1810307682000. Starting simulation... +info: Entering event queue @ 1810506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1811307682000. Starting simulation... +info: Entering event queue @ 1811506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1812307682000. Starting simulation... +info: Entering event queue @ 1812506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1813307682000. Starting simulation... +info: Entering event queue @ 1813506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1814307682000. Starting simulation... +info: Entering event queue @ 1814506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1815307682000. Starting simulation... +info: Entering event queue @ 1815506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1816307682000. Starting simulation... +info: Entering event queue @ 1816506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1817307682000. Starting simulation... +info: Entering event queue @ 1817506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1818307682000. Starting simulation... +info: Entering event queue @ 1818506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1819307682000. Starting simulation... +info: Entering event queue @ 1819506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1820307682000. Starting simulation... +info: Entering event queue @ 1820506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1821307682000. Starting simulation... +info: Entering event queue @ 1821506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1822307682000. Starting simulation... +info: Entering event queue @ 1822506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1823307682000. Starting simulation... +info: Entering event queue @ 1823506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1824307682000. Starting simulation... +info: Entering event queue @ 1824506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1825307682000. Starting simulation... +info: Entering event queue @ 1825506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1826307682000. Starting simulation... +info: Entering event queue @ 1826506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1827307682000. Starting simulation... +info: Entering event queue @ 1827506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1828307682000. Starting simulation... +info: Entering event queue @ 1828506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1829307682000. Starting simulation... +info: Entering event queue @ 1829506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1830307682000. Starting simulation... +info: Entering event queue @ 1830506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1831307682000. Starting simulation... +info: Entering event queue @ 1831506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1832307682000. Starting simulation... +info: Entering event queue @ 1832506137000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1833307682000. Starting simulation... -info: Entering event queue @ 1834043821000. Starting simulation... +info: Entering event queue @ 1833506137000. Starting simulation... +info: Entering event queue @ 1834241547000. Starting simulation... switching cpus -info: Entering event queue @ 1834043823000. Starting simulation... +info: Entering event queue @ 1834241549000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1835043823000. Starting simulation... +info: Entering event queue @ 1835241549000. Starting simulation... switching cpus -info: Entering event queue @ 1835043824000. Starting simulation... +info: Entering event queue @ 1835241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1836043824000. Starting simulation... +info: Entering event queue @ 1836241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1837043824000. Starting simulation... +info: Entering event queue @ 1837241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1838043824000. Starting simulation... +info: Entering event queue @ 1838241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1839043824000. Starting simulation... +info: Entering event queue @ 1839241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1840043824000. Starting simulation... +info: Entering event queue @ 1840241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1841043824000. Starting simulation... +info: Entering event queue @ 1841241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1842043824000. Starting simulation... +info: Entering event queue @ 1842241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1843043824000. Starting simulation... +info: Entering event queue @ 1843241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1844043824000. Starting simulation... +info: Entering event queue @ 1844241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1845043824000. Starting simulation... +info: Entering event queue @ 1845241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1846043824000. Starting simulation... +info: Entering event queue @ 1846241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1847043824000. Starting simulation... +info: Entering event queue @ 1847241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1848043824000. Starting simulation... +info: Entering event queue @ 1848241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1849043824000. Starting simulation... +info: Entering event queue @ 1849241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1850043824000. Starting simulation... +info: Entering event queue @ 1850241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1851043824000. Starting simulation... +info: Entering event queue @ 1851241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1852043824000. Starting simulation... +info: Entering event queue @ 1852241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1853043824000. Starting simulation... +info: Entering event queue @ 1853241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1854043824000. Starting simulation... +info: Entering event queue @ 1854241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1855043824000. Starting simulation... +info: Entering event queue @ 1855241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1856043824000. Starting simulation... +info: Entering event queue @ 1856241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1857043824000. Starting simulation... +info: Entering event queue @ 1857241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1858043824000. Starting simulation... +info: Entering event queue @ 1858241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1859043824000. Starting simulation... +info: Entering event queue @ 1859241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1860043824000. Starting simulation... +info: Entering event queue @ 1860241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1861043824000. Starting simulation... +info: Entering event queue @ 1861241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1862043824000. Starting simulation... +info: Entering event queue @ 1862241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1863043824000. Starting simulation... +info: Entering event queue @ 1863241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1864043824000. Starting simulation... +info: Entering event queue @ 1864241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1865043824000. Starting simulation... +info: Entering event queue @ 1865241556500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1866043824000. Starting simulation... -info: Entering event queue @ 1866780115000. Starting simulation... +info: Entering event queue @ 1866241556500. Starting simulation... +info: Entering event queue @ 1866978147000. Starting simulation... switching cpus -info: Entering event queue @ 1866780117000. Starting simulation... +info: Entering event queue @ 1866978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1867780117000. Starting simulation... +info: Entering event queue @ 1867978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1868780117000. Starting simulation... +info: Entering event queue @ 1868978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1869780117000. Starting simulation... +info: Entering event queue @ 1869978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1870780117000. Starting simulation... +info: Entering event queue @ 1870978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1871780117000. Starting simulation... +info: Entering event queue @ 1871978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1872780117000. Starting simulation... +info: Entering event queue @ 1872978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1873780117000. Starting simulation... +info: Entering event queue @ 1873978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1874780117000. Starting simulation... +info: Entering event queue @ 1874978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1875780117000. Starting simulation... +info: Entering event queue @ 1875978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1876780117000. Starting simulation... +info: Entering event queue @ 1876978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1877780117000. Starting simulation... +info: Entering event queue @ 1877978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1878780117000. Starting simulation... +info: Entering event queue @ 1878978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1879780117000. Starting simulation... +info: Entering event queue @ 1879978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1880780117000. Starting simulation... +info: Entering event queue @ 1880978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1881780117000. Starting simulation... +info: Entering event queue @ 1881978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1882780117000. Starting simulation... +info: Entering event queue @ 1882978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1883780117000. Starting simulation... +info: Entering event queue @ 1883978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1884780117000. Starting simulation... +info: Entering event queue @ 1884978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1885780117000. Starting simulation... +info: Entering event queue @ 1885978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1886780117000. Starting simulation... +info: Entering event queue @ 1886978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1887780117000. Starting simulation... +info: Entering event queue @ 1887978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1888780117000. Starting simulation... +info: Entering event queue @ 1888978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1889780117000. Starting simulation... +info: Entering event queue @ 1889978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1890780117000. Starting simulation... +info: Entering event queue @ 1890978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1891780117000. Starting simulation... +info: Entering event queue @ 1891978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1892780117000. Starting simulation... +info: Entering event queue @ 1892978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1893780117000. Starting simulation... +info: Entering event queue @ 1893978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1894780117000. Starting simulation... +info: Entering event queue @ 1894978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1895780117000. Starting simulation... +info: Entering event queue @ 1895978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1896780117000. Starting simulation... +info: Entering event queue @ 1896978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1897780117000. Starting simulation... +info: Entering event queue @ 1897978149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1898780117000. Starting simulation... -info: Entering event queue @ 1899516256000. Starting simulation... +info: Entering event queue @ 1898978149000. Starting simulation... +info: Entering event queue @ 1899714726000. Starting simulation... switching cpus -info: Entering event queue @ 1899516258000. Starting simulation... +info: Entering event queue @ 1899714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1900516258000. Starting simulation... +info: Entering event queue @ 1900714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1901516258000. Starting simulation... +info: Entering event queue @ 1901714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1902516258000. Starting simulation... +info: Entering event queue @ 1902714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1903516258000. Starting simulation... +info: Entering event queue @ 1903714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1904516258000. Starting simulation... +info: Entering event queue @ 1904714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1905516258000. Starting simulation... +info: Entering event queue @ 1905714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1906516258000. Starting simulation... +info: Entering event queue @ 1906714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1907516258000. Starting simulation... +info: Entering event queue @ 1907714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1908516258000. Starting simulation... +info: Entering event queue @ 1908714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1909516258000. Starting simulation... +info: Entering event queue @ 1909714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1910516258000. Starting simulation... +info: Entering event queue @ 1910714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1911516258000. Starting simulation... +info: Entering event queue @ 1911714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1912516258000. Starting simulation... +info: Entering event queue @ 1912714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1913516258000. Starting simulation... +info: Entering event queue @ 1913714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1914516258000. Starting simulation... +info: Entering event queue @ 1914714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1915516258000. Starting simulation... +info: Entering event queue @ 1915714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1916516258000. Starting simulation... +info: Entering event queue @ 1916714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1917516258000. Starting simulation... +info: Entering event queue @ 1917714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1918516258000. Starting simulation... +info: Entering event queue @ 1918714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1919516258000. Starting simulation... +info: Entering event queue @ 1919714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1920516258000. Starting simulation... +info: Entering event queue @ 1920714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1921516258000. Starting simulation... +info: Entering event queue @ 1921714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1922516258000. Starting simulation... +info: Entering event queue @ 1922714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1923516258000. Starting simulation... +info: Entering event queue @ 1923714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1924516258000. Starting simulation... +info: Entering event queue @ 1924714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1925516258000. Starting simulation... +info: Entering event queue @ 1925714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1926516258000. Starting simulation... +info: Entering event queue @ 1926714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1927516258000. Starting simulation... +info: Entering event queue @ 1927714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1928516258000. Starting simulation... +info: Entering event queue @ 1928714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1929516258000. Starting simulation... +info: Entering event queue @ 1929714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1930516258000. Starting simulation... +info: Entering event queue @ 1930714728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1931516258000. Starting simulation... -info: Entering event queue @ 1932252856000. Starting simulation... +info: Entering event queue @ 1931714728000. Starting simulation... +info: Entering event queue @ 1932450138000. Starting simulation... switching cpus -info: Entering event queue @ 1932252858000. Starting simulation... +info: Entering event queue @ 1932450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1933252858000. Starting simulation... +info: Entering event queue @ 1933450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1934252858000. Starting simulation... +info: Entering event queue @ 1934450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1935252858000. Starting simulation... +info: Entering event queue @ 1935450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1936252858000. Starting simulation... +info: Entering event queue @ 1936450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1937252858000. Starting simulation... +info: Entering event queue @ 1937450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1938252858000. Starting simulation... +info: Entering event queue @ 1938450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1939252858000. Starting simulation... +info: Entering event queue @ 1939450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1940252858000. Starting simulation... +info: Entering event queue @ 1940450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1941252858000. Starting simulation... +info: Entering event queue @ 1941450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1942252858000. Starting simulation... +info: Entering event queue @ 1942450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1943252858000. Starting simulation... +info: Entering event queue @ 1943450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1944252858000. Starting simulation... +info: Entering event queue @ 1944450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1945252858000. Starting simulation... +info: Entering event queue @ 1945450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1946252858000. Starting simulation... +info: Entering event queue @ 1946450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1947252858000. Starting simulation... +info: Entering event queue @ 1947450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1948252858000. Starting simulation... +info: Entering event queue @ 1948450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1949252858000. Starting simulation... +info: Entering event queue @ 1949450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1950252858000. Starting simulation... +info: Entering event queue @ 1950450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1951252858000. Starting simulation... +info: Entering event queue @ 1951450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1952252858000. Starting simulation... +info: Entering event queue @ 1952450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1953252858000. Starting simulation... +info: Entering event queue @ 1953450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1954252858000. Starting simulation... +info: Entering event queue @ 1954450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1955252858000. Starting simulation... +info: Entering event queue @ 1955450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1956252858000. Starting simulation... +info: Entering event queue @ 1956450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1957252858000. Starting simulation... +info: Entering event queue @ 1957450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1958252858000. Starting simulation... +info: Entering event queue @ 1958450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1959252858000. Starting simulation... +info: Entering event queue @ 1959450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1960252858000. Starting simulation... +info: Entering event queue @ 1960450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1961252858000. Starting simulation... +info: Entering event queue @ 1961450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1962252858000. Starting simulation... +info: Entering event queue @ 1962450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1963252858000. Starting simulation... +info: Entering event queue @ 1963450140000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1964252858000. Starting simulation... -info: Entering event queue @ 1964989147000. Starting simulation... +info: Entering event queue @ 1964450140000. Starting simulation... +info: Entering event queue @ 1965186738000. Starting simulation... switching cpus -info: Entering event queue @ 1964989149000. Starting simulation... +info: Entering event queue @ 1965186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1965989149000. Starting simulation... +info: Entering event queue @ 1966186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1966989149000. Starting simulation... +info: Entering event queue @ 1967186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1967989149000. Starting simulation... +info: Entering event queue @ 1968186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1968989149000. Starting simulation... +info: Entering event queue @ 1969186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1969989149000. Starting simulation... +info: Entering event queue @ 1970186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1970989149000. Starting simulation... +info: Entering event queue @ 1971186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1971989149000. Starting simulation... +info: Entering event queue @ 1972186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1972989149000. Starting simulation... +info: Entering event queue @ 1973186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1973989149000. Starting simulation... +info: Entering event queue @ 1974186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1974989149000. Starting simulation... +info: Entering event queue @ 1975186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1975989149000. Starting simulation... +info: Entering event queue @ 1976186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1976989149000. Starting simulation... +info: Entering event queue @ 1977186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1977989149000. Starting simulation... +info: Entering event queue @ 1978186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1978989149000. Starting simulation... +info: Entering event queue @ 1979186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1979989149000. Starting simulation... +info: Entering event queue @ 1980186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1980989149000. Starting simulation... +info: Entering event queue @ 1981186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1981989149000. Starting simulation... +info: Entering event queue @ 1982186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1982989149000. Starting simulation... +info: Entering event queue @ 1983186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1983989149000. Starting simulation... +info: Entering event queue @ 1984186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1984989149000. Starting simulation... +info: Entering event queue @ 1985186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1985989149000. Starting simulation... +info: Entering event queue @ 1986186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1986989149000. Starting simulation... +info: Entering event queue @ 1987186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1987989149000. Starting simulation... +info: Entering event queue @ 1988186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1988989149000. Starting simulation... +info: Entering event queue @ 1989186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1989989149000. Starting simulation... +info: Entering event queue @ 1990186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1990989149000. Starting simulation... +info: Entering event queue @ 1991186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1991989149000. Starting simulation... +info: Entering event queue @ 1992186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1992989149000. Starting simulation... +info: Entering event queue @ 1993186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1993989149000. Starting simulation... +info: Entering event queue @ 1994186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1994989149000. Starting simulation... +info: Entering event queue @ 1995186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1995989149000. Starting simulation... +info: Entering event queue @ 1996186740000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1996989149000. Starting simulation... -info: Entering event queue @ 1997725291000. Starting simulation... +info: Entering event queue @ 1997186740000. Starting simulation... +info: Entering event queue @ 1997923355000. Starting simulation... switching cpus -info: Entering event queue @ 1997725293000. Starting simulation... +info: Entering event queue @ 1997923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1998725293000. Starting simulation... +info: Entering event queue @ 1998923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1999725293000. Starting simulation... +info: Entering event queue @ 1999923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2000725293000. Starting simulation... +info: Entering event queue @ 2000923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2001725293000. Starting simulation... +info: Entering event queue @ 2001923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2002725293000. Starting simulation... +info: Entering event queue @ 2002923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2003725293000. Starting simulation... +info: Entering event queue @ 2003923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2004725293000. Starting simulation... +info: Entering event queue @ 2004923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2005725293000. Starting simulation... +info: Entering event queue @ 2005923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2006725293000. Starting simulation... +info: Entering event queue @ 2006923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2007725293000. Starting simulation... +info: Entering event queue @ 2007923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2008725293000. Starting simulation... +info: Entering event queue @ 2008923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2009725293000. Starting simulation... +info: Entering event queue @ 2009923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2010725293000. Starting simulation... +info: Entering event queue @ 2010923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2011725293000. Starting simulation... +info: Entering event queue @ 2011923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2012725293000. Starting simulation... +info: Entering event queue @ 2012923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2013725293000. Starting simulation... +info: Entering event queue @ 2013923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2014725293000. Starting simulation... +info: Entering event queue @ 2014923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2015725293000. Starting simulation... +info: Entering event queue @ 2015923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2016725293000. Starting simulation... +info: Entering event queue @ 2016923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2017725293000. Starting simulation... +info: Entering event queue @ 2017923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2018725293000. Starting simulation... +info: Entering event queue @ 2018923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2019725293000. Starting simulation... +info: Entering event queue @ 2019923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2020725293000. Starting simulation... +info: Entering event queue @ 2020923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2021725293000. Starting simulation... +info: Entering event queue @ 2021923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2022725293000. Starting simulation... +info: Entering event queue @ 2022923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2023725293000. Starting simulation... +info: Entering event queue @ 2023923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2024725293000. Starting simulation... +info: Entering event queue @ 2024923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2025725293000. Starting simulation... +info: Entering event queue @ 2025923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2026725293000. Starting simulation... +info: Entering event queue @ 2026923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2027725293000. Starting simulation... +info: Entering event queue @ 2027923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2028725293000. Starting simulation... +info: Entering event queue @ 2028923357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2029725293000. Starting simulation... -info: Entering event queue @ 2030461582000. Starting simulation... +info: Entering event queue @ 2029923357000. Starting simulation... +info: Entering event queue @ 2030658922000. Starting simulation... switching cpus -info: Entering event queue @ 2030461584000. Starting simulation... +info: Entering event queue @ 2030658924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2031461584000. Starting simulation... +info: Entering event queue @ 2031658924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2032461584000. Starting simulation... +info: Entering event queue @ 2032658924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2033461584000. Starting simulation... +info: Entering event queue @ 2033658924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2034461584000. Starting simulation... +info: Entering event queue @ 2034658924000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2035461584000. Starting simulation... +info: Entering event queue @ 2035658924000. Starting simulation... switching cpus -info: Entering event queue @ 2035461585000. Starting simulation... +info: Entering event queue @ 2035658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2036461585000. Starting simulation... +info: Entering event queue @ 2036658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2037461585000. Starting simulation... +info: Entering event queue @ 2037658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2038461585000. Starting simulation... +info: Entering event queue @ 2038658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2039461585000. Starting simulation... +info: Entering event queue @ 2039658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2040461585000. Starting simulation... +info: Entering event queue @ 2040658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2041461585000. Starting simulation... +info: Entering event queue @ 2041658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2042461585000. Starting simulation... +info: Entering event queue @ 2042658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2043461585000. Starting simulation... +info: Entering event queue @ 2043658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2044461585000. Starting simulation... +info: Entering event queue @ 2044658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2045461585000. Starting simulation... +info: Entering event queue @ 2045658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2046461585000. Starting simulation... +info: Entering event queue @ 2046658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2047461585000. Starting simulation... +info: Entering event queue @ 2047658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2048461585000. Starting simulation... +info: Entering event queue @ 2048658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2049461585000. Starting simulation... +info: Entering event queue @ 2049658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2050461585000. Starting simulation... +info: Entering event queue @ 2050658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2051461585000. Starting simulation... +info: Entering event queue @ 2051658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2052461585000. Starting simulation... +info: Entering event queue @ 2052658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2053461585000. Starting simulation... +info: Entering event queue @ 2053658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2054461585000. Starting simulation... +info: Entering event queue @ 2054658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2055461585000. Starting simulation... +info: Entering event queue @ 2055658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2056461585000. Starting simulation... +info: Entering event queue @ 2056658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2057461585000. Starting simulation... +info: Entering event queue @ 2057658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2058461585000. Starting simulation... +info: Entering event queue @ 2058658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2059461585000. Starting simulation... +info: Entering event queue @ 2059658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2060461585000. Starting simulation... +info: Entering event queue @ 2060658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2061461585000. Starting simulation... +info: Entering event queue @ 2061658931500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2062461585000. Starting simulation... -info: Entering event queue @ 2063197726000. Starting simulation... +info: Entering event queue @ 2062658931500. Starting simulation... +info: Entering event queue @ 2063395522000. Starting simulation... switching cpus -info: Entering event queue @ 2063197728000. Starting simulation... +info: Entering event queue @ 2063395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2064197728000. Starting simulation... +info: Entering event queue @ 2064395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2065197728000. Starting simulation... +info: Entering event queue @ 2065395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2066197728000. Starting simulation... +info: Entering event queue @ 2066395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2067197728000. Starting simulation... +info: Entering event queue @ 2067395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2068197728000. Starting simulation... +info: Entering event queue @ 2068395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2069197728000. Starting simulation... +info: Entering event queue @ 2069395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2070197728000. Starting simulation... +info: Entering event queue @ 2070395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2071197728000. Starting simulation... +info: Entering event queue @ 2071395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2072197728000. Starting simulation... +info: Entering event queue @ 2072395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2073197728000. Starting simulation... +info: Entering event queue @ 2073395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2074197728000. Starting simulation... +info: Entering event queue @ 2074395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2075197728000. Starting simulation... +info: Entering event queue @ 2075395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2076197728000. Starting simulation... +info: Entering event queue @ 2076395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2077197728000. Starting simulation... +info: Entering event queue @ 2077395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2078197728000. Starting simulation... +info: Entering event queue @ 2078395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2079197728000. Starting simulation... +info: Entering event queue @ 2079395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2080197728000. Starting simulation... +info: Entering event queue @ 2080395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2081197728000. Starting simulation... +info: Entering event queue @ 2081395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2082197728000. Starting simulation... +info: Entering event queue @ 2082395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2083197728000. Starting simulation... +info: Entering event queue @ 2083395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2084197728000. Starting simulation... +info: Entering event queue @ 2084395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2085197728000. Starting simulation... +info: Entering event queue @ 2085395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2086197728000. Starting simulation... +info: Entering event queue @ 2086395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2087197728000. Starting simulation... +info: Entering event queue @ 2087395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2088197728000. Starting simulation... +info: Entering event queue @ 2088395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2089197728000. Starting simulation... +info: Entering event queue @ 2089395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2090197728000. Starting simulation... +info: Entering event queue @ 2090395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2091197728000. Starting simulation... +info: Entering event queue @ 2091395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2092197728000. Starting simulation... +info: Entering event queue @ 2092395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2093197728000. Starting simulation... +info: Entering event queue @ 2093395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2094197728000. Starting simulation... +info: Entering event queue @ 2094395524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2095197728000. Starting simulation... -info: Entering event queue @ 2095933873000. Starting simulation... +info: Entering event queue @ 2095395524000. Starting simulation... +info: Entering event queue @ 2096132143000. Starting simulation... switching cpus -info: Entering event queue @ 2095933875000. Starting simulation... +info: Entering event queue @ 2096132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2096933875000. Starting simulation... +info: Entering event queue @ 2097132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2097933875000. Starting simulation... +info: Entering event queue @ 2098132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2098933875000. Starting simulation... +info: Entering event queue @ 2099132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2099933875000. Starting simulation... +info: Entering event queue @ 2100132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2100933875000. Starting simulation... +info: Entering event queue @ 2101132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2101933875000. Starting simulation... +info: Entering event queue @ 2102132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2102933875000. Starting simulation... +info: Entering event queue @ 2103132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2103933875000. Starting simulation... +info: Entering event queue @ 2104132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2104933875000. Starting simulation... +info: Entering event queue @ 2105132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2105933875000. Starting simulation... +info: Entering event queue @ 2106132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2106933875000. Starting simulation... +info: Entering event queue @ 2107132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2107933875000. Starting simulation... +info: Entering event queue @ 2108132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2108933875000. Starting simulation... +info: Entering event queue @ 2109132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2109933875000. Starting simulation... +info: Entering event queue @ 2110132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2110933875000. Starting simulation... +info: Entering event queue @ 2111132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2111933875000. Starting simulation... +info: Entering event queue @ 2112132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2112933875000. Starting simulation... +info: Entering event queue @ 2113132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2113933875000. Starting simulation... +info: Entering event queue @ 2114132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2114933875000. Starting simulation... +info: Entering event queue @ 2115132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2115933875000. Starting simulation... +info: Entering event queue @ 2116132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2116933875000. Starting simulation... +info: Entering event queue @ 2117132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2117933875000. Starting simulation... +info: Entering event queue @ 2118132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2118933875000. Starting simulation... +info: Entering event queue @ 2119132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2119933875000. Starting simulation... +info: Entering event queue @ 2120132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2120933875000. Starting simulation... +info: Entering event queue @ 2121132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2121933875000. Starting simulation... +info: Entering event queue @ 2122132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2122933875000. Starting simulation... +info: Entering event queue @ 2123132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2123933875000. Starting simulation... +info: Entering event queue @ 2124132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2124933875000. Starting simulation... +info: Entering event queue @ 2125132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2125933875000. Starting simulation... +info: Entering event queue @ 2126132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2126933875000. Starting simulation... +info: Entering event queue @ 2127132145000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2127933875000. Starting simulation... -info: Entering event queue @ 2128670473000. Starting simulation... +info: Entering event queue @ 2128132145000. Starting simulation... +info: Entering event queue @ 2128868743000. Starting simulation... switching cpus -info: Entering event queue @ 2128670475000. Starting simulation... +info: Entering event queue @ 2128868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2129670475000. Starting simulation... +info: Entering event queue @ 2129868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2130670475000. Starting simulation... +info: Entering event queue @ 2130868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2131670475000. Starting simulation... +info: Entering event queue @ 2131868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2132670475000. Starting simulation... +info: Entering event queue @ 2132868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2133670475000. Starting simulation... +info: Entering event queue @ 2133868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2134670475000. Starting simulation... +info: Entering event queue @ 2134868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2135670475000. Starting simulation... +info: Entering event queue @ 2135868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2136670475000. Starting simulation... +info: Entering event queue @ 2136868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2137670475000. Starting simulation... +info: Entering event queue @ 2137868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2138670475000. Starting simulation... +info: Entering event queue @ 2138868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2139670475000. Starting simulation... +info: Entering event queue @ 2139868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2140670475000. Starting simulation... +info: Entering event queue @ 2140868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2141670475000. Starting simulation... +info: Entering event queue @ 2141868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2142670475000. Starting simulation... +info: Entering event queue @ 2142868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2143670475000. Starting simulation... +info: Entering event queue @ 2143868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2144670475000. Starting simulation... +info: Entering event queue @ 2144868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2145670475000. Starting simulation... +info: Entering event queue @ 2145868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2146670475000. Starting simulation... +info: Entering event queue @ 2146868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2147670475000. Starting simulation... +info: Entering event queue @ 2147868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2148670475000. Starting simulation... +info: Entering event queue @ 2148868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2149670475000. Starting simulation... +info: Entering event queue @ 2149868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2150670475000. Starting simulation... +info: Entering event queue @ 2150868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2151670475000. Starting simulation... +info: Entering event queue @ 2151868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2152670475000. Starting simulation... +info: Entering event queue @ 2152868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2153670475000. Starting simulation... +info: Entering event queue @ 2153868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2154670475000. Starting simulation... +info: Entering event queue @ 2154868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2155670475000. Starting simulation... +info: Entering event queue @ 2155868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2156670475000. Starting simulation... +info: Entering event queue @ 2156868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2157670475000. Starting simulation... +info: Entering event queue @ 2157868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2158670475000. Starting simulation... +info: Entering event queue @ 2158868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2159670475000. Starting simulation... +info: Entering event queue @ 2159868745000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2160670475000. Starting simulation... -info: Entering event queue @ 2161406305000. Starting simulation... +info: Entering event queue @ 2160868745000. Starting simulation... +info: Entering event queue @ 2161604155000. Starting simulation... switching cpus -info: Entering event queue @ 2161406307000. Starting simulation... +info: Entering event queue @ 2161604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2162406307000. Starting simulation... +info: Entering event queue @ 2162604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2163406307000. Starting simulation... +info: Entering event queue @ 2163604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2164406307000. Starting simulation... +info: Entering event queue @ 2164604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2165406307000. Starting simulation... +info: Entering event queue @ 2165604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2166406307000. Starting simulation... +info: Entering event queue @ 2166604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2167406307000. Starting simulation... +info: Entering event queue @ 2167604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2168406307000. Starting simulation... +info: Entering event queue @ 2168604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2169406307000. Starting simulation... +info: Entering event queue @ 2169604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2170406307000. Starting simulation... +info: Entering event queue @ 2170604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2171406307000. Starting simulation... +info: Entering event queue @ 2171604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2172406307000. Starting simulation... +info: Entering event queue @ 2172604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2173406307000. Starting simulation... +info: Entering event queue @ 2173604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2174406307000. Starting simulation... +info: Entering event queue @ 2174604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2175406307000. Starting simulation... +info: Entering event queue @ 2175604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2176406307000. Starting simulation... +info: Entering event queue @ 2176604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2177406307000. Starting simulation... +info: Entering event queue @ 2177604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2178406307000. Starting simulation... +info: Entering event queue @ 2178604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2179406307000. Starting simulation... +info: Entering event queue @ 2179604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2180406307000. Starting simulation... +info: Entering event queue @ 2180604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2181406307000. Starting simulation... +info: Entering event queue @ 2181604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2182406307000. Starting simulation... +info: Entering event queue @ 2182604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2183406307000. Starting simulation... +info: Entering event queue @ 2183604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2184406307000. Starting simulation... +info: Entering event queue @ 2184604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2185406307000. Starting simulation... +info: Entering event queue @ 2185604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2186406307000. Starting simulation... +info: Entering event queue @ 2186604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2187406307000. Starting simulation... +info: Entering event queue @ 2187604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2188406307000. Starting simulation... +info: Entering event queue @ 2188604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2189406307000. Starting simulation... +info: Entering event queue @ 2189604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2190406307000. Starting simulation... +info: Entering event queue @ 2190604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2191406307000. Starting simulation... +info: Entering event queue @ 2191604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2192406307000. Starting simulation... +info: Entering event queue @ 2192604157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2193406307000. Starting simulation... -info: Entering event queue @ 2194142905000. Starting simulation... +info: Entering event queue @ 2193604157000. Starting simulation... +info: Entering event queue @ 2194340734000. Starting simulation... switching cpus -info: Entering event queue @ 2194142907000. Starting simulation... +info: Entering event queue @ 2194340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2195142907000. Starting simulation... +info: Entering event queue @ 2195340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2196142907000. Starting simulation... +info: Entering event queue @ 2196340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2197142907000. Starting simulation... +info: Entering event queue @ 2197340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2198142907000. Starting simulation... +info: Entering event queue @ 2198340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2199142907000. Starting simulation... +info: Entering event queue @ 2199340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2200142907000. Starting simulation... +info: Entering event queue @ 2200340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2201142907000. Starting simulation... +info: Entering event queue @ 2201340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2202142907000. Starting simulation... +info: Entering event queue @ 2202340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2203142907000. Starting simulation... +info: Entering event queue @ 2203340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2204142907000. Starting simulation... +info: Entering event queue @ 2204340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2205142907000. Starting simulation... +info: Entering event queue @ 2205340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2206142907000. Starting simulation... +info: Entering event queue @ 2206340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2207142907000. Starting simulation... +info: Entering event queue @ 2207340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2208142907000. Starting simulation... +info: Entering event queue @ 2208340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2209142907000. Starting simulation... +info: Entering event queue @ 2209340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2210142907000. Starting simulation... +info: Entering event queue @ 2210340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2211142907000. Starting simulation... +info: Entering event queue @ 2211340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2212142907000. Starting simulation... +info: Entering event queue @ 2212340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2213142907000. Starting simulation... +info: Entering event queue @ 2213340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2214142907000. Starting simulation... +info: Entering event queue @ 2214340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2215142907000. Starting simulation... +info: Entering event queue @ 2215340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2216142907000. Starting simulation... +info: Entering event queue @ 2216340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2217142907000. Starting simulation... +info: Entering event queue @ 2217340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2218142907000. Starting simulation... +info: Entering event queue @ 2218340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2219142907000. Starting simulation... +info: Entering event queue @ 2219340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2220142907000. Starting simulation... +info: Entering event queue @ 2220340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2221142907000. Starting simulation... +info: Entering event queue @ 2221340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2222142907000. Starting simulation... +info: Entering event queue @ 2222340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2223142907000. Starting simulation... +info: Entering event queue @ 2223340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2224142907000. Starting simulation... +info: Entering event queue @ 2224340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2225142907000. Starting simulation... +info: Entering event queue @ 2225340736000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2226142907000. Starting simulation... -info: Entering event queue @ 2226879196000. Starting simulation... +info: Entering event queue @ 2226340736000. Starting simulation... +info: Entering event queue @ 2227077334000. Starting simulation... switching cpus -info: Entering event queue @ 2226879198000. Starting simulation... +info: Entering event queue @ 2227077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2227879198000. Starting simulation... +info: Entering event queue @ 2228077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2228879198000. Starting simulation... +info: Entering event queue @ 2229077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2229879198000. Starting simulation... +info: Entering event queue @ 2230077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2230879198000. Starting simulation... +info: Entering event queue @ 2231077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2231879198000. Starting simulation... +info: Entering event queue @ 2232077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2232879198000. Starting simulation... +info: Entering event queue @ 2233077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2233879198000. Starting simulation... +info: Entering event queue @ 2234077336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2234879198000. Starting simulation... +info: Entering event queue @ 2235077336000. Starting simulation... switching cpus -info: Entering event queue @ 2234879199000. Starting simulation... +info: Entering event queue @ 2235077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2235879199000. Starting simulation... +info: Entering event queue @ 2236077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2236879199000. Starting simulation... +info: Entering event queue @ 2237077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2237879199000. Starting simulation... +info: Entering event queue @ 2238077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2238879199000. Starting simulation... +info: Entering event queue @ 2239077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2239879199000. Starting simulation... +info: Entering event queue @ 2240077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2240879199000. Starting simulation... +info: Entering event queue @ 2241077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2241879199000. Starting simulation... +info: Entering event queue @ 2242077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2242879199000. Starting simulation... +info: Entering event queue @ 2243077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2243879199000. Starting simulation... +info: Entering event queue @ 2244077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2244879199000. Starting simulation... +info: Entering event queue @ 2245077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2245879199000. Starting simulation... +info: Entering event queue @ 2246077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2246879199000. Starting simulation... +info: Entering event queue @ 2247077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2247879199000. Starting simulation... +info: Entering event queue @ 2248077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2248879199000. Starting simulation... +info: Entering event queue @ 2249077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2249879199000. Starting simulation... +info: Entering event queue @ 2250077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2250879199000. Starting simulation... +info: Entering event queue @ 2251077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2251879199000. Starting simulation... +info: Entering event queue @ 2252077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2252879199000. Starting simulation... +info: Entering event queue @ 2253077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2253879199000. Starting simulation... +info: Entering event queue @ 2254077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2254879199000. Starting simulation... +info: Entering event queue @ 2255077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2255879199000. Starting simulation... +info: Entering event queue @ 2256077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2256879199000. Starting simulation... +info: Entering event queue @ 2257077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2257879199000. Starting simulation... +info: Entering event queue @ 2258077343500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2258879199000. Starting simulation... -info: Entering event queue @ 2259615337000. Starting simulation... +info: Entering event queue @ 2259077343500. Starting simulation... +info: Entering event queue @ 2259812939000. Starting simulation... switching cpus -info: Entering event queue @ 2259615339000. Starting simulation... +info: Entering event queue @ 2259812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2260615339000. Starting simulation... +info: Entering event queue @ 2260812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2261615339000. Starting simulation... +info: Entering event queue @ 2261812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2262615339000. Starting simulation... +info: Entering event queue @ 2262812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2263615339000. Starting simulation... +info: Entering event queue @ 2263812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2264615339000. Starting simulation... +info: Entering event queue @ 2264812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2265615339000. Starting simulation... +info: Entering event queue @ 2265812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2266615339000. Starting simulation... +info: Entering event queue @ 2266812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2267615339000. Starting simulation... +info: Entering event queue @ 2267812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2268615339000. Starting simulation... +info: Entering event queue @ 2268812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2269615339000. Starting simulation... +info: Entering event queue @ 2269812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2270615339000. Starting simulation... +info: Entering event queue @ 2270812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2271615339000. Starting simulation... +info: Entering event queue @ 2271812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2272615339000. Starting simulation... +info: Entering event queue @ 2272812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2273615339000. Starting simulation... +info: Entering event queue @ 2273812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2274615339000. Starting simulation... +info: Entering event queue @ 2274812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2275615339000. Starting simulation... +info: Entering event queue @ 2275812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2276615339000. Starting simulation... +info: Entering event queue @ 2276812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2277615339000. Starting simulation... +info: Entering event queue @ 2277812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2278615339000. Starting simulation... +info: Entering event queue @ 2278812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2279615339000. Starting simulation... +info: Entering event queue @ 2279812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2280615339000. Starting simulation... +info: Entering event queue @ 2280812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2281615339000. Starting simulation... +info: Entering event queue @ 2281812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2282615339000. Starting simulation... +info: Entering event queue @ 2282812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2283615339000. Starting simulation... +info: Entering event queue @ 2283812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2284615339000. Starting simulation... +info: Entering event queue @ 2284812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2285615339000. Starting simulation... +info: Entering event queue @ 2285812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2286615339000. Starting simulation... +info: Entering event queue @ 2286812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2287615339000. Starting simulation... +info: Entering event queue @ 2287812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2288615339000. Starting simulation... +info: Entering event queue @ 2288812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2289615339000. Starting simulation... +info: Entering event queue @ 2289812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2290615339000. Starting simulation... +info: Entering event queue @ 2290812941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2291615339000. Starting simulation... -info: Entering event queue @ 2292351631000. Starting simulation... +info: Entering event queue @ 2291812941000. Starting simulation... +info: Entering event queue @ 2292549539000. Starting simulation... switching cpus -info: Entering event queue @ 2292351633000. Starting simulation... +info: Entering event queue @ 2292549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2293351633000. Starting simulation... +info: Entering event queue @ 2293549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2294351633000. Starting simulation... +info: Entering event queue @ 2294549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2295351633000. Starting simulation... +info: Entering event queue @ 2295549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2296351633000. Starting simulation... +info: Entering event queue @ 2296549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2297351633000. Starting simulation... +info: Entering event queue @ 2297549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2298351633000. Starting simulation... +info: Entering event queue @ 2298549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2299351633000. Starting simulation... +info: Entering event queue @ 2299549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2300351633000. Starting simulation... +info: Entering event queue @ 2300549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2301351633000. Starting simulation... +info: Entering event queue @ 2301549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2302351633000. Starting simulation... +info: Entering event queue @ 2302549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2303351633000. Starting simulation... +info: Entering event queue @ 2303549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2304351633000. Starting simulation... +info: Entering event queue @ 2304549541000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2305351633000. Starting simulation... +info: Entering event queue @ 2305549541000. Starting simulation... switching cpus -info: Entering event queue @ 2305351696000. Starting simulation... +info: Entering event queue @ 2305549582000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2306351696000. Starting simulation... +info: Entering event queue @ 2306549582000. Starting simulation... switching cpus -info: Entering event queue @ 2306351697000. Starting simulation... +info: Entering event queue @ 2306549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2307351697000. Starting simulation... +info: Entering event queue @ 2307549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2308351697000. Starting simulation... +info: Entering event queue @ 2308549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2309351697000. Starting simulation... +info: Entering event queue @ 2309549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2310351697000. Starting simulation... +info: Entering event queue @ 2310549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2311351697000. Starting simulation... +info: Entering event queue @ 2311549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2312351697000. Starting simulation... +info: Entering event queue @ 2312549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2313351697000. Starting simulation... +info: Entering event queue @ 2313549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2314351697000. Starting simulation... +info: Entering event queue @ 2314549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2315351697000. Starting simulation... +info: Entering event queue @ 2315549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2316351697000. Starting simulation... +info: Entering event queue @ 2316549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2317351697000. Starting simulation... +info: Entering event queue @ 2317549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2318351697000. Starting simulation... +info: Entering event queue @ 2318549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2319351697000. Starting simulation... +info: Entering event queue @ 2319549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2320351697000. Starting simulation... +info: Entering event queue @ 2320549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2321351697000. Starting simulation... +info: Entering event queue @ 2321549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2322351697000. Starting simulation... +info: Entering event queue @ 2322549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2323351697000. Starting simulation... +info: Entering event queue @ 2323549589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2324351697000. Starting simulation... -info: Entering event queue @ 2325088231000. Starting simulation... +info: Entering event queue @ 2324549589500. Starting simulation... +info: Entering event queue @ 2325286118000. Starting simulation... +info: Entering event queue @ 2325286124000. Starting simulation... switching cpus -info: Entering event queue @ 2325088237000. Starting simulation... +info: Entering event queue @ 2325286125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2326088237000. Starting simulation... +info: Entering event queue @ 2326286125500. Starting simulation... switching cpus -info: Entering event queue @ 2326088238500. Starting simulation... +info: Entering event queue @ 2326286133000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2327088238500. Starting simulation... +info: Entering event queue @ 2327286133000. Starting simulation... switching cpus -info: Entering event queue @ 2327088324000. Starting simulation... +info: Entering event queue @ 2327286140500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2328088324000. Starting simulation... +info: Entering event queue @ 2328286140500. Starting simulation... switching cpus -info: Entering event queue @ 2328088325000. Starting simulation... +info: Entering event queue @ 2328286186000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2329088325000. Starting simulation... +info: Entering event queue @ 2329286186000. Starting simulation... switching cpus -info: Entering event queue @ 2329088480000. Starting simulation... +info: Entering event queue @ 2329286223000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2330088480000. Starting simulation... +info: Entering event queue @ 2330286223000. Starting simulation... switching cpus -info: Entering event queue @ 2330088481000. Starting simulation... +info: Entering event queue @ 2330286230500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2331088481000. Starting simulation... +info: Entering event queue @ 2331286230500. Starting simulation... switching cpus -info: Entering event queue @ 2331088482000. Starting simulation... +info: Entering event queue @ 2331286254000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2332088482000. Starting simulation... +info: Entering event queue @ 2332286254000. Starting simulation... switching cpus -info: Entering event queue @ 2332088483000. Starting simulation... +info: Entering event queue @ 2332286408000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2333088483000. Starting simulation... +info: Entering event queue @ 2333286408000. Starting simulation... switching cpus -info: Entering event queue @ 2333088484000. Starting simulation... +info: Entering event queue @ 2333286415500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2334088484000. Starting simulation... +info: Entering event queue @ 2334286415500. Starting simulation... switching cpus -info: Entering event queue @ 2334088485000. Starting simulation... +info: Entering event queue @ 2334286517000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2335088485000. Starting simulation... +info: Entering event queue @ 2335286517000. Starting simulation... switching cpus -info: Entering event queue @ 2335088511000. Starting simulation... +info: Entering event queue @ 2335286619000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2336088511000. Starting simulation... +info: Entering event queue @ 2336286619000. Starting simulation... switching cpus -info: Entering event queue @ 2336088552000. Starting simulation... +info: Entering event queue @ 2336286772000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2337088552000. Starting simulation... +info: Entering event queue @ 2337286772000. Starting simulation... switching cpus -info: Entering event queue @ 2337088554000. Starting simulation... +info: Entering event queue @ 2337286779500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2338088554000. Starting simulation... +info: Entering event queue @ 2338286779500. Starting simulation... switching cpus -info: Entering event queue @ 2338088597000. Starting simulation... +info: Entering event queue @ 2338286858000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2339088597000. Starting simulation... +info: Entering event queue @ 2339286858000. Starting simulation... switching cpus -info: Entering event queue @ 2339088612000. Starting simulation... +info: Entering event queue @ 2339286865500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2340088612000. Starting simulation... +info: Entering event queue @ 2340286865500. Starting simulation... switching cpus -info: Entering event queue @ 2340088674000. Starting simulation... +info: Entering event queue @ 2340286954000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2341088674000. Starting simulation... +info: Entering event queue @ 2341286954000. Starting simulation... switching cpus -info: Entering event queue @ 2341088772000. Starting simulation... +info: Entering event queue @ 2341287003000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2342088772000. Starting simulation... +info: Entering event queue @ 2342287003000. Starting simulation... switching cpus -info: Entering event queue @ 2342088773000. Starting simulation... +info: Entering event queue @ 2342287101000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2343088773000. Starting simulation... +info: Entering event queue @ 2343287101000. Starting simulation... switching cpus -info: Entering event queue @ 2343088775000. Starting simulation... +info: Entering event queue @ 2343287108500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2344088775000. Starting simulation... +info: Entering event queue @ 2344287108500. Starting simulation... switching cpus -info: Entering event queue @ 2344088789000. Starting simulation... +info: Entering event queue @ 2344287231000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2345088789000. Starting simulation... +info: Entering event queue @ 2345287231000. Starting simulation... switching cpus -info: Entering event queue @ 2345088919000. Starting simulation... +info: Entering event queue @ 2345287255000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2346088919000. Starting simulation... +info: Entering event queue @ 2346287255000. Starting simulation... switching cpus -info: Entering event queue @ 2346088990000. Starting simulation... +info: Entering event queue @ 2346287350000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2347088990000. Starting simulation... +info: Entering event queue @ 2347287350000. Starting simulation... switching cpus -info: Entering event queue @ 2347089092000. Starting simulation... +info: Entering event queue @ 2347287397000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2348089092000. Starting simulation... +info: Entering event queue @ 2348287397000. Starting simulation... switching cpus -info: Entering event queue @ 2348089095500. Starting simulation... +info: Entering event queue @ 2348287404500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2349089095500. Starting simulation... +info: Entering event queue @ 2349287404500. Starting simulation... switching cpus -info: Entering event queue @ 2349089096500. Starting simulation... +info: Entering event queue @ 2349287448000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2350089096500. Starting simulation... +info: Entering event queue @ 2350287448000. Starting simulation... switching cpus -info: Entering event queue @ 2350089098500. Starting simulation... +info: Entering event queue @ 2350287455500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2351089098500. Starting simulation... +info: Entering event queue @ 2351287455500. Starting simulation... switching cpus -info: Entering event queue @ 2351089113000. Starting simulation... +info: Entering event queue @ 2351287463000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2352089113000. Starting simulation... +info: Entering event queue @ 2352287463000. Starting simulation... switching cpus -info: Entering event queue @ 2352089199000. Starting simulation... +info: Entering event queue @ 2352287470500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2353089199000. Starting simulation... +info: Entering event queue @ 2353287470500. Starting simulation... switching cpus -info: Entering event queue @ 2353089200000. Starting simulation... +info: Entering event queue @ 2353287572000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2354089200000. Starting simulation... +info: Entering event queue @ 2354287572000. Starting simulation... switching cpus -info: Entering event queue @ 2354089248000. Starting simulation... +info: Entering event queue @ 2354287703000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2355089248000. Starting simulation... +info: Entering event queue @ 2355287703000. Starting simulation... switching cpus -info: Entering event queue @ 2355089265000. Starting simulation... +info: Entering event queue @ 2355287710500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2356089265000. Starting simulation... +info: Entering event queue @ 2356287710500. Starting simulation... switching cpus -info: Entering event queue @ 2356089316000. Starting simulation... +info: Entering event queue @ 2356287765000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2357089316000. Starting simulation... -info: Entering event queue @ 2357824372000. Starting simulation... +info: Entering event queue @ 2357287765000. Starting simulation... +info: Entering event queue @ 2358021530000. Starting simulation... switching cpus -info: Entering event queue @ 2357824374000. Starting simulation... +info: Entering event queue @ 2358021532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2358824374000. Starting simulation... +info: Entering event queue @ 2359021532000. Starting simulation... switching cpus -info: Entering event queue @ 2358824488000. Starting simulation... +info: Entering event queue @ 2359021676000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2359824488000. Starting simulation... +info: Entering event queue @ 2360021676000. Starting simulation... switching cpus -info: Entering event queue @ 2359824489000. Starting simulation... +info: Entering event queue @ 2360021831000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2360824489000. Starting simulation... +info: Entering event queue @ 2361021831000. Starting simulation... switching cpus -info: Entering event queue @ 2360824618000. Starting simulation... +info: Entering event queue @ 2361021907000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2361824618000. Starting simulation... +info: Entering event queue @ 2362021907000. Starting simulation... switching cpus -info: Entering event queue @ 2361824637000. Starting simulation... +info: Entering event queue @ 2362021914500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2362824637000. Starting simulation... +info: Entering event queue @ 2363021914500. Starting simulation... switching cpus -info: Entering event queue @ 2362824638000. Starting simulation... +info: Entering event queue @ 2363021992000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2363824638000. Starting simulation... +info: Entering event queue @ 2364021992000. Starting simulation... switching cpus -info: Entering event queue @ 2363824687000. Starting simulation... +info: Entering event queue @ 2364022007000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2364824687000. Starting simulation... +info: Entering event queue @ 2365022007000. Starting simulation... switching cpus -info: Entering event queue @ 2364824823000. Starting simulation... +info: Entering event queue @ 2365022014500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2365824823000. Starting simulation... +info: Entering event queue @ 2366022014500. Starting simulation... switching cpus -info: Entering event queue @ 2365824964000. Starting simulation... +info: Entering event queue @ 2366022027000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2366824964000. Starting simulation... +info: Entering event queue @ 2367022027000. Starting simulation... switching cpus -info: Entering event queue @ 2366824989000. Starting simulation... +info: Entering event queue @ 2367022117000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2367824989000. Starting simulation... +info: Entering event queue @ 2368022117000. Starting simulation... switching cpus -info: Entering event queue @ 2367825012000. Starting simulation... +info: Entering event queue @ 2368022124500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2368825012000. Starting simulation... +info: Entering event queue @ 2369022124500. Starting simulation... switching cpus -info: Entering event queue @ 2368825145000. Starting simulation... +info: Entering event queue @ 2369022270000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2369825145000. Starting simulation... +info: Entering event queue @ 2370022270000. Starting simulation... switching cpus -info: Entering event queue @ 2369825146000. Starting simulation... +info: Entering event queue @ 2370022277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2370825146000. Starting simulation... +info: Entering event queue @ 2371022277500. Starting simulation... switching cpus -info: Entering event queue @ 2370825288000. Starting simulation... +info: Entering event queue @ 2371022285000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2371825288000. Starting simulation... +info: Entering event queue @ 2372022285000. Starting simulation... switching cpus -info: Entering event queue @ 2371825289000. Starting simulation... +info: Entering event queue @ 2372022414000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2372825289000. Starting simulation... +info: Entering event queue @ 2373022414000. Starting simulation... switching cpus -info: Entering event queue @ 2372825296000. Starting simulation... +info: Entering event queue @ 2373022432000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2373825296000. Starting simulation... +info: Entering event queue @ 2374022432000. Starting simulation... switching cpus -info: Entering event queue @ 2373825361000. Starting simulation... +info: Entering event queue @ 2374022439500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2374825361000. Starting simulation... +info: Entering event queue @ 2375022439500. Starting simulation... switching cpus -info: Entering event queue @ 2374825463000. Starting simulation... +info: Entering event queue @ 2375022569000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2375825463000. Starting simulation... +info: Entering event queue @ 2376022569000. Starting simulation... switching cpus -info: Entering event queue @ 2375825612000. Starting simulation... +info: Entering event queue @ 2376022686000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2376825612000. Starting simulation... +info: Entering event queue @ 2377022686000. Starting simulation... switching cpus -info: Entering event queue @ 2376825684000. Starting simulation... +info: Entering event queue @ 2377022827000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2377825684000. Starting simulation... +info: Entering event queue @ 2378022827000. Starting simulation... switching cpus -info: Entering event queue @ 2377825750000. Starting simulation... +info: Entering event queue @ 2378022982000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2378825750000. Starting simulation... +info: Entering event queue @ 2379022982000. Starting simulation... switching cpus -info: Entering event queue @ 2378825867000. Starting simulation... +info: Entering event queue @ 2379023037000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2379825867000. Starting simulation... +info: Entering event queue @ 2380023037000. Starting simulation... switching cpus -info: Entering event queue @ 2379825907000. Starting simulation... +info: Entering event queue @ 2380023062000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2380825907000. Starting simulation... +info: Entering event queue @ 2381023062000. Starting simulation... switching cpus -info: Entering event queue @ 2380825985000. Starting simulation... +info: Entering event queue @ 2381023069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2381825985000. Starting simulation... +info: Entering event queue @ 2382023069500. Starting simulation... switching cpus -info: Entering event queue @ 2381826127000. Starting simulation... +info: Entering event queue @ 2382023080500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2382826127000. Starting simulation... +info: Entering event queue @ 2383023080500. Starting simulation... switching cpus -info: Entering event queue @ 2382826217000. Starting simulation... +info: Entering event queue @ 2383023209000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2383826217000. Starting simulation... +info: Entering event queue @ 2384023209000. Starting simulation... switching cpus -info: Entering event queue @ 2383826218000. Starting simulation... +info: Entering event queue @ 2384023216500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2384826218000. Starting simulation... +info: Entering event queue @ 2385023216500. Starting simulation... switching cpus -info: Entering event queue @ 2384826219000. Starting simulation... +info: Entering event queue @ 2385023294000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2385826219000. Starting simulation... +info: Entering event queue @ 2386023294000. Starting simulation... switching cpus -info: Entering event queue @ 2385826249000. Starting simulation... +info: Entering event queue @ 2386023307500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2386826249000. Starting simulation... +info: Entering event queue @ 2387023307500. Starting simulation... switching cpus -info: Entering event queue @ 2386826330000. Starting simulation... +info: Entering event queue @ 2387023398000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2387826330000. Starting simulation... +info: Entering event queue @ 2388023398000. Starting simulation... switching cpus -info: Entering event queue @ 2387826331000. Starting simulation... +info: Entering event queue @ 2388023422000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2388826331000. Starting simulation... +info: Entering event queue @ 2389023422000. Starting simulation... switching cpus -info: Entering event queue @ 2388826388000. Starting simulation... +info: Entering event queue @ 2389023429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2389826388000. Starting simulation... -info: Entering event queue @ 2390560663000. Starting simulation... +info: Entering event queue @ 2390023429500. Starting simulation... +info: Entering event queue @ 2390758151000. Starting simulation... switching cpus -info: Entering event queue @ 2390560665000. Starting simulation... +info: Entering event queue @ 2390758153000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2391560665000. Starting simulation... +info: Entering event queue @ 2391758153000. Starting simulation... switching cpus -info: Entering event queue @ 2391560666000. Starting simulation... +info: Entering event queue @ 2391758161000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2392560666000. Starting simulation... +info: Entering event queue @ 2392758161000. Starting simulation... switching cpus -info: Entering event queue @ 2392560703000. Starting simulation... +info: Entering event queue @ 2392758168500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2393560703000. Starting simulation... +info: Entering event queue @ 2393758168500. Starting simulation... switching cpus -info: Entering event queue @ 2393560798000. Starting simulation... +info: Entering event queue @ 2393758292000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2394560798000. Starting simulation... +info: Entering event queue @ 2394758292000. Starting simulation... switching cpus -info: Entering event queue @ 2394560799000. Starting simulation... +info: Entering event queue @ 2394758302000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2395560799000. Starting simulation... +info: Entering event queue @ 2395758302000. Starting simulation... switching cpus -info: Entering event queue @ 2395560928000. Starting simulation... +info: Entering event queue @ 2395758458000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2396560928000. Starting simulation... +info: Entering event queue @ 2396758458000. Starting simulation... switching cpus -info: Entering event queue @ 2396561075000. Starting simulation... +info: Entering event queue @ 2396758470000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2397561075000. Starting simulation... +info: Entering event queue @ 2397758470000. Starting simulation... switching cpus -info: Entering event queue @ 2397561139000. Starting simulation... +info: Entering event queue @ 2397758606000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2398561139000. Starting simulation... +info: Entering event queue @ 2398758606000. Starting simulation... switching cpus -info: Entering event queue @ 2398561189000. Starting simulation... +info: Entering event queue @ 2398758753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2399561189000. Starting simulation... +info: Entering event queue @ 2399758753000. Starting simulation... switching cpus -info: Entering event queue @ 2399561344000. Starting simulation... +info: Entering event queue @ 2399758906000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2400561344000. Starting simulation... +info: Entering event queue @ 2400758906000. Starting simulation... switching cpus -info: Entering event queue @ 2400561484000. Starting simulation... +info: Entering event queue @ 2400759041000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2401561484000. Starting simulation... +info: Entering event queue @ 2401759041000. Starting simulation... switching cpus -info: Entering event queue @ 2401561534000. Starting simulation... +info: Entering event queue @ 2401759189000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2402561534000. Starting simulation... +info: Entering event queue @ 2402759189000. Starting simulation... switching cpus -info: Entering event queue @ 2402561628000. Starting simulation... +info: Entering event queue @ 2402759220000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2403561628000. Starting simulation... +info: Entering event queue @ 2403759220000. Starting simulation... switching cpus -info: Entering event queue @ 2403561712000. Starting simulation... +info: Entering event queue @ 2403759362000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2404561712000. Starting simulation... +info: Entering event queue @ 2404759362000. Starting simulation... switching cpus -info: Entering event queue @ 2404561726000. Starting simulation... +info: Entering event queue @ 2404759454000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2405561726000. Starting simulation... +info: Entering event queue @ 2405759454000. Starting simulation... switching cpus -info: Entering event queue @ 2405561835000. Starting simulation... +info: Entering event queue @ 2405759609000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2406561835000. Starting simulation... +info: Entering event queue @ 2406759609000. Starting simulation... switching cpus -info: Entering event queue @ 2406561960000. Starting simulation... +info: Entering event queue @ 2406759693000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2407561960000. Starting simulation... +info: Entering event queue @ 2407759693000. Starting simulation... switching cpus -info: Entering event queue @ 2407562071000. Starting simulation... +info: Entering event queue @ 2407759791000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2408562071000. Starting simulation... +info: Entering event queue @ 2408759791000. Starting simulation... switching cpus -info: Entering event queue @ 2408562185000. Starting simulation... +info: Entering event queue @ 2408759806000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2409562185000. Starting simulation... +info: Entering event queue @ 2409759806000. Starting simulation... switching cpus -info: Entering event queue @ 2409562309000. Starting simulation... +info: Entering event queue @ 2409759845000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2410562309000. Starting simulation... +info: Entering event queue @ 2410759845000. Starting simulation... switching cpus -info: Entering event queue @ 2410562346000. Starting simulation... +info: Entering event queue @ 2410759950000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2411562346000. Starting simulation... +info: Entering event queue @ 2411759950000. Starting simulation... switching cpus -info: Entering event queue @ 2411562485000. Starting simulation... +info: Entering event queue @ 2411759976000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2412562485000. Starting simulation... +info: Entering event queue @ 2412759976000. Starting simulation... switching cpus -info: Entering event queue @ 2412562486000. Starting simulation... +info: Entering event queue @ 2412759983500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2413562486000. Starting simulation... +info: Entering event queue @ 2413759983500. Starting simulation... switching cpus -info: Entering event queue @ 2413562559000. Starting simulation... +info: Entering event queue @ 2413760084000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2414562559000. Starting simulation... +info: Entering event queue @ 2414760084000. Starting simulation... switching cpus -info: Entering event queue @ 2414562654000. Starting simulation... +info: Entering event queue @ 2414760142000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2415562654000. Starting simulation... +info: Entering event queue @ 2415760142000. Starting simulation... switching cpus -info: Entering event queue @ 2415562655000. Starting simulation... +info: Entering event queue @ 2415760169000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2416562655000. Starting simulation... +info: Entering event queue @ 2416760169000. Starting simulation... switching cpus -info: Entering event queue @ 2416562810000. Starting simulation... +info: Entering event queue @ 2416760278000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2417562810000. Starting simulation... +info: Entering event queue @ 2417760278000. Starting simulation... switching cpus -info: Entering event queue @ 2417562871000. Starting simulation... +info: Entering event queue @ 2417760378000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2418562871000. Starting simulation... +info: Entering event queue @ 2418760378000. Starting simulation... switching cpus -info: Entering event queue @ 2418562872000. Starting simulation... +info: Entering event queue @ 2418760524000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2419562872000. Starting simulation... +info: Entering event queue @ 2419760524000. Starting simulation... switching cpus -info: Entering event queue @ 2419562919000. Starting simulation... +info: Entering event queue @ 2419760601000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2420562919000. Starting simulation... +info: Entering event queue @ 2420760601000. Starting simulation... switching cpus -info: Entering event queue @ 2420562986000. Starting simulation... +info: Entering event queue @ 2420760619000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2421562986000. Starting simulation... +info: Entering event queue @ 2421760619000. Starting simulation... switching cpus -info: Entering event queue @ 2421562987000. Starting simulation... +info: Entering event queue @ 2421760647000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2422562987000. Starting simulation... -info: Entering event queue @ 2423297572000. Starting simulation... +info: Entering event queue @ 2422760647000. Starting simulation... +info: Entering event queue @ 2423494730000. Starting simulation... switching cpus -info: Entering event queue @ 2423297574000. Starting simulation... +info: Entering event queue @ 2423494732000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2424297574000. Starting simulation... +info: Entering event queue @ 2424494732000. Starting simulation... switching cpus -info: Entering event queue @ 2424297699000. Starting simulation... +info: Entering event queue @ 2424494817000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2425297699000. Starting simulation... switching cpus -info: Entering event queue @ 2425297786000. Starting simulation... +info: Entering event queue @ 2425494817000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2426297786000. Starting simulation... +info: Entering event queue @ 2426494817000. Starting simulation... switching cpus -info: Entering event queue @ 2426297856000. Starting simulation... +info: Entering event queue @ 2426494898000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2427297856000. Starting simulation... +info: Entering event queue @ 2427494898000. Starting simulation... switching cpus -info: Entering event queue @ 2427298009000. Starting simulation... +info: Entering event queue @ 2427494973000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2428298009000. Starting simulation... +info: Entering event queue @ 2428494973000. Starting simulation... switching cpus -info: Entering event queue @ 2428298043000. Starting simulation... +info: Entering event queue @ 2428494980500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2429298043000. Starting simulation... +info: Entering event queue @ 2429494980500. Starting simulation... switching cpus -info: Entering event queue @ 2429298115000. Starting simulation... +info: Entering event queue @ 2429495036000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2430298115000. Starting simulation... +info: Entering event queue @ 2430495036000. Starting simulation... switching cpus -info: Entering event queue @ 2430298116000. Starting simulation... +info: Entering event queue @ 2430495139000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2431298116000. Starting simulation... +info: Entering event queue @ 2431495139000. Starting simulation... switching cpus -info: Entering event queue @ 2431298128000. Starting simulation... +info: Entering event queue @ 2431495146500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2432298128000. Starting simulation... +info: Entering event queue @ 2432495146500. Starting simulation... switching cpus -info: Entering event queue @ 2432298154000. Starting simulation... +info: Entering event queue @ 2432495281000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2433298154000. Starting simulation... +info: Entering event queue @ 2433495281000. Starting simulation... switching cpus -info: Entering event queue @ 2433298155000. Starting simulation... +info: Entering event queue @ 2433495390000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2434298155000. Starting simulation... +info: Entering event queue @ 2434495390000. Starting simulation... switching cpus -info: Entering event queue @ 2434298209000. Starting simulation... +info: Entering event queue @ 2434495397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2435298209000. Starting simulation... +info: Entering event queue @ 2435495397500. Starting simulation... switching cpus -info: Entering event queue @ 2435298264000. Starting simulation... +info: Entering event queue @ 2435495416000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2436298264000. Starting simulation... +info: Entering event queue @ 2436495416000. Starting simulation... switching cpus -info: Entering event queue @ 2436298295000. Starting simulation... +info: Entering event queue @ 2436495532000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2437298295000. Starting simulation... +info: Entering event queue @ 2437495532000. Starting simulation... switching cpus -info: Entering event queue @ 2437298393000. Starting simulation... +info: Entering event queue @ 2437495571000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2438298393000. Starting simulation... +info: Entering event queue @ 2438495571000. Starting simulation... switching cpus -info: Entering event queue @ 2438298535000. Starting simulation... +info: Entering event queue @ 2438495727000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2439298535000. Starting simulation... +info: Entering event queue @ 2439495727000. Starting simulation... switching cpus -info: Entering event queue @ 2439298588000. Starting simulation... +info: Entering event queue @ 2439495866000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2440298588000. Starting simulation... +info: Entering event queue @ 2440495866000. Starting simulation... switching cpus -info: Entering event queue @ 2440298715000. Starting simulation... +info: Entering event queue @ 2440495930000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2441298715000. Starting simulation... +info: Entering event queue @ 2441495930000. Starting simulation... switching cpus -info: Entering event queue @ 2441298826000. Starting simulation... +info: Entering event queue @ 2441495956000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2442298826000. Starting simulation... +info: Entering event queue @ 2442495956000. Starting simulation... switching cpus -info: Entering event queue @ 2442298827000. Starting simulation... +info: Entering event queue @ 2442496014000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2443298827000. Starting simulation... +info: Entering event queue @ 2443496014000. Starting simulation... switching cpus -info: Entering event queue @ 2443298920000. Starting simulation... +info: Entering event queue @ 2443496047000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2444298920000. Starting simulation... +info: Entering event queue @ 2444496047000. Starting simulation... switching cpus -info: Entering event queue @ 2444298968000. Starting simulation... +info: Entering event queue @ 2444496070000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2445298968000. Starting simulation... +info: Entering event queue @ 2445496070000. Starting simulation... switching cpus -info: Entering event queue @ 2445298969000. Starting simulation... +info: Entering event queue @ 2445496224000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2446298969000. Starting simulation... +info: Entering event queue @ 2446496224000. Starting simulation... switching cpus -info: Entering event queue @ 2446299109000. Starting simulation... +info: Entering event queue @ 2446496340000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2447299109000. Starting simulation... +info: Entering event queue @ 2447496340000. Starting simulation... switching cpus -info: Entering event queue @ 2447299228000. Starting simulation... +info: Entering event queue @ 2447496437000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2448299228000. Starting simulation... +info: Entering event queue @ 2448496437000. Starting simulation... switching cpus -info: Entering event queue @ 2448299344000. Starting simulation... +info: Entering event queue @ 2448496470000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2449299344000. Starting simulation... +info: Entering event queue @ 2449496470000. Starting simulation... switching cpus -info: Entering event queue @ 2449299491000. Starting simulation... +info: Entering event queue @ 2449496529000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2450299491000. Starting simulation... +info: Entering event queue @ 2450496529000. Starting simulation... switching cpus -info: Entering event queue @ 2450299553000. Starting simulation... +info: Entering event queue @ 2450496616000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2451299553000. Starting simulation... +info: Entering event queue @ 2451496616000. Starting simulation... switching cpus -info: Entering event queue @ 2451299683000. Starting simulation... +info: Entering event queue @ 2451496657000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2452299683000. Starting simulation... +info: Entering event queue @ 2452496657000. Starting simulation... switching cpus -info: Entering event queue @ 2452299768000. Starting simulation... +info: Entering event queue @ 2452496803000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2453299768000. Starting simulation... +info: Entering event queue @ 2453496803000. Starting simulation... switching cpus -info: Entering event queue @ 2453299890000. Starting simulation... +info: Entering event queue @ 2453496810500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2454299890000. Starting simulation... +info: Entering event queue @ 2454496810500. Starting simulation... switching cpus -info: Entering event queue @ 2454299959000. Starting simulation... +info: Entering event queue @ 2454496936000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2455299959000. Starting simulation... -info: Entering event queue @ 2456033037000. Starting simulation... +info: Entering event queue @ 2455496936000. Starting simulation... +info: Entering event queue @ 2456231330000. Starting simulation... switching cpus -info: Entering event queue @ 2456033039000. Starting simulation... +info: Entering event queue @ 2456231332000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2457033039000. Starting simulation... +info: Entering event queue @ 2457231332000. Starting simulation... switching cpus -info: Entering event queue @ 2457033167000. Starting simulation... +info: Entering event queue @ 2457231468000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2458033167000. Starting simulation... +info: Entering event queue @ 2458231468000. Starting simulation... switching cpus -info: Entering event queue @ 2458033184000. Starting simulation... +info: Entering event queue @ 2458231599000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2459033184000. Starting simulation... +info: Entering event queue @ 2459231599000. Starting simulation... switching cpus -info: Entering event queue @ 2459033282000. Starting simulation... +info: Entering event queue @ 2459231662000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2460033282000. Starting simulation... +info: Entering event queue @ 2460231662000. Starting simulation... switching cpus -info: Entering event queue @ 2460033316000. Starting simulation... +info: Entering event queue @ 2460231735000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2461033316000. Starting simulation... +info: Entering event queue @ 2461231735000. Starting simulation... switching cpus -info: Entering event queue @ 2461033409000. Starting simulation... +info: Entering event queue @ 2461231751000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2462033409000. Starting simulation... +info: Entering event queue @ 2462231751000. Starting simulation... switching cpus -info: Entering event queue @ 2462033511000. Starting simulation... +info: Entering event queue @ 2462231781000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2463033511000. Starting simulation... +info: Entering event queue @ 2463231781000. Starting simulation... switching cpus -info: Entering event queue @ 2463033638000. Starting simulation... +info: Entering event queue @ 2463231788500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2464033638000. Starting simulation... +info: Entering event queue @ 2464231788500. Starting simulation... switching cpus -info: Entering event queue @ 2464033758000. Starting simulation... +info: Entering event queue @ 2464231848000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2465033758000. Starting simulation... +info: Entering event queue @ 2465231848000. Starting simulation... switching cpus -info: Entering event queue @ 2465033759000. Starting simulation... +info: Entering event queue @ 2465231865000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2466033759000. Starting simulation... +info: Entering event queue @ 2466231865000. Starting simulation... switching cpus -info: Entering event queue @ 2466033904000. Starting simulation... +info: Entering event queue @ 2466231917000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2467033904000. Starting simulation... +info: Entering event queue @ 2467231917000. Starting simulation... switching cpus -info: Entering event queue @ 2467033927000. Starting simulation... +info: Entering event queue @ 2467232004000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2468033927000. Starting simulation... +info: Entering event queue @ 2468232004000. Starting simulation... switching cpus -info: Entering event queue @ 2468034035000. Starting simulation... +info: Entering event queue @ 2468232072000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2469034035000. Starting simulation... +info: Entering event queue @ 2469232072000. Starting simulation... switching cpus -info: Entering event queue @ 2469034153000. Starting simulation... +info: Entering event queue @ 2469232192000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2470034153000. Starting simulation... +info: Entering event queue @ 2470232192000. Starting simulation... switching cpus -info: Entering event queue @ 2470034198000. Starting simulation... +info: Entering event queue @ 2470232287000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2471034198000. Starting simulation... +info: Entering event queue @ 2471232287000. Starting simulation... switching cpus -info: Entering event queue @ 2471034246000. Starting simulation... +info: Entering event queue @ 2471232409000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2472034246000. Starting simulation... +info: Entering event queue @ 2472232409000. Starting simulation... switching cpus -info: Entering event queue @ 2472034313000. Starting simulation... +info: Entering event queue @ 2472232561000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2473034313000. Starting simulation... +info: Entering event queue @ 2473232561000. Starting simulation... switching cpus -info: Entering event queue @ 2473034456000. Starting simulation... +info: Entering event queue @ 2473232685000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2474034456000. Starting simulation... +info: Entering event queue @ 2474232685000. Starting simulation... switching cpus -info: Entering event queue @ 2474034604000. Starting simulation... +info: Entering event queue @ 2474232739000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2475034604000. Starting simulation... +info: Entering event queue @ 2475232739000. Starting simulation... switching cpus -info: Entering event queue @ 2475034749000. Starting simulation... +info: Entering event queue @ 2475232746500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2476034749000. Starting simulation... +info: Entering event queue @ 2476232746500. Starting simulation... switching cpus -info: Entering event queue @ 2476034794000. Starting simulation... +info: Entering event queue @ 2476232869000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2477034794000. Starting simulation... +info: Entering event queue @ 2477232869000. Starting simulation... switching cpus -info: Entering event queue @ 2477034802000. Starting simulation... +info: Entering event queue @ 2477232953000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2478034802000. Starting simulation... +info: Entering event queue @ 2478232953000. Starting simulation... switching cpus -info: Entering event queue @ 2478034803000. Starting simulation... +info: Entering event queue @ 2478232960500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2479034803000. Starting simulation... +info: Entering event queue @ 2479232960500. Starting simulation... switching cpus -info: Entering event queue @ 2479034908000. Starting simulation... +info: Entering event queue @ 2479232968000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2480034908000. Starting simulation... +info: Entering event queue @ 2480232968000. Starting simulation... switching cpus -info: Entering event queue @ 2480034957000. Starting simulation... +info: Entering event queue @ 2480233089000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2481034957000. Starting simulation... +info: Entering event queue @ 2481233089000. Starting simulation... switching cpus -info: Entering event queue @ 2481034958000. Starting simulation... +info: Entering event queue @ 2481233134000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2482034958000. Starting simulation... +info: Entering event queue @ 2482233134000. Starting simulation... switching cpus -info: Entering event queue @ 2482035090000. Starting simulation... +info: Entering event queue @ 2482233141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2483035090000. Starting simulation... +info: Entering event queue @ 2483233141500. Starting simulation... switching cpus -info: Entering event queue @ 2483035091000. Starting simulation... +info: Entering event queue @ 2483233286000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2484035091000. Starting simulation... +info: Entering event queue @ 2484233286000. Starting simulation... switching cpus -info: Entering event queue @ 2484035144000. Starting simulation... +info: Entering event queue @ 2484233426000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2485035144000. Starting simulation... +info: Entering event queue @ 2485233426000. Starting simulation... switching cpus -info: Entering event queue @ 2485035271000. Starting simulation... +info: Entering event queue @ 2485233556000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2486035271000. Starting simulation... -info: Entering event queue @ 2486035296500. Starting simulation... +info: Entering event queue @ 2486233556000. Starting simulation... switching cpus -info: Entering event queue @ 2486035328001. Starting simulation... +info: Entering event queue @ 2486233563500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2487035328001. Starting simulation... +info: Entering event queue @ 2487233563500. Starting simulation... switching cpus -info: Entering event queue @ 2487035397000. Starting simulation... +info: Entering event queue @ 2487233646000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2488035397000. Starting simulation... -info: Entering event queue @ 2488769554000. Starting simulation... +info: Entering event queue @ 2488233646000. Starting simulation... +info: Entering event queue @ 2488966935000. Starting simulation... switching cpus -info: Entering event queue @ 2488769556000. Starting simulation... +info: Entering event queue @ 2488966937000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2489769556000. Starting simulation... +info: Entering event queue @ 2489966937000. Starting simulation... switching cpus -info: Entering event queue @ 2489769557000. Starting simulation... +info: Entering event queue @ 2489966944500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2490769557000. Starting simulation... +info: Entering event queue @ 2490966944500. Starting simulation... switching cpus -info: Entering event queue @ 2490769609000. Starting simulation... +info: Entering event queue @ 2490967075000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2491769609000. Starting simulation... +info: Entering event queue @ 2491967075000. Starting simulation... switching cpus -info: Entering event queue @ 2491769729000. Starting simulation... +info: Entering event queue @ 2491967146000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2492769729000. Starting simulation... +info: Entering event queue @ 2492967146000. Starting simulation... switching cpus -info: Entering event queue @ 2492769746000. Starting simulation... +info: Entering event queue @ 2492967153500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2493769746000. Starting simulation... +info: Entering event queue @ 2493967153500. Starting simulation... switching cpus -info: Entering event queue @ 2493769816000. Starting simulation... +info: Entering event queue @ 2493967161000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2494769816000. Starting simulation... +info: Entering event queue @ 2494967161000. Starting simulation... switching cpus -info: Entering event queue @ 2494769817000. Starting simulation... +info: Entering event queue @ 2494967168500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2495769817000. Starting simulation... +info: Entering event queue @ 2495967168500. Starting simulation... switching cpus -info: Entering event queue @ 2495769874000. Starting simulation... +info: Entering event queue @ 2495967212000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2496769874000. Starting simulation... +info: Entering event queue @ 2496967212000. Starting simulation... switching cpus -info: Entering event queue @ 2496769981000. Starting simulation... +info: Entering event queue @ 2496967335000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2497769981000. Starting simulation... switching cpus -info: Entering event queue @ 2497769982000. Starting simulation... +info: Entering event queue @ 2497967335000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2498769982000. Starting simulation... +info: Entering event queue @ 2498967335000. Starting simulation... switching cpus -info: Entering event queue @ 2498770059000. Starting simulation... +info: Entering event queue @ 2498967427000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2499770059000. Starting simulation... +info: Entering event queue @ 2499967427000. Starting simulation... switching cpus -info: Entering event queue @ 2499770067000. Starting simulation... +info: Entering event queue @ 2499967545000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2500770067000. Starting simulation... +info: Entering event queue @ 2500967545000. Starting simulation... switching cpus -info: Entering event queue @ 2500770068000. Starting simulation... +info: Entering event queue @ 2500967552500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2501770068000. Starting simulation... +info: Entering event queue @ 2501967552500. Starting simulation... switching cpus -info: Entering event queue @ 2501770143000. Starting simulation... +info: Entering event queue @ 2501967556000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2502770143000. Starting simulation... +info: Entering event queue @ 2502967556000. Starting simulation... switching cpus -info: Entering event queue @ 2502770205000. Starting simulation... +info: Entering event queue @ 2502967624000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2503770205000. Starting simulation... +info: Entering event queue @ 2503967624000. Starting simulation... switching cpus -info: Entering event queue @ 2503770206000. Starting simulation... +info: Entering event queue @ 2503967631500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2504770206000. Starting simulation... +info: Entering event queue @ 2504967631500. Starting simulation... switching cpus -info: Entering event queue @ 2504770245000. Starting simulation... +info: Entering event queue @ 2504967739000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2505770245000. Starting simulation... +info: Entering event queue @ 2505967739000. Starting simulation... switching cpus -info: Entering event queue @ 2505770337000. Starting simulation... +info: Entering event queue @ 2505967746500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2506770337000. Starting simulation... +info: Entering event queue @ 2506967746500. Starting simulation... switching cpus -info: Entering event queue @ 2506770376000. Starting simulation... +info: Entering event queue @ 2506967777000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2507770376000. Starting simulation... +info: Entering event queue @ 2507967777000. Starting simulation... switching cpus -info: Entering event queue @ 2507770429000. Starting simulation... +info: Entering event queue @ 2507967850000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2508770429000. Starting simulation... +info: Entering event queue @ 2508967850000. Starting simulation... switching cpus -info: Entering event queue @ 2508770532000. Starting simulation... +info: Entering event queue @ 2508967857500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2509770532000. Starting simulation... +info: Entering event queue @ 2509967857500. Starting simulation... switching cpus -info: Entering event queue @ 2509770565000. Starting simulation... +info: Entering event queue @ 2509967904000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2510770565000. Starting simulation... +info: Entering event queue @ 2510967904000. Starting simulation... switching cpus -info: Entering event queue @ 2510770668000. Starting simulation... +info: Entering event queue @ 2510968030000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2511770668000. Starting simulation... +info: Entering event queue @ 2511968030000. Starting simulation... switching cpus -info: Entering event queue @ 2511770737000. Starting simulation... +info: Entering event queue @ 2511968037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2512770737000. Starting simulation... +info: Entering event queue @ 2512968037500. Starting simulation... switching cpus -info: Entering event queue @ 2512770886000. Starting simulation... +info: Entering event queue @ 2512968149000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2513770886000. Starting simulation... +info: Entering event queue @ 2513968149000. Starting simulation... switching cpus -info: Entering event queue @ 2513770887000. Starting simulation... +info: Entering event queue @ 2513968255000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2514770887000. Starting simulation... +info: Entering event queue @ 2514968255000. Starting simulation... switching cpus -info: Entering event queue @ 2514771013000. Starting simulation... +info: Entering event queue @ 2514968262500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2515771013000. Starting simulation... +info: Entering event queue @ 2515968262500. Starting simulation... switching cpus -info: Entering event queue @ 2515771025000. Starting simulation... +info: Entering event queue @ 2515968353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2516771025000. Starting simulation... +info: Entering event queue @ 2516968353000. Starting simulation... switching cpus -info: Entering event queue @ 2516771132000. Starting simulation... +info: Entering event queue @ 2516968367000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2517771132000. Starting simulation... +info: Entering event queue @ 2517968367000. Starting simulation... switching cpus -info: Entering event queue @ 2517771133000. Starting simulation... +info: Entering event queue @ 2517968374500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2518771133000. Starting simulation... +info: Entering event queue @ 2518968374500. Starting simulation... switching cpus -info: Entering event queue @ 2518771270000. Starting simulation... +info: Entering event queue @ 2518968382000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2519771270000. Starting simulation... +info: Entering event queue @ 2519968382000. Starting simulation... switching cpus -info: Entering event queue @ 2519771364000. Starting simulation... +info: Entering event queue @ 2519968393000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2520771364000. Starting simulation... -info: Entering event queue @ 2521505845000. Starting simulation... +info: Entering event queue @ 2520968393000. Starting simulation... +info: Entering event queue @ 2521703535000. Starting simulation... switching cpus -info: Entering event queue @ 2521505847000. Starting simulation... +info: Entering event queue @ 2521703537000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2522505847000. Starting simulation... +info: Entering event queue @ 2522703537000. Starting simulation... switching cpus -info: Entering event queue @ 2522505848000. Starting simulation... +info: Entering event queue @ 2522703612000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2523505848000. Starting simulation... +info: Entering event queue @ 2523703612000. Starting simulation... switching cpus -info: Entering event queue @ 2523505849000. Starting simulation... +info: Entering event queue @ 2523703619500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2524505849000. Starting simulation... +info: Entering event queue @ 2524703619500. Starting simulation... switching cpus -info: Entering event queue @ 2524505850000. Starting simulation... +info: Entering event queue @ 2524703726000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2525505850000. Starting simulation... +info: Entering event queue @ 2525703726000. Starting simulation... switching cpus -info: Entering event queue @ 2525505953000. Starting simulation... +info: Entering event queue @ 2525703841000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2526505953000. Starting simulation... +info: Entering event queue @ 2526703841000. Starting simulation... +info: Entering event queue @ 2526703980500. Starting simulation... switching cpus -info: Entering event queue @ 2526505954000. Starting simulation... +info: Entering event queue @ 2526703988000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2527505954000. Starting simulation... -info: Entering event queue @ 2527505964000. Starting simulation... +info: Entering event queue @ 2527703988000. Starting simulation... switching cpus -info: Entering event queue @ 2527505965500. Starting simulation... +info: Entering event queue @ 2527704057000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2528505965500. Starting simulation... +info: Entering event queue @ 2528704057000. Starting simulation... +info: Entering event queue @ 2528704070000. Starting simulation... switching cpus -info: Entering event queue @ 2528506085000. Starting simulation... +info: Entering event queue @ 2528704072500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2529506085000. Starting simulation... +info: Entering event queue @ 2529704072500. Starting simulation... switching cpus -info: Entering event queue @ 2529506182000. Starting simulation... +info: Entering event queue @ 2529704080000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2530506182000. Starting simulation... +info: Entering event queue @ 2530704080000. Starting simulation... switching cpus -info: Entering event queue @ 2530506241000. Starting simulation... +info: Entering event queue @ 2530704175000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2531506241000. Starting simulation... +info: Entering event queue @ 2531704175000. Starting simulation... switching cpus -info: Entering event queue @ 2531506368000. Starting simulation... +info: Entering event queue @ 2531704259000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2532506368000. Starting simulation... +info: Entering event queue @ 2532704259000. Starting simulation... switching cpus -info: Entering event queue @ 2532506400000. Starting simulation... +info: Entering event queue @ 2532704266500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2533506400000. Starting simulation... +info: Entering event queue @ 2533704266500. Starting simulation... switching cpus -info: Entering event queue @ 2533506404000. Starting simulation... +info: Entering event queue @ 2533704275000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2534506404000. Starting simulation... +info: Entering event queue @ 2534704275000. Starting simulation... switching cpus -info: Entering event queue @ 2534506527000. Starting simulation... +info: Entering event queue @ 2534704354000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2535506527000. Starting simulation... +info: Entering event queue @ 2535704354000. Starting simulation... switching cpus -info: Entering event queue @ 2535506668000. Starting simulation... +info: Entering event queue @ 2535704361500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2536506668000. Starting simulation... +info: Entering event queue @ 2536704361500. Starting simulation... switching cpus -info: Entering event queue @ 2536506816000. Starting simulation... +info: Entering event queue @ 2536704449000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2537506816000. Starting simulation... +info: Entering event queue @ 2537704449000. Starting simulation... switching cpus -info: Entering event queue @ 2537506817000. Starting simulation... +info: Entering event queue @ 2537704557000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2538506817000. Starting simulation... +info: Entering event queue @ 2538704557000. Starting simulation... switching cpus -info: Entering event queue @ 2538506962000. Starting simulation... +info: Entering event queue @ 2538704705000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2539506962000. Starting simulation... +info: Entering event queue @ 2539704705000. Starting simulation... switching cpus -info: Entering event queue @ 2539507054000. Starting simulation... +info: Entering event queue @ 2539704773000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2540507054000. Starting simulation... +info: Entering event queue @ 2540704773000. Starting simulation... switching cpus -info: Entering event queue @ 2540507055000. Starting simulation... +info: Entering event queue @ 2540704780500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2541507055000. Starting simulation... +info: Entering event queue @ 2541704780500. Starting simulation... switching cpus -info: Entering event queue @ 2541507057000. Starting simulation... +info: Entering event queue @ 2541704788000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2542507057000. Starting simulation... +info: Entering event queue @ 2542704788000. Starting simulation... switching cpus -info: Entering event queue @ 2542507129000. Starting simulation... +info: Entering event queue @ 2542704795500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2543507129000. Starting simulation... +info: Entering event queue @ 2543704795500. Starting simulation... switching cpus -info: Entering event queue @ 2543507190000. Starting simulation... +info: Entering event queue @ 2543704917000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2544507190000. Starting simulation... +info: Entering event queue @ 2544704917000. Starting simulation... switching cpus -info: Entering event queue @ 2544507208000. Starting simulation... +info: Entering event queue @ 2544705016000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2545507208000. Starting simulation... +info: Entering event queue @ 2545705016000. Starting simulation... switching cpus -info: Entering event queue @ 2545507209000. Starting simulation... +info: Entering event queue @ 2545705132000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2546507209000. Starting simulation... +info: Entering event queue @ 2546705132000. Starting simulation... switching cpus -info: Entering event queue @ 2546507292000. Starting simulation... +info: Entering event queue @ 2546705217000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2547507292000. Starting simulation... +info: Entering event queue @ 2547705217000. Starting simulation... switching cpus -info: Entering event queue @ 2547507296000. Starting simulation... +info: Entering event queue @ 2547705224500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2548507296000. Starting simulation... +info: Entering event queue @ 2548705224500. Starting simulation... switching cpus -info: Entering event queue @ 2548507297000. Starting simulation... +info: Entering event queue @ 2548705235000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2549507297000. Starting simulation... +info: Entering event queue @ 2549705235000. Starting simulation... switching cpus -info: Entering event queue @ 2549507392000. Starting simulation... +info: Entering event queue @ 2549705357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2550507392000. Starting simulation... +info: Entering event queue @ 2550705357000. Starting simulation... switching cpus -info: Entering event queue @ 2550507429000. Starting simulation... +info: Entering event queue @ 2550705364500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2551507429000. Starting simulation... +info: Entering event queue @ 2551705364500. Starting simulation... switching cpus -info: Entering event queue @ 2551507430000. Starting simulation... +info: Entering event queue @ 2551705395000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2552507430000. Starting simulation... +info: Entering event queue @ 2552705395000. Starting simulation... switching cpus -info: Entering event queue @ 2552507449000. Starting simulation... +info: Entering event queue @ 2552705402500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2553507449000. Starting simulation... -info: Entering event queue @ 2554241989000. Starting simulation... +info: Entering event queue @ 2553705402500. Starting simulation... +info: Entering event queue @ 2554438939000. Starting simulation... switching cpus -info: Entering event queue @ 2554241991000. Starting simulation... +info: Entering event queue @ 2554438946500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2555241991000. Starting simulation... +info: Entering event queue @ 2555438946500. Starting simulation... switching cpus -info: Entering event queue @ 2555241999500. Starting simulation... +info: Entering event queue @ 2555438954000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2556241999500. Starting simulation... +info: Entering event queue @ 2556438954000. Starting simulation... switching cpus -info: Entering event queue @ 2556242000500. Starting simulation... +info: Entering event queue @ 2556438961500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2557242000500. Starting simulation... +info: Entering event queue @ 2557438961500. Starting simulation... switching cpus -info: Entering event queue @ 2557242001500. Starting simulation... +info: Entering event queue @ 2557438969000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2558242001500. Starting simulation... +info: Entering event queue @ 2558438969000. Starting simulation... switching cpus -info: Entering event queue @ 2558242077000. Starting simulation... +info: Entering event queue @ 2558438976500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2559242077000. Starting simulation... +info: Entering event queue @ 2559438976500. Starting simulation... switching cpus -info: Entering event queue @ 2559242141000. Starting simulation... +info: Entering event queue @ 2559439045000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2560242141000. Starting simulation... +info: Entering event queue @ 2560439045000. Starting simulation... switching cpus -info: Entering event queue @ 2560242242000. Starting simulation... +info: Entering event queue @ 2560439111000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2561242242000. Starting simulation... +info: Entering event queue @ 2561439111000. Starting simulation... switching cpus -info: Entering event queue @ 2561242255000. Starting simulation... +info: Entering event queue @ 2561439229000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2562242255000. Starting simulation... +info: Entering event queue @ 2562439229000. Starting simulation... switching cpus -info: Entering event queue @ 2562242375000. Starting simulation... +info: Entering event queue @ 2562439304000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2563242375000. Starting simulation... +info: Entering event queue @ 2563439304000. Starting simulation... switching cpus -info: Entering event queue @ 2563242389000. Starting simulation... +info: Entering event queue @ 2563439451000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2564242389000. Starting simulation... +info: Entering event queue @ 2564439451000. Starting simulation... switching cpus -info: Entering event queue @ 2564242391000. Starting simulation... +info: Entering event queue @ 2564439484000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2565242391000. Starting simulation... +info: Entering event queue @ 2565439484000. Starting simulation... switching cpus -info: Entering event queue @ 2565242463000. Starting simulation... +info: Entering event queue @ 2565439632000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2566242463000. Starting simulation... +info: Entering event queue @ 2566439632000. Starting simulation... switching cpus -info: Entering event queue @ 2566242542000. Starting simulation... +info: Entering event queue @ 2566439771000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2567242542000. Starting simulation... +info: Entering event queue @ 2567439771000. Starting simulation... switching cpus -info: Entering event queue @ 2567242688000. Starting simulation... +info: Entering event queue @ 2567439778500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2568242688000. Starting simulation... +info: Entering event queue @ 2568439778500. Starting simulation... switching cpus -info: Entering event queue @ 2568242730000. Starting simulation... +info: Entering event queue @ 2568439829000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2569242730000. Starting simulation... +info: Entering event queue @ 2569439829000. Starting simulation... switching cpus -info: Entering event queue @ 2569242838000. Starting simulation... +info: Entering event queue @ 2569439894000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2570242838000. Starting simulation... +info: Entering event queue @ 2570439894000. Starting simulation... switching cpus -info: Entering event queue @ 2570242940000. Starting simulation... +info: Entering event queue @ 2570439901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2571242940000. Starting simulation... +info: Entering event queue @ 2571439901500. Starting simulation... switching cpus -info: Entering event queue @ 2571242946000. Starting simulation... +info: Entering event queue @ 2571440025000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2572242946000. Starting simulation... +info: Entering event queue @ 2572440025000. Starting simulation... switching cpus -info: Entering event queue @ 2572243030000. Starting simulation... +info: Entering event queue @ 2572440157000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2573243030000. Starting simulation... +info: Entering event queue @ 2573440157000. Starting simulation... switching cpus -info: Entering event queue @ 2573243031000. Starting simulation... +info: Entering event queue @ 2573440165000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2574243031000. Starting simulation... +info: Entering event queue @ 2574440165000. Starting simulation... switching cpus -info: Entering event queue @ 2574243077000. Starting simulation... +info: Entering event queue @ 2574440172500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2575243077000. Starting simulation... +info: Entering event queue @ 2575440172500. Starting simulation... switching cpus -info: Entering event queue @ 2575243233000. Starting simulation... +info: Entering event queue @ 2575440283000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2576243233000. Starting simulation... +info: Entering event queue @ 2576440283000. Starting simulation... switching cpus -info: Entering event queue @ 2576243261000. Starting simulation... +info: Entering event queue @ 2576440290500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2577243261000. Starting simulation... +info: Entering event queue @ 2577440290500. Starting simulation... switching cpus -info: Entering event queue @ 2577243262000. Starting simulation... +info: Entering event queue @ 2577440355000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2578243262000. Starting simulation... +info: Entering event queue @ 2578440355000. Starting simulation... switching cpus -info: Entering event queue @ 2578243340000. Starting simulation... +info: Entering event queue @ 2578440362500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2579243340000. Starting simulation... +info: Entering event queue @ 2579440362500. Starting simulation... switching cpus -info: Entering event queue @ 2579243341000. Starting simulation... +info: Entering event queue @ 2579440365000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2580243341000. Starting simulation... +info: Entering event queue @ 2580440365000. Starting simulation... switching cpus -info: Entering event queue @ 2580243342000. Starting simulation... +info: Entering event queue @ 2580440372500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2581243342000. Starting simulation... +info: Entering event queue @ 2581440372500. Starting simulation... switching cpus -info: Entering event queue @ 2581243343000. Starting simulation... +info: Entering event queue @ 2581440380000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2582243343000. Starting simulation... +info: Entering event queue @ 2582440380000. Starting simulation... +info: Entering event queue @ 2582440388500. Starting simulation... switching cpus -info: Entering event queue @ 2582243344000. Starting simulation... +info: Entering event queue @ 2582440391000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2583243344000. Starting simulation... -info: Entering event queue @ 2583243355000. Starting simulation... +info: Entering event queue @ 2583440391000. Starting simulation... +info: Entering event queue @ 2583440399500. Starting simulation... switching cpus -info: Entering event queue @ 2583243358500. Starting simulation... +info: Entering event queue @ 2583440403000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2584243358500. Starting simulation... +info: Entering event queue @ 2584440403000. Starting simulation... switching cpus -info: Entering event queue @ 2584243360500. Starting simulation... +info: Entering event queue @ 2584440412000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2585243360500. Starting simulation... +info: Entering event queue @ 2585440412000. Starting simulation... switching cpus -info: Entering event queue @ 2585243362500. Starting simulation... +info: Entering event queue @ 2585440419500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2586243362500. Starting simulation... -info: Entering event queue @ 2586996937000. Starting simulation... +info: Entering event queue @ 2586440419500. Starting simulation... +info: Entering event queue @ 2587181122000. Starting simulation... switching cpus -info: Entering event queue @ 2586996939000. Starting simulation... +info: Entering event queue @ 2587181124000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2587996939000. Starting simulation... +info: Entering event queue @ 2588181124000. Starting simulation... switching cpus -info: Entering event queue @ 2587996940000. Starting simulation... +info: Entering event queue @ 2588181131500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2588996940000. Starting simulation... +info: Entering event queue @ 2589181131500. Starting simulation... switching cpus -info: Entering event queue @ 2588996941000. Starting simulation... +info: Entering event queue @ 2589181133000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2589996941000. Starting simulation... +info: Entering event queue @ 2590181133000. Starting simulation... switching cpus -info: Entering event queue @ 2589996942000. Starting simulation... +info: Entering event queue @ 2590181140500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2590996942000. Starting simulation... +info: Entering event queue @ 2591181140500. Starting simulation... switching cpus -info: Entering event queue @ 2590996944000. Starting simulation... +info: Entering event queue @ 2591181172000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2591996944000. Starting simulation... +info: Entering event queue @ 2592181172000. Starting simulation... switching cpus -info: Entering event queue @ 2591996945000. Starting simulation... +info: Entering event queue @ 2592181179500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2592996945000. Starting simulation... +info: Entering event queue @ 2593181179500. Starting simulation... switching cpus -info: Entering event queue @ 2592996946000. Starting simulation... +info: Entering event queue @ 2593181187000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2593996946000. Starting simulation... +info: Entering event queue @ 2594181187000. Starting simulation... switching cpus -info: Entering event queue @ 2593996952500. Starting simulation... +info: Entering event queue @ 2594181194500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2594996952500. Starting simulation... +info: Entering event queue @ 2595181194500. Starting simulation... switching cpus -info: Entering event queue @ 2594996953500. Starting simulation... +info: Entering event queue @ 2595181202000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2595996953500. Starting simulation... +info: Entering event queue @ 2596181202000. Starting simulation... switching cpus -info: Entering event queue @ 2595996958500. Starting simulation... +info: Entering event queue @ 2596181209500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2596996958500. Starting simulation... +info: Entering event queue @ 2597181209500. Starting simulation... switching cpus -info: Entering event queue @ 2596996959500. Starting simulation... +info: Entering event queue @ 2597181217000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2597996959500. Starting simulation... +info: Entering event queue @ 2598181217000. Starting simulation... switching cpus -info: Entering event queue @ 2597996960500. Starting simulation... +info: Entering event queue @ 2598181222000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2598996960500. Starting simulation... +info: Entering event queue @ 2599181222000. Starting simulation... switching cpus -info: Entering event queue @ 2598996961500. Starting simulation... +info: Entering event queue @ 2599181229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2599996961500. Starting simulation... +info: Entering event queue @ 2600181229500. Starting simulation... switching cpus -info: Entering event queue @ 2599996963500. Starting simulation... +info: Entering event queue @ 2600181237000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2600996963500. Starting simulation... +info: Entering event queue @ 2601181237000. Starting simulation... +info: Entering event queue @ 2601181244500. Starting simulation... switching cpus -info: Entering event queue @ 2600996975000. Starting simulation... +info: Entering event queue @ 2601181247500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2601996975000. Starting simulation... +info: Entering event queue @ 2602181247500. Starting simulation... switching cpus -info: Entering event queue @ 2601996976000. Starting simulation... +info: Entering event queue @ 2602181255000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2602996976000. Starting simulation... +info: Entering event queue @ 2603181255000. Starting simulation... +info: Entering event queue @ 2603181266500. Starting simulation... switching cpus -info: Entering event queue @ 2602997129000. Starting simulation... +info: Entering event queue @ 2603181269000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2603997129000. Starting simulation... +info: Entering event queue @ 2604181269000. Starting simulation... switching cpus -info: Entering event queue @ 2603997243000. Starting simulation... +info: Entering event queue @ 2604181375000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2604997243000. Starting simulation... +info: Entering event queue @ 2605181375000. Starting simulation... switching cpus -info: Entering event queue @ 2604997244500. Starting simulation... +info: Entering event queue @ 2605181382500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2605997244500. Starting simulation... +info: Entering event queue @ 2606181382500. Starting simulation... switching cpus -info: Entering event queue @ 2605997245500. Starting simulation... +info: Entering event queue @ 2606181390000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2606997245500. Starting simulation... +info: Entering event queue @ 2607181390000. Starting simulation... switching cpus -info: Entering event queue @ 2606997246500. Starting simulation... +info: Entering event queue @ 2607181397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2607997246500. Starting simulation... -info: Entering event queue @ 2607997257000. Starting simulation... +info: Entering event queue @ 2608181397500. Starting simulation... switching cpus -info: Entering event queue @ 2607997260500. Starting simulation... +info: Entering event queue @ 2608181405000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 2608997260500. Starting simulation... +info: Entering event queue @ 2609181405000. Starting simulation... switching cpus -info: Entering event queue @ 2608997261500. Starting simulation... +info: Entering event queue @ 2609181412500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e925b6c9c..26ec1de8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.608779 # Number of seconds simulated -sim_ticks 2608778789000 # Number of ticks simulated -final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.610012 # Number of seconds simulated +sim_ticks 2610011893000 # Number of ticks simulated +final_tick 2610011893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 616577 # Simulator instruction rate (inst/s) -host_op_rate 784589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26716567066 # Simulator tick rate (ticks/s) -host_mem_usage 403640 # Number of bytes of host memory used -host_seconds 97.65 # Real time elapsed on the host -sim_insts 60206536 # Number of instructions simulated -sim_ops 76612339 # Number of ops (including micro ops) simulated +host_inst_rate 167893 # Simulator instruction rate (inst/s) +host_op_rate 213643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7278548305 # Simulator tick rate (ticks/s) +host_mem_usage 438276 # Number of bytes of host memory used +host_seconds 358.59 # Real time elapsed on the host +sim_insts 60204721 # Number of instructions simulated +sim_ops 76610045 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4486348 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4557348 # Number of bytes read from this memory -system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1520260 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1495880 # Number of bytes written to this memory -system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 356960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4558796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 347904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4486256 # Number of bytes read from this memory +system.physmem.bytes_read::total 132433500 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 356960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 347904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1510336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1505932 # Number of bytes written to this memory +system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70132 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71232 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380065 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373970 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 11780 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 71264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70124 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494031 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 377584 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 376483 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47004917 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1719712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1746928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 582748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 573402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 136766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1746657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 133296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1718864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50740573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 136766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 133296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1407135 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 578670 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 576983 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2562788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1407135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47004917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2302460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2320330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494012 # Total number of read requests seen -system.physmem.writeReqs 811397 # Total number of write requests seen -system.physmem.cpureqs 213789 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991616768 # Total number of bytes read from memory -system.physmem.bytesWritten 51929408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132432464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6687308 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967895 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968388 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 136766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2325327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 133296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2295847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53303362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494031 # Total number of read requests seen +system.physmem.writeReqs 811452 # Total number of write requests seen +system.physmem.cpureqs 213827 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991617984 # Total number of bytes read from memory +system.physmem.bytesWritten 51932928 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132433500 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 27 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4514 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 974843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968385 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967706 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968022 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967512 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967509 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 50752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50998 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50782 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50199 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51047 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50585 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2608774377500 # Total gap between requests +system.physmem.totGap 2610007485000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6676 # Categorize read packet sizes +system.physmem.readPktSize::2 6679 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 151912 # Categorize read packet sizes +system.physmem.readPktSize::6 151928 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754035 # Categorize write packet sizes +system.physmem.writePktSize::2 754067 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57362 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1116374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 959978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3651919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2754799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2759743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2734008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 61745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 162677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57385 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3652365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2754414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2734327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 61705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 162629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,59 +152,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.totQLat 338360116500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 433225996500 # Sum of mem lat for all requests -system.physmem.totBusLat 77469930000 # Total cycles spent in databus access -system.physmem.totBankLat 17395950000 # Total cycles spent in bank access -system.physmem.avgQLat 21838.16 # Average queueing delay per request -system.physmem.avgBankLat 1122.75 # Average bank access latency per request +system.physmem.wrQLenPdf::16 35213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.totQLat 338127152500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 432998718750 # Sum of mem lat for all requests +system.physmem.totBusLat 77470020000 # Total cycles spent in databus access +system.physmem.totBankLat 17401546250 # Total cycles spent in bank access +system.physmem.avgQLat 21823.10 # Average queueing delay per request +system.physmem.avgBankLat 1123.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27960.91 # Average memory access latency -system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27946.21 # Average memory access latency +system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.24 # Average write queue length over time -system.physmem.readRowHits 15419485 # Number of row buffer hits during reads -system.physmem.writeRowHits 793971 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.25 # Average write queue length over time +system.physmem.readRowHits 15419474 # Number of row buffer hits during reads +system.physmem.writeRowHits 794097 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159994.42 # Average gap between requests +system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes +system.physmem.avgGap 160069.31 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -217,205 +217,205 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 61800 # number of replacements -system.l2c.tagsinuse 50918.274770 # Cycle average of tags in use -system.l2c.total_refs 1698590 # Total number of references to valid blocks. -system.l2c.sampled_refs 127185 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.355270 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37907.739724 # Average occupied blocks per requestor +system.l2c.replacements 61815 # number of replacements +system.l2c.tagsinuse 50922.556622 # Cycle average of tags in use +system.l2c.total_refs 1697645 # Total number of references to valid blocks. +system.l2c.sampled_refs 127200 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.346266 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2558113997500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37911.407506 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4327.115083 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3097.452751 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2668.881349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2917.085036 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3494.638708 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3026.772490 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2989.111997 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.047263 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044511 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 10140 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 409506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188271 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 434846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 182307 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241751 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits -system.l2c.Writeback_hits::total 596435 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.053324 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.046185 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.053415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.045610 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.777017 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 10043 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 407564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 186717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9399 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3346 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 436383 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183761 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1240867 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596298 # number of Writeback hits +system.l2c.Writeback_hits::total 596298 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57591 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114569 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10140 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 409506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245862 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3405 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 434846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239285 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356320 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10140 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3715 # number of overall hits -system.l2c.overall_hits::cpu0.inst 409506 # number of overall hits -system.l2c.overall_hits::cpu0.data 245862 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9561 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3405 # number of overall hits -system.l2c.overall_hits::cpu1.inst 434846 # number of overall hits -system.l2c.overall_hits::cpu1.data 239285 # number of overall hits -system.l2c.overall_hits::total 1356320 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 55801 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114544 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10043 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 407564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 242518 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9399 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3346 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 436383 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 242504 # number of demand (read+write) hits +system.l2c.demand_hits::total 1355411 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10043 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3654 # number of overall hits +system.l2c.overall_hits::cpu0.inst 407564 # number of overall hits +system.l2c.overall_hits::cpu0.data 242518 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9399 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3346 # number of overall hits +system.l2c.overall_hits::cpu1.inst 436383 # number of overall hits +system.l2c.overall_hits::cpu1.data 242504 # number of overall hits +system.l2c.overall_hits::total 1355411 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5513 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4337 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20458 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1394 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2871 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67697 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133098 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 5164 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5288 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5436 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4561 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20452 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1403 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2882 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 66764 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 66344 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133108 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6138 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 70914 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 72034 # number of demand (read+write) misses -system.l2c.demand_misses::total 153556 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5164 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 72052 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5436 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 70905 # number of demand (read+write) misses +system.l2c.demand_misses::total 153560 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6138 # number of overall misses -system.l2c.overall_misses::cpu0.data 70914 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4467 # number of overall misses -system.l2c.overall_misses::cpu1.data 72034 # number of overall misses -system.l2c.overall_misses::total 153556 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5164 # number of overall misses +system.l2c.overall_misses::cpu0.data 72052 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5436 # number of overall misses +system.l2c.overall_misses::cpu1.data 70905 # number of overall misses +system.l2c.overall_misses::total 153560 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 318133500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 286446000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 246251500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 242168000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1093150500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 227000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 228000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 455000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 2952570500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3124407000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6076977500 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 276276000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 281472500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 285306500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 251488000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1094694500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 249000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 205000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 454000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3062671000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3034678000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6097349000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 318133500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3239016500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 246251500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3366575000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7170128000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 276276000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3344143500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 285306500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3286166000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7192043500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 318133500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3239016500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 246251500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3366575000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7170128000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3717 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 415644 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 193784 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9561 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3405 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 439313 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 186644 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262209 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596435 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596435 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1405 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1492 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2897 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 122992 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 124675 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247667 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3717 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 415644 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 316776 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9561 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3405 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 439313 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 311319 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1509876 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3717 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 415644 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 316776 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9561 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3405 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 439313 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 311319 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1509876 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000538 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014767 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028449 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023237 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016208 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992171 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989946 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.531750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.542988 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537407 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000538 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014767 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.223862 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.231383 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101701 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000538 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014767 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.223862 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.231383 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101701 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu0.inst 276276000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3344143500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 285306500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3286166000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7192043500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 10044 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3656 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 412728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 192005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 441819 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 188322 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1261319 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596298 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596298 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1415 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1493 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2908 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 122565 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125087 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247652 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3656 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 412728 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9399 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3346 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 441819 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 313409 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1508971 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3656 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 412728 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9399 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3346 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 441819 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 313409 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1508971 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000100 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000547 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012512 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027541 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024219 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016215 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991519 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990623 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991059 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.544723 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.530383 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537480 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000100 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000547 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012512 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.229049 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.226238 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101765 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000100 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000547 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012512 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.229049 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.226238 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101765 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51830.156403 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 51958.280428 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55126.818894 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 55837.675813 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53433.888943 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 162.840746 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 154.366960 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 158.481365 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45145.647620 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46152.813271 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 45657.917474 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53500.387297 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 53228.536309 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52484.639441 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 55138.785354 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53525.058674 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 177.476835 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 138.607167 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 157.529493 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45873.090288 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 45741.559146 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 45807.532229 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 51830.156403 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 45675.275686 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55126.818894 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46735.916373 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 46693.896689 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53500.387297 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 46412.917060 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52484.639441 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46346.040477 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 46835.396588 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 51830.156403 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 45675.275686 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55126.818894 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46735.916373 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 46693.896689 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53500.387297 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 46412.917060 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52484.639441 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46346.040477 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 46835.396588 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,131 +424,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57362 # number of writebacks -system.l2c.writebacks::total 57362 # number of writebacks +system.l2c.writebacks::writebacks 57385 # number of writebacks +system.l2c.writebacks::total 57385 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6138 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5513 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4467 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4337 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20458 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1394 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1477 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2871 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 65401 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 67697 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133098 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5164 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5288 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5436 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4561 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20452 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1403 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1479 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2882 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 66764 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 66344 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133108 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6138 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 70914 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4467 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 72034 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153556 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5164 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 72052 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5436 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 70905 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153560 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6138 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 70914 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4467 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 72034 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153556 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5164 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 72052 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5436 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 70905 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153560 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 241189638 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 217772763 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 190279467 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 188012087 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 837367708 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13941394 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14803954 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28745348 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2130102401 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2271808177 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4401910578 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 211511414 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 215576288 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 217120186 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 194516811 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 838838452 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14070376 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14791479 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28861855 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2222426749 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2199580594 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4422007343 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 241189638 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2347875164 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 190279467 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2459820264 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5239278286 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 211511414 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2438003037 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 217120186 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2394097405 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5260845795 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 241189638 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2347875164 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 190279467 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2459820264 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5239278286 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 211511414 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2438003037 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 217120186 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2394097405 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5260845795 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209116116 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83656256785 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83045804272 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166911177173 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4790532841 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4370266467 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9160799308 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83638407285 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83062445525 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166909968926 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4517984886 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4642435980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9160420866 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209116116 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88446789626 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87416070739 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176071976481 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028449 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023237 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016208 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992171 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989946 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531750 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542988 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537407 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101701 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014767 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.223862 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.231383 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88156392171 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87704881505 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176070389792 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027541 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024219 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016215 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991519 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990623 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991059 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.544723 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.530383 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537480 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.229049 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.226238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101765 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000547 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.012512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.229049 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.226238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101765 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39501.680210 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43350.723311 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40931.064034 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.988490 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.312086 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.875094 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33558.476402 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33072.702655 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40767.074130 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42647.842798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41014.983962 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.778332 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10014.522901 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 33287.801045 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.175118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33221.198899 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33836.715664 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34259.219816 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.715664 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34259.219816 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -573,135 +573,135 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7507395 # DTB read hits -system.cpu0.dtb.read_misses 6880 # DTB read misses -system.cpu0.dtb.write_hits 5552217 # DTB write hits -system.cpu0.dtb.write_misses 1843 # DTB write misses -system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7403432 # DTB read hits +system.cpu0.dtb.read_misses 6873 # DTB read misses +system.cpu0.dtb.write_hits 5501198 # DTB write hits +system.cpu0.dtb.write_misses 1842 # DTB write misses +system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6531 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7514275 # DTB read accesses -system.cpu0.dtb.write_accesses 5554060 # DTB write accesses +system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7410305 # DTB read accesses +system.cpu0.dtb.write_accesses 5503040 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13059612 # DTB hits -system.cpu0.dtb.misses 8723 # DTB misses -system.cpu0.dtb.accesses 13068335 # DTB accesses -system.cpu0.itb.inst_hits 30766787 # ITB inst hits -system.cpu0.itb.inst_misses 3610 # ITB inst misses +system.cpu0.dtb.hits 12904630 # DTB hits +system.cpu0.dtb.misses 8715 # DTB misses +system.cpu0.dtb.accesses 12913345 # DTB accesses +system.cpu0.itb.inst_hits 30303054 # ITB inst hits +system.cpu0.itb.inst_misses 3598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2714 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2696 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30770397 # ITB inst accesses -system.cpu0.itb.hits 30766787 # DTB hits -system.cpu0.itb.misses 3610 # DTB misses -system.cpu0.itb.accesses 30770397 # DTB accesses -system.cpu0.numCycles 2552895768 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30306652 # ITB inst accesses +system.cpu0.itb.hits 30303054 # DTB hits +system.cpu0.itb.misses 3598 # DTB misses +system.cpu0.itb.accesses 30306652 # DTB accesses +system.cpu0.numCycles 2668343003 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30144155 # Number of instructions committed -system.cpu0.committedOps 38293148 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34424496 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses -system.cpu0.num_func_calls 1041305 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4017298 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34424496 # number of integer instructions -system.cpu0.num_fp_insts 5276 # number of float instructions -system.cpu0.num_int_register_reads 197342644 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37147872 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written -system.cpu0.num_mem_refs 13659420 # number of memory refs -system.cpu0.num_load_insts 7847088 # Number of load instructions -system.cpu0.num_store_insts 5812332 # Number of store instructions -system.cpu0.num_idle_cycles 3486764467.544441 # Number of idle cycles -system.cpu0.num_busy_cycles -933868699.544441 # Number of busy cycles -system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles -system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles +system.cpu0.committedInsts 29632665 # Number of instructions committed +system.cpu0.committedOps 37682858 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33888275 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5192 # Number of float alu accesses +system.cpu0.num_func_calls 1024744 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3926833 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33888275 # number of integer instructions +system.cpu0.num_fp_insts 5192 # number of float instructions +system.cpu0.num_int_register_reads 194247306 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521980 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3842 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1352 # number of times the floating registers were written +system.cpu0.num_mem_refs 13487420 # number of memory refs +system.cpu0.num_load_insts 7732200 # Number of load instructions +system.cpu0.num_store_insts 5755220 # Number of store instructions +system.cpu0.num_idle_cycles -6063478274.849866 # Number of idle cycles +system.cpu0.num_busy_cycles 8731821277.849865 # Number of busy cycles +system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles +system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83016 # number of quiesce instructions executed -system.cpu0.icache.replacements 856082 # number of replacements -system.cpu0.icache.tagsinuse 510.977353 # Cycle average of tags in use -system.cpu0.icache.total_refs 60644038 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 354.101290 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 156.876063 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.691604 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.306399 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998003 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30350406 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30293632 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60644038 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30350406 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30293632 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60644038 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30350406 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30293632 # number of overall hits -system.cpu0.icache.overall_hits::total 60644038 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 416381 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 440213 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856594 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 416381 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 440213 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856594 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 416381 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 440213 # number of overall misses -system.cpu0.icache.overall_misses::total 856594 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5680035500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933793500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11613829000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5680035500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5933793500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11613829000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5680035500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5933793500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11613829000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766787 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733845 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61500632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30766787 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30733845 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61500632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30766787 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30733845 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61500632 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013533 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014323 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013533 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014323 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013533 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014323 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.437770 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.369078 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13558.148901 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13558.148901 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13558.148901 # average overall miss latency +system.cpu0.kern.inst.quiesce 83014 # number of quiesce instructions executed +system.cpu0.icache.replacements 855673 # number of replacements +system.cpu0.icache.tagsinuse 510.972312 # Cycle average of tags in use +system.cpu0.icache.total_refs 60642600 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 856185 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.828851 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 18907162000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 150.590705 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 360.381607 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.294122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.703870 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29889508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30753092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60642600 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29889508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30753092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60642600 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29889508 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30753092 # number of overall hits +system.cpu0.icache.overall_hits::total 60642600 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 413546 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 442639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856185 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 413546 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 442639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856185 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 413546 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 442639 # number of overall misses +system.cpu0.icache.overall_misses::total 856185 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5610148500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5995583000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11605731500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5610148500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5995583000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11605731500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5610148500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5995583000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11605731500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30303054 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 31195731 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61498785 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30303054 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 31195731 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61498785 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30303054 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 31195731 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61498785 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013647 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014189 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013922 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013647 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014189 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013922 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013647 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014189 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013922 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.960014 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.085273 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.167984 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13555.167984 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13555.167984 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,158 +710,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416381 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440213 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856594 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 416381 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 440213 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856594 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 416381 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 440213 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856594 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847273500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053367500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900641000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847273500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053367500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9900641000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847273500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053367500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9900641000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413546 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856185 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 413546 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 442639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856185 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 413546 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 442639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856185 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4783056500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5110305000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9893361500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4783056500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5110305000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9893361500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4783056500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5110305000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9893361500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11558.148901 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013647 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014189 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013922 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013647 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014189 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013922 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013647 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014189 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013922 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11555.167984 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 627582 # number of replacements -system.cpu0.dcache.tagsinuse 511.912781 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23658997 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 628094 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.667924 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 627466 # number of replacements +system.cpu0.dcache.tagsinuse 511.912822 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23658362 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 627978 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.673871 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 366.658408 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 145.254373 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.716130 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.283700 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 140.437193 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 371.475629 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.274291 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.725538 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6610508 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6586985 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13197493 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4931207 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5043314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974521 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 109194 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 127142 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236336 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 114801 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 132949 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247750 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11541715 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11630299 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23172014 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11541715 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11630299 # number of overall hits -system.cpu0.dcache.overall_hits::total 23172014 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 188176 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 180837 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369013 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 124397 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 126167 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250564 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5608 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5807 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11415 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 312573 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 307004 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619577 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 312573 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 307004 # number of overall misses -system.cpu0.dcache.overall_misses::total 619577 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2684372000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2560293500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5244665500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3933510000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4106405000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8039915000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 77896000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77564000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 155460000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6617882000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6666698500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13284580500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6617882000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6666698500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13284580500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6798684 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6767822 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13566506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5055604 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5169481 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 114802 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132949 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247751 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 114801 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 132949 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247750 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11854288 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11937303 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23791591 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11854288 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11937303 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23791591 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027678 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026720 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024606 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024406 # miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6510444 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6686709 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13197153 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4886816 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5087431 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974247 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 106752 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129570 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236322 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112519 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135213 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247732 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11397260 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11774140 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23171400 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11397260 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11774140 # number of overall hits +system.cpu0.dcache.overall_hits::total 23171400 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 186238 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 182678 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 368916 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 123980 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 126580 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250560 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5767 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5644 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11411 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 310218 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 309258 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619476 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 310218 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 309258 # number of overall misses +system.cpu0.dcache.overall_misses::total 619476 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2656146500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2591895000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5248041500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4024715000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4035571500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8060286500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80055500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 75055500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 155111000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6680861500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 6627466500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13308328000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6680861500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 6627466500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13308328000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6696682 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6869387 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13566069 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5010796 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5214011 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10224807 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 112519 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135214 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135213 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247732 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11707478 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12083398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23790876 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11707478 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12083398 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23790876 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027810 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026593 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027194 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024743 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024277 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048849 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043678 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046074 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026368 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025718 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026042 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025718 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026042 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14265.219794 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14158.017994 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14212.684919 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31620.617861 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32547.377682 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32087.271116 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13890.156919 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13356.982952 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13618.922470 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21172.276556 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21715.347357 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21441.371290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21172.276556 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21715.347357 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21441.371290 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051254 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.041741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046062 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026497 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025594 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026497 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025594 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14262.108163 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14188.325907 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14225.573030 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32462.614938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31881.588719 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32169.087245 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13881.654240 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13298.281361 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13593.111910 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21483.201932 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21483.201932 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,81 +870,81 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596435 # number of writebacks -system.cpu0.dcache.writebacks::total 596435 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188176 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 180837 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369013 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 124397 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126167 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250564 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5608 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11415 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 312573 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307004 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619577 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 312573 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307004 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619577 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308020000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198619500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506639500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684716000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854071000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7538787000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66680000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65950000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992736000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052690500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12045426500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992736000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052690500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12045426500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377755000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718296000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096051000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611257000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088544500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699801500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 596298 # number of writebacks +system.cpu0.dcache.writebacks::total 596298 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186238 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368916 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 123980 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126580 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250560 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5767 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5644 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 310218 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619476 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 310218 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309258 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619476 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283670500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226539000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510209500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776755000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782411500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559166500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68521500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63767500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132289000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6060425500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6008950500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12069376000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6060425500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6008950500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12069376000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91364051500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90730862500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182094914000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9290730000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9409303500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18700033500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100989012000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806840500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795852500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027678 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026720 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024606 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024406 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654781500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100140166000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794947500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024277 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048849 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043678 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12265.219794 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12158.017994 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.684919 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29620.617861 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30547.377682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30087.271116 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.156919 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11356.982952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.922470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12262.108163 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.325907 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.573030 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.614938 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29881.588719 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.087245 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -961,68 +961,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7490951 # DTB read hits -system.cpu1.dtb.read_misses 7083 # DTB read misses -system.cpu1.dtb.write_hits 5680260 # DTB write hits -system.cpu1.dtb.write_misses 1778 # DTB write misses -system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7594464 # DTB read hits +system.cpu1.dtb.read_misses 6935 # DTB read misses +system.cpu1.dtb.write_hits 5731015 # DTB write hits +system.cpu1.dtb.write_misses 1760 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6452 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7498034 # DTB read accesses -system.cpu1.dtb.write_accesses 5682038 # DTB write accesses +system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7601399 # DTB read accesses +system.cpu1.dtb.write_accesses 5732775 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13171211 # DTB hits -system.cpu1.dtb.misses 8861 # DTB misses -system.cpu1.dtb.accesses 13180072 # DTB accesses -system.cpu1.itb.inst_hits 30733845 # ITB inst hits -system.cpu1.itb.inst_misses 3661 # ITB inst misses +system.cpu1.dtb.hits 13325479 # DTB hits +system.cpu1.dtb.misses 8695 # DTB misses +system.cpu1.dtb.accesses 13334174 # DTB accesses +system.cpu1.itb.inst_hits 31195731 # ITB inst hits +system.cpu1.itb.inst_misses 3619 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1275 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2756 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2687 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30737506 # ITB inst accesses -system.cpu1.itb.hits 30733845 # DTB hits -system.cpu1.itb.misses 3661 # DTB misses -system.cpu1.itb.accesses 30737506 # DTB accesses -system.cpu1.numCycles 2664661810 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31199350 # ITB inst accesses +system.cpu1.itb.hits 31195731 # DTB hits +system.cpu1.itb.misses 3619 # DTB misses +system.cpu1.itb.accesses 31199350 # DTB accesses +system.cpu1.numCycles 2551680783 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30062381 # Number of instructions committed -system.cpu1.committedOps 38319191 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34454554 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses -system.cpu1.num_func_calls 1098878 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3931539 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34454554 # number of integer instructions -system.cpu1.num_fp_insts 4993 # number of float instructions -system.cpu1.num_int_register_reads 197476132 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37039734 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written -system.cpu1.num_mem_refs 13739046 # number of memory refs -system.cpu1.num_load_insts 7815505 # Number of load instructions -system.cpu1.num_store_insts 5923541 # Number of store instructions -system.cpu1.num_idle_cycles 1359990951.127739 # Number of idle cycles -system.cpu1.num_busy_cycles 1304670858.872261 # Number of busy cycles -system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles +system.cpu1.committedInsts 30572056 # Number of instructions committed +system.cpu1.committedOps 38927187 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34988620 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses +system.cpu1.num_func_calls 1115365 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34988620 # number of integer instructions +system.cpu1.num_fp_insts 5077 # number of float instructions +system.cpu1.num_int_register_reads 200559310 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37663253 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written +system.cpu1.num_mem_refs 13910244 # number of memory refs +system.cpu1.num_load_insts 7929876 # Number of load instructions +system.cpu1.num_store_insts 5980368 # Number of store instructions +system.cpu1.num_idle_cycles 10585260111.377636 # Number of idle cycles +system.cpu1.num_busy_cycles -8033579328.377636 # Number of busy cycles +system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles +system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.replacements 0 # number of replacements @@ -1039,10 +1039,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1196198690564 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1196198690564 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947260006 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1195947260006 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 33629e29f..59e0f30e1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -16,7 +16,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -1275,7 +1275,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1295,7 +1295,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index bf52a9da4..041d5bc34 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 3 2013 21:19:51 -gem5 started Mar 4 2013 00:22:16 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 27 2013 00:32:51 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5132857897000 because m5_exit instruction encountered +Exiting @ tick 5132865528000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2e53a645e..949b06658 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.136865 # Number of seconds simulated -sim_ticks 5136864508000 # Number of ticks simulated -final_tick 5136864508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132866 # Number of seconds simulated +sim_ticks 5132865528000 # Number of ticks simulated +final_tick 5132865528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157360 # Simulator instruction rate (inst/s) -host_op_rate 311060 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1981722494 # Simulator tick rate (ticks/s) -host_mem_usage 783288 # Number of bytes of host memory used -host_seconds 2592.12 # Real time elapsed on the host -sim_insts 407895398 # Number of instructions simulated -sim_ops 806304609 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2499136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +host_inst_rate 61482 # Simulator instruction rate (inst/s) +host_op_rate 121532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 773550742 # Simulator tick rate (ticks/s) +host_mem_usage 771808 # Number of bytes of host memory used +host_seconds 6635.46 # Real time elapsed on the host +sim_insts 407963797 # Number of instructions simulated +sim_ops 806422961 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2435200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1076928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10801024 # Number of bytes read from this memory -system.physmem.bytes_read::total 14380480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1076928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1076928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9561920 # Number of bytes written to this memory -system.physmem.bytes_written::total 9561920 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1080768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10867584 # Number of bytes read from this memory +system.physmem.bytes_read::total 14387264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1080768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1080768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9583040 # Number of bytes written to this memory +system.physmem.bytes_written::total 9583040 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16827 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168766 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224695 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149405 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149405 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 486510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16887 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169806 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224801 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149735 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149735 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 474433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2102649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2799466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1861431 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1861431 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1861431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 486510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2117255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2802969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 474433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2102649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4660898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224695 # Total number of read requests seen -system.physmem.writeReqs 149405 # Total number of write requests seen -system.physmem.cpureqs 378068 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14380480 # Total number of bytes read from memory -system.physmem.bytesWritten 9561920 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14380480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9561920 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 102 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3959 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15933 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9055 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8476 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11557 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8626 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8868 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8652 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 210558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2117255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4669965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224801 # Total number of read requests seen +system.physmem.writeReqs 149735 # Total number of write requests seen +system.physmem.cpureqs 378687 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14387264 # Total number of bytes read from memory +system.physmem.bytesWritten 9583040 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14387264 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9583040 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4143 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9192 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11578 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8737 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8467 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8901 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11873 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8670 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8399 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11146 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136864456000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132865474500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224695 # Categorize read packet sizes +system.physmem.readPktSize::6 224801 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149405 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149735 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -136,92 +136,92 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.totQLat 4766626250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9279378750 # Sum of mem lat for all requests -system.physmem.totBusLat 1122965000 # Total cycles spent in databus access -system.physmem.totBankLat 3389787500 # Total cycles spent in bank access -system.physmem.avgQLat 21223.40 # Average queueing delay per request -system.physmem.avgBankLat 15093.02 # Average bank access latency per request +system.physmem.wrQLenPdf::26 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.totQLat 4748150250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9279735250 # Sum of mem lat for all requests +system.physmem.totBusLat 1123565000 # Total cycles spent in databus access +system.physmem.totBankLat 3408020000 # Total cycles spent in bank access +system.physmem.avgQLat 21129.84 # Average queueing delay per request +system.physmem.avgBankLat 15166.10 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41316.42 # Average memory access latency +system.physmem.avgMemAccLat 41295.94 # Average memory access latency system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.02 # Average write queue length over time -system.physmem.readRowHits 193644 # Number of row buffer hits during reads -system.physmem.writeRowHits 105706 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.75 # Row buffer hit rate for writes -system.physmem.avgGap 13731260.24 # Average gap between requests -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.116323 # Cycle average of tags in use +system.physmem.avgWrQLen 10.74 # Average write queue length over time +system.physmem.readRowHits 193533 # Number of row buffer hits during reads +system.physmem.writeRowHits 105971 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes +system.physmem.avgGap 13704598.42 # Average gap between requests +system.iocache.replacements 47575 # number of replacements +system.iocache.tagsinuse 0.104035 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.116323 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.warmup_cycle 4991882227000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.104035 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006502 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006502 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144901871 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144901871 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053199611 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10053199611 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10198101482 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10198101482 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10198101482 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10198101482 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142432660 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 142432660 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10000305290 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10000305290 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10142737950 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10142737950 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10142737950 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10142737950 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 159407.998900 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.786194 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 215179.786194 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214115.381007 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214115.381007 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 138033 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156519.406593 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 156519.406593 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214047.630351 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214047.630351 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 212948.518791 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 212948.518791 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 135861 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12531 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12418 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.015322 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.940651 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97611900 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97611900 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622412826 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7622412826 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7720024726 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7720024726 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95090941 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95090941 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7569522729 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7569522729 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7664613670 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7664613670 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107383.828383 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163150.959461 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.959461 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104495.539560 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 104495.539560 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -293,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86192778 # Number of BP lookups -system.cpu.branchPred.condPredicted 86192778 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1105969 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81285940 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79207876 # Number of BTB hits +system.cpu.branchPred.lookups 86256793 # Number of BP lookups +system.cpu.branchPred.condPredicted 86256793 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1113068 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81525739 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79259204 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.443514 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.219853 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448117283 # number of cpu cycles simulated +system.cpu.numCycles 448546895 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27407295 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425903825 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86192778 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79207876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163564309 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4697150 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125610 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63070837 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 35658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 51192 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9007924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 482953 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2789 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257808166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.261396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27629675 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426131263 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86256793 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79259204 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163637829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4743979 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122519 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63152705 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51550 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9043434 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 488848 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3024 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258223805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.257780 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94670555 36.72% 36.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1565511 0.61% 37.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71913522 27.89% 65.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935622 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1598852 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2418850 0.94% 67.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1070189 0.42% 67.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1376236 0.53% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82258829 31.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95012138 36.79% 36.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1565899 0.61% 37.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71926197 27.85% 65.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935616 0.36% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1604506 0.62% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2433567 0.94% 67.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1079084 0.42% 67.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1383528 0.54% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82283270 31.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257808166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192344 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950429 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31124176 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60511588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159357091 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3262426 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3552885 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837683480 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3552885 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33860427 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37375460 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11010468 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159557932 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12450994 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834052267 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19515 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5867687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4751018 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8643 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995567635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810525606 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810524958 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964273740 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31293888 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 458980 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 466833 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28792477 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17053482 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10121038 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1248085 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 996765 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827936036 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1250306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823005910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148163 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21984013 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33436004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 197912 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257808166 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.192319 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383919 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258223805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192303 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950026 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31307096 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60630076 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159436775 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3257103 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3592755 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838113616 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 880 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3592755 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34040592 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37476959 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11041434 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159631550 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12440515 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834468110 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19385 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5834152 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4771877 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8971 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 996054249 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811560635 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811560099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964410768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31643474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457361 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464527 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28752334 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17095902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10132687 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1166436 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 902107 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828339786 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1247404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823331592 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149918 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22245950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33811662 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 194652 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258223805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.188442 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71353106 27.68% 27.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15525279 6.02% 33.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10289212 3.99% 37.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7463811 2.90% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75897283 29.44% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3839331 1.49% 71.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72507991 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 780183 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151970 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71699549 27.77% 27.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15529974 6.01% 33.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10286408 3.98% 37.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7471868 2.89% 40.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75917572 29.40% 70.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3857166 1.49% 71.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72524361 28.09% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 784342 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152565 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257808166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258223805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 363662 34.07% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553259 51.83% 85.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150581 14.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 368681 34.39% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552933 51.58% 85.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150329 14.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 310965 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795485356 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310005 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795767028 96.65% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -457,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17833485 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9376104 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17865255 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9389304 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823005910 # Type of FU issued -system.cpu.iq.rate 1.836586 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1067502 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905165811 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851180208 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818537057 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 302 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823762347 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1638684 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823331592 # Type of FU issued +system.cpu.iq.rate 1.835553 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1071943 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906239242 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851843261 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818849223 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824093432 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1643495 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3078529 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22784 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11411 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1710138 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3116410 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23570 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11612 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1711798 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12218 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932508 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11844 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3552885 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26109999 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2115264 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829186342 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321096 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17053482 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10121038 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 718511 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615692 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10262 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11411 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 648780 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593291 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1242071 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821133450 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17423083 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1872459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3592755 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26248050 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2110636 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829587190 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 321004 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17095902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10132687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 717072 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1612321 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11848 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11612 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 657039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 595254 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1252293 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821445338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17448687 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1886253 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26567058 # number of memory reference insts executed -system.cpu.iew.exec_branches 83190955 # Number of branches executed -system.cpu.iew.exec_stores 9143975 # Number of stores executed -system.cpu.iew.exec_rate 1.832407 # Inst execution rate -system.cpu.iew.wb_sent 820672114 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818537115 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639752264 # num instructions producing a value -system.cpu.iew.wb_consumers 1045484939 # num instructions consuming a value +system.cpu.iew.exec_refs 26607218 # number of memory reference insts executed +system.cpu.iew.exec_branches 83228491 # Number of branches executed +system.cpu.iew.exec_stores 9158531 # Number of stores executed +system.cpu.iew.exec_rate 1.831348 # Inst execution rate +system.cpu.iew.wb_sent 820983226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818849277 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639988645 # num instructions producing a value +system.cpu.iew.wb_consumers 1045811759 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826614 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825560 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611954 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22773726 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052392 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1110510 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254255281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.171240 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853929 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23057499 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052750 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1117600 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254631050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.167025 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854459 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82490050 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11810591 4.65% 37.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3912535 1.54% 38.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74936309 29.47% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436608 0.96% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1481517 0.58% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 940613 0.37% 70.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70914138 27.89% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5332920 2.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82837862 32.53% 32.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11822724 4.64% 37.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3905327 1.53% 38.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74951929 29.44% 68.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2438342 0.96% 69.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480698 0.58% 69.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927919 0.36% 70.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70920568 27.85% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5345681 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254255281 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407895398 # Number of instructions committed -system.cpu.commit.committedOps 806304609 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254631050 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963797 # Number of instructions committed +system.cpu.commit.committedOps 806422961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22385850 # Number of memory references committed -system.cpu.commit.loads 13974950 # Number of loads committed -system.cpu.commit.membars 473369 # Number of memory barriers committed -system.cpu.commit.branches 82185287 # Number of branches committed +system.cpu.commit.refs 22400378 # Number of memory references committed +system.cpu.commit.loads 13979489 # Number of loads committed +system.cpu.commit.membars 473507 # Number of memory barriers committed +system.cpu.commit.branches 82198469 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735250581 # Number of committed integer instructions. +system.cpu.commit.int_insts 735362199 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5332920 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5345681 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1077922480 # The number of ROB reads -system.cpu.rob.rob_writes 1661728217 # The number of ROB writes -system.cpu.timesIdled 1219694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190309117 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9825609154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407895398 # Number of Instructions Simulated -system.cpu.committedOps 806304609 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407895398 # Number of Instructions Simulated -system.cpu.cpi 1.098608 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098608 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910243 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910243 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506572228 # number of integer regfile reads -system.cpu.int_regfile_writes 976715078 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.misc_regfile_reads 264599077 # number of misc regfile reads -system.cpu.misc_regfile_writes 402085 # number of misc regfile writes -system.cpu.icache.replacements 1045531 # number of replacements -system.cpu.icache.tagsinuse 510.125027 # Cycle average of tags in use -system.cpu.icache.total_refs 7898981 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1046043 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.551297 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.125027 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7898981 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7898981 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7898981 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7898981 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7898981 # number of overall hits -system.cpu.icache.overall_hits::total 7898981 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108941 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108941 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108941 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108941 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108941 # number of overall misses -system.cpu.icache.overall_misses::total 1108941 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254214993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15254214993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15254214993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15254214993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15254214993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15254214993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9007922 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9007922 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9007922 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9007922 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9007922 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9007922 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123107 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123107 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123107 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123107 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123107 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123107 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13755.659673 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13755.659673 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13755.659673 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13755.659673 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 11697 # number of cycles access was blocked +system.cpu.rob.rob_reads 1078687614 # The number of ROB reads +system.cpu.rob.rob_writes 1662572605 # The number of ROB writes +system.cpu.timesIdled 1222238 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190323090 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817181581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963797 # Number of Instructions Simulated +system.cpu.committedOps 806422961 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963797 # Number of Instructions Simulated +system.cpu.cpi 1.099477 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099477 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909523 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909523 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1507059295 # number of integer regfile reads +system.cpu.int_regfile_writes 977046319 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 264741173 # number of misc regfile reads +system.cpu.misc_regfile_writes 402265 # number of misc regfile writes +system.cpu.icache.replacements 1056074 # number of replacements +system.cpu.icache.tagsinuse 510.395640 # Cycle average of tags in use +system.cpu.icache.total_refs 7921465 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1056586 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.497227 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56044666000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.395640 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996866 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996866 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7921465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7921465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7921465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7921465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7921465 # number of overall hits +system.cpu.icache.overall_hits::total 7921465 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1121968 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1121968 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1121968 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1121968 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1121968 # number of overall misses +system.cpu.icache.overall_misses::total 1121968 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15396039491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15396039491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15396039491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15396039491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15396039491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15396039491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9043433 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9043433 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9043433 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9043433 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9043433 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9043433 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13722.351699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13722.351699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13722.351699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13722.351699 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 11326 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 280 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.775000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.229008 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60573 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60573 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60573 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60573 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60573 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60573 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048368 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1048368 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1048368 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1048368 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1048368 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1048368 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12562155993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12562155993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12562155993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12562155993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12562155993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12562155993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116383 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116383 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116383 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.582445 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.582445 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62943 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62943 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62943 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62943 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62943 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62943 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1059025 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1059025 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1059025 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1059025 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1059025 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1059025 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12680665992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12680665992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12680665992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12680665992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12680665992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12680665992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117104 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117104 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117104 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11973.906180 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11973.906180 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9623 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.015619 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25274 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9637 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.622600 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103989981500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.015619 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375976 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375976 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25281 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25281 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9902 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.007248 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25368 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9915 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.558548 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5106962474500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007248 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375453 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375453 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25400 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25400 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25283 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25283 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25283 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25283 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10506 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10506 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10506 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10506 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10506 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10506 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117420000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117420000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117420000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 117420000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117420000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 117420000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 35787 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 35787 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25402 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25402 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25402 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25402 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10789 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10789 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10789 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10789 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10789 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10789 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118480500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118480500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118480500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 118480500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118480500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 118480500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36189 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36189 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 35789 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 35789 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 35789 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 35789 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.293570 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.293570 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.293554 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.293554 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.293554 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.293554 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11176.470588 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11176.470588 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11176.470588 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11176.470588 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36191 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36191 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36191 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36191 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298129 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298129 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298113 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.298113 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298113 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.298113 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10981.601631 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10981.601631 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10981.601631 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10981.601631 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1917 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1917 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10506 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10506 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10506 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10506 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10506 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10506 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96408000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96408000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96408000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96408000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96408000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96408000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.293570 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.293570 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.293554 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.293554 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.470588 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2074 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2074 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10789 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10789 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10789 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10789 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10789 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10789 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96902500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96902500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96902500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96902500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96902500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96902500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298129 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298129 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298113 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298113 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8981.601631 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 107366 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.959117 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135123 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 107381 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.258351 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959117 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809945 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809945 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135139 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135139 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135139 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135139 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135139 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135139 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108408 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 108408 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108408 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 108408 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108408 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 108408 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1365628000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1365628000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1365628000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1365628000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1365628000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1365628000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243547 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 243547 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243547 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 243547 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243547 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 243547 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.445121 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.445121 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.445121 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.445121 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.445121 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.445121 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12597.114604 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12597.114604 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12597.114604 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12597.114604 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 112679 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.888368 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 129664 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 112694 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.150585 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5099752322000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.888368 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.868023 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.868023 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 129683 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 129683 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 129683 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 129683 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 129683 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 129683 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113702 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 113702 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113702 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 113702 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113702 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 113702 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1421375500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1421375500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1421375500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1421375500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1421375500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1421375500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243385 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 243385 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243385 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 243385 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243385 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 243385 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.467169 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.467169 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.467169 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.467169 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.467169 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.467169 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12500.883889 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12500.883889 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12500.883889 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12500.883889 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35267 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35267 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108408 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108408 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108408 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 108408 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108408 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 108408 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1148812000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1148812000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1148812000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.445121 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.445121 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.445121 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10597.114604 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35808 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35808 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113702 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113702 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113702 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 113702 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113702 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 113702 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1193971500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1193971500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1193971500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.467169 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.467169 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.467169 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10500.883889 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1660204 # number of replacements -system.cpu.dcache.tagsinuse 511.993130 # Cycle average of tags in use -system.cpu.dcache.total_refs 19074634 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660716 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.485789 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1659172 # number of replacements +system.cpu.dcache.tagsinuse 511.998283 # Cycle average of tags in use +system.cpu.dcache.total_refs 19096669 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1659684 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.506208 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.993130 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10985848 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10985848 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8083807 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8083807 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19069655 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19069655 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19069655 # number of overall hits -system.cpu.dcache.overall_hits::total 19069655 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2236198 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2236198 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317897 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317897 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2554095 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2554095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2554095 # number of overall misses -system.cpu.dcache.overall_misses::total 2554095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32136809500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32136809500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9657348993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9657348993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41794158493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41794158493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41794158493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41794158493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13222046 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13222046 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8401704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8401704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21623750 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21623750 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21623750 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21623750 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169126 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118115 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118115 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118115 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118115 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14371.182471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14371.182471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30378.861685 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30378.861685 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16363.588078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16363.588078 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 398738 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.998283 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999997 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999997 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10998697 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10998697 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8092860 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8092860 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19091557 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19091557 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19091557 # number of overall hits +system.cpu.dcache.overall_hits::total 19091557 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2244277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2244277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318772 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2563049 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2563049 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2563049 # number of overall misses +system.cpu.dcache.overall_misses::total 2563049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32186629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32186629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9715417494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9715417494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41902046494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41902046494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41902046494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41902046494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13242974 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13242974 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8411632 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8411632 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21654606 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21654606 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21654606 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21654606 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037897 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037897 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118360 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118360 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118360 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14341.647221 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14341.647221 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30477.637603 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30477.637603 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16348.515574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16348.515574 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 394709 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43025 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.377878 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.173945 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561580 # number of writebacks -system.cpu.dcache.writebacks::total 1561580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863817 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 863817 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25014 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25014 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 888831 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 888831 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 888831 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 888831 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372381 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1372381 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292883 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292883 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1665264 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1665264 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1665264 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1665264 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17480696000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17480696000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8813584993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8813584993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26294280993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26294280993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26294280993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26294280993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97294541500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97294541500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2465874000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2465874000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99760415500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99760415500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077011 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077011 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077011 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077011 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12737.494908 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12737.494908 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30092.511320 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30092.511320 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.857340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.857340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.857340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.857340 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1560811 # number of writebacks +system.cpu.dcache.writebacks::total 1560811 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 872480 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 872480 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26264 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 898744 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 898744 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 898744 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 898744 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371797 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1371797 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292508 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 292508 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1664305 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1664305 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1664305 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1664305 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17453179000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17453179000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8875888494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8875888494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26329067494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26329067494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26329067494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26329067494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298479500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298479500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473755000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473755000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99772234500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99772234500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034774 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034774 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12722.858411 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12722.858411 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30344.088004 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30344.088004 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -932,141 +932,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113491 # number of replacements -system.cpu.l2cache.tagsinuse 64842.078955 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3927958 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 177583 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.118998 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 113709 # number of replacements +system.cpu.l2cache.tagsinuse 64835.556178 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3943740 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 177736 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.188752 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50032.816197 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.886318 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133448 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3280.359245 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11517.883747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.763440 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50100.135073 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 8.974222 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131215 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3272.117566 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11454.198102 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.764467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000137 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175749 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989412 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101572 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1029165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1334330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2473204 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1598764 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1598764 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 341 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 341 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 156095 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 156095 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 101572 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1029165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1490425 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2629299 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 101572 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1029165 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1490425 # number of overall hits -system.cpu.l2cache.overall_hits::total 2629299 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.049929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.174777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989312 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 105558 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8113 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1039658 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333728 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2487057 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1598693 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1598693 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154593 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154593 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 105558 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 8113 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1039658 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1488321 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2641650 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 105558 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 8113 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1039658 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1488321 # number of overall hits +system.cpu.l2cache.overall_hits::total 2641650 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16828 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36875 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 53756 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3686 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3686 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132834 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132834 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16888 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36900 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 53846 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3866 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3866 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133854 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133854 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169709 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186590 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 47 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 16888 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 170754 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 187700 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16828 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169709 # number of overall misses -system.cpu.l2cache.overall_misses::total 186590 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6046500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 16888 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 170754 # number of overall misses +system.cpu.l2cache.overall_misses::total 187700 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4568000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1168943500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2535282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3710661500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17110500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17110500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6867635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6867635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6046500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1172288500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2518183499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3695429499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17446500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17446500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6941993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6941993500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4568000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1168943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9402917000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10578296500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6046500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1172288500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9460176999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10637422999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4568000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1168943500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9402917000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10578296500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101619 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8143 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1045993 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1371205 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2526960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1598764 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1598764 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4027 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4027 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288929 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288929 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101619 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8143 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1045993 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1660134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2815889 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101619 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8143 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1045993 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1660134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2815889 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000463 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000737 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016088 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026892 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021273 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915322 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915322 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459746 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.459746 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000463 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016088 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102226 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.066263 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000463 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016088 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102226 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.066263 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128648.936170 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 1172288500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9460176999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10637422999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 105610 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8119 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1056546 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1370628 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2540903 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1598693 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1598693 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4187 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4187 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288447 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288447 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 105610 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 8119 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1056546 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1659075 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2829350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 105610 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 8119 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1056546 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1659075 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2829350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000492 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000739 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015984 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026922 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021192 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.923334 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.923334 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464051 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.464051 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000492 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000739 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015984 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102921 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.066340 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000492 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000739 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015984 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102921 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.066340 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87846.153846 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69464.196577 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68753.410169 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69027.857355 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4642.023874 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4642.023874 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51700.882304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51700.882304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128648.936170 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69415.472525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68243.455257 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68629.601066 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4512.803932 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4512.803932 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51862.428467 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51862.428467 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69464.196577 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55406.118709 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56692.730050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128648.936170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56672.472025 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69464.196577 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55406.118709 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56692.730050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56672.472025 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,8 +1075,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102738 # number of writebacks -system.cpu.l2cache.writebacks::total 102738 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 103068 # number of writebacks +system.cpu.l2cache.writebacks::total 103068 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -1086,88 +1086,88 @@ system.cpu.l2cache.demand_mshr_hits::total 2 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 47 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16827 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36874 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 53754 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3686 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3686 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132834 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132834 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 47 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16887 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36899 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53844 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3866 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3866 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133854 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 186588 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 47 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16887 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 170753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 187698 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16827 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 186588 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5461043 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16887 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 170753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 187698 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3916050 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 959626979 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2076990471 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3042392748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37820166 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37820166 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5229334603 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5229334603 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5461043 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 962195275 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2059471232 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3025896812 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39657846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39657846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5291032825 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5291032825 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3916050 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 959626979 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7306325074 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8271727351 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5461043 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 962195275 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7350504057 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8316929637 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3916050 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 959626979 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7306325074 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8271727351 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185441500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185441500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304074500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304074500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489516000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489516000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026892 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915322 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915322 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459746 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459746 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.066263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.066263 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 962195275 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7350504057 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8316929637 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89189069500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89189069500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2311324000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2311324000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91500393500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91500393500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.923334 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.923334 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464051 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464051 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066340 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066340 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57028.999762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56326.692819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56598.443800 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10260.489962 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10260.489962 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39367.440588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39367.440588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56978.461242 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55813.741077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56197.474408 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10258.108122 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10258.108122 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39528.387833 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39528.387833 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |