diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/fs/10.linux-boot | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/fs/10.linux-boot')
10 files changed, 4923 insertions, 4895 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 70213a160..da3261384 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:49 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:11:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897464893500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107002000 +Exiting @ tick 1899401490000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 89ae1dc03..af2074343 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,179 +1,179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897464893500 # Number of ticks simulated -final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899401 # Number of seconds simulated +sim_ticks 1899401490000 # Number of ticks simulated +final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189830 # Simulator instruction rate (inst/s) -host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6418636186 # Simulator tick rate (ticks/s) -host_mem_usage 296280 # Number of bytes of host memory used -host_seconds 295.62 # Real time elapsed on the host -sim_insts 56117221 # Number of instructions simulated -sim_ops 56117221 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30408512 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10470144 # Number of bytes written to this memory -system.physmem.num_reads 475133 # Number of read requests responded to by this memory -system.physmem.num_writes 163596 # Number of write requests responded to by this memory +host_inst_rate 189434 # Simulator instruction rate (inst/s) +host_op_rate 189434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6363739723 # Simulator tick rate (ticks/s) +host_mem_usage 296196 # Number of bytes of host memory used +host_seconds 298.47 # Real time elapsed on the host +sim_insts 56540749 # Number of instructions simulated +sim_ops 56540749 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10508736 # Number of bytes written to this memory +system.physmem.num_reads 475339 # Number of read requests responded to by this memory +system.physmem.num_writes 164199 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397850 # number of replacements -system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use -system.l2c.total_refs 2482376 # Total number of references to valid blocks. -system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.062074 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 109195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 38109 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits -system.l2c.Writeback_hits::total 827202 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits -system.l2c.overall_hits::cpu0.data 932654 # number of overall hits -system.l2c.overall_hits::cpu1.inst 109195 # number of overall hits -system.l2c.overall_hits::cpu1.data 49204 # number of overall hits -system.l2c.overall_hits::total 2046785 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 15234 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 290346 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1960 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2086 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 562 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 45 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 84 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113888 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 102548000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 110604500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16117985000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2465000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1619000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4084000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 420000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 629500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5974507500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 563694000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6538201500 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 111155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 40195 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 827202 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2622 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 111 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 282068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21841 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 970966 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1336888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 111155 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 62036 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 970966 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1336888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 111155 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 62036 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015690 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.275256 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.017633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.051897 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.925865 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.608108 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756757 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.403761 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.492010 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015690 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.302369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206848 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.302369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206848 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52034.407224 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52320.408163 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53022.291467 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1007.355946 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2880.782918 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency +system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 397771 # number of replacements +system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use +system.l2c.total_refs 2469954 # Total number of references to valid blocks. +system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 117817 # 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mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # 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average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -293,81 +293,81 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.463236 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.205020 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # 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average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -385,22 +385,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9525013 # DTB read hits -system.cpu0.dtb.read_misses 35809 # DTB read misses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_accesses 640960 # DTB read accesses -system.cpu0.dtb.write_hits 6193277 # DTB write hits -system.cpu0.dtb.write_misses 8191 # DTB write misses -system.cpu0.dtb.write_acv 352 # DTB write access violations -system.cpu0.dtb.write_accesses 218947 # DTB write accesses -system.cpu0.dtb.data_hits 15718290 # DTB hits -system.cpu0.dtb.data_misses 44000 # DTB misses -system.cpu0.dtb.data_acv 948 # DTB access violations -system.cpu0.dtb.data_accesses 859907 # DTB accesses -system.cpu0.itb.fetch_hits 1059968 # ITB hits -system.cpu0.itb.fetch_misses 28334 # ITB misses -system.cpu0.itb.fetch_acv 968 # ITB acv -system.cpu0.itb.fetch_accesses 1088302 # ITB accesses +system.cpu0.dtb.read_hits 8814586 # DTB read hits +system.cpu0.dtb.read_misses 32972 # DTB read misses +system.cpu0.dtb.read_acv 518 # DTB read access violations +system.cpu0.dtb.read_accesses 619797 # DTB read accesses +system.cpu0.dtb.write_hits 5858085 # DTB write hits +system.cpu0.dtb.write_misses 6892 # DTB write misses +system.cpu0.dtb.write_acv 315 # DTB write access violations +system.cpu0.dtb.write_accesses 207416 # DTB write accesses +system.cpu0.dtb.data_hits 14672671 # DTB hits +system.cpu0.dtb.data_misses 39864 # DTB misses +system.cpu0.dtb.data_acv 833 # DTB access violations +system.cpu0.dtb.data_accesses 827213 # DTB accesses +system.cpu0.itb.fetch_hits 1034325 # ITB hits +system.cpu0.itb.fetch_misses 27665 # ITB misses +system.cpu0.itb.fetch_acv 1025 # ITB acv +system.cpu0.itb.fetch_accesses 1061990 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -413,279 +413,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112143855 # number of cpu cycles simulated +system.cpu0.numCycles 105407779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued -system.cpu0.iq.rate 0.489688 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued +system.cpu0.iq.rate 0.482387 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3514446 # number of nop insts executed -system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8658040 # Number of branches executed -system.cpu0.iew.exec_stores 6215854 # Number of stores executed -system.cpu0.iew.exec_rate 0.483991 # Inst execution rate -system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26555285 # num instructions producing a value -system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value +system.cpu0.iew.exec_nop 3218084 # number of nop insts executed +system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7980527 # Number of branches executed +system.cpu0.iew.exec_stores 5879131 # Number of stores executed +system.cpu0.iew.exec_rate 0.477396 # Inst execution rate +system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24623982 # num instructions producing a value +system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 53643051 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53643051 # Number of instructions committed -system.cpu0.commit.committedOps 53643051 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50284711 # Number of instructions committed +system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14593748 # Number of memory references committed -system.cpu0.commit.loads 8594447 # Number of loads committed -system.cpu0.commit.membars 217509 # Number of memory barriers committed -system.cpu0.commit.branches 8090596 # Number of branches committed -system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. -system.cpu0.commit.function_calls 704226 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13762834 # Number of memory references committed +system.cpu0.commit.loads 8083571 # Number of loads committed +system.cpu0.commit.membars 205088 # Number of memory barriers committed +system.cpu0.commit.branches 7564309 # Number of branches committed +system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. +system.cpu0.commit.function_calls 644133 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136894487 # The number of ROB reads -system.cpu0.rob.rob_writes 125011331 # The number of ROB writes -system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50529139 # Number of Instructions Simulated -system.cpu0.committedOps 50529139 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated -system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads -system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes -system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads -system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes +system.cpu0.rob.rob_reads 126892294 # The number of ROB reads +system.cpu0.rob.rob_writes 115369853 # The number of ROB writes +system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47376653 # Number of Instructions Simulated +system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated +system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads +system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes +system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads +system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -717,211 +717,211 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 970410 # number of replacements -system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use -system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.008513 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7511566 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7511566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7511566 # number of overall hits -system.cpu0.icache.overall_hits::total 7511566 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1025306 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1025306 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1025306 # number of overall misses -system.cpu0.icache.overall_misses::total 1025306 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15323045497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15323045497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8536872 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8536872 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120103 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120103 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120103 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked +system.cpu0.icache.replacements 923652 # number of replacements +system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use +system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits +system.cpu0.icache.overall_hits::total 6902434 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses +system.cpu0.icache.overall_misses::total 973969 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 220 # number of writebacks -system.cpu0.icache.writebacks::total 220 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54249 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54249 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 971057 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 971057 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 971057 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 971057 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 196 # number of writebacks +system.cpu0.icache.writebacks::total 196 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1340651 # number of replacements -system.cpu0.dcache.tagsinuse 504.872538 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19222000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.872538 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6993872 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3966970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 182544 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208490 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10960842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10960842 # number of overall hits -system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1697480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1808304 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21693 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 688 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3505784 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3505784 # number of overall misses -system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92214768853 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92214768853 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195307 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.313111 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106215 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003289 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.242336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.242336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9218.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked +system.cpu0.dcache.replacements 1225027 # number of replacements +system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits +system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses +system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 791009 # number of writebacks -system.cpu0.dcache.writebacks::total 791009 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2175152 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2175152 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330632 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330632 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049268 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.082399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003289 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6205.668605 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks +system.cpu0.dcache.writebacks::total 689568 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency @@ -930,22 +930,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1327892 # DTB read hits -system.cpu1.dtb.read_misses 10318 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 331425 # DTB read accesses -system.cpu1.dtb.write_hits 775217 # DTB write hits -system.cpu1.dtb.write_misses 3380 # DTB write misses -system.cpu1.dtb.write_acv 51 # DTB write access violations -system.cpu1.dtb.write_accesses 128049 # DTB write accesses -system.cpu1.dtb.data_hits 2103109 # DTB hits -system.cpu1.dtb.data_misses 13698 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 459474 # DTB accesses -system.cpu1.itb.fetch_hits 367800 # ITB hits -system.cpu1.itb.fetch_misses 7781 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 375581 # ITB accesses +system.cpu1.dtb.read_hits 1967803 # DTB read hits +system.cpu1.dtb.read_misses 13979 # DTB read misses +system.cpu1.dtb.read_acv 50 # DTB read access violations +system.cpu1.dtb.read_accesses 344857 # DTB read accesses +system.cpu1.dtb.write_hits 1156959 # DTB write hits +system.cpu1.dtb.write_misses 3426 # DTB write misses +system.cpu1.dtb.write_acv 86 # DTB write access violations +system.cpu1.dtb.write_accesses 133134 # DTB write accesses +system.cpu1.dtb.data_hits 3124762 # DTB hits +system.cpu1.dtb.data_misses 17405 # DTB misses +system.cpu1.dtb.data_acv 136 # DTB access violations +system.cpu1.dtb.data_accesses 477991 # DTB accesses +system.cpu1.itb.fetch_hits 421916 # ITB hits +system.cpu1.itb.fetch_misses 9109 # ITB misses +system.cpu1.itb.fetch_acv 356 # ITB acv +system.cpu1.itb.fetch_accesses 431025 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -958,643 +958,647 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9964881 # number of cpu cycles simulated +system.cpu1.numCycles 16642884 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits +system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued -system.cpu1.iq.rate 0.630911 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued +system.cpu1.iq.rate 0.613946 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 264808 # number of nop insts executed -system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed -system.cpu1.iew.exec_branches 906293 # Number of branches executed -system.cpu1.iew.exec_stores 781951 # Number of stores executed -system.cpu1.iew.exec_rate 0.623044 # Inst execution rate -system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2959215 # num instructions producing a value -system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value +system.cpu1.iew.exec_nop 532071 # number of nop insts executed +system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1559516 # Number of branches executed +system.cpu1.iew.exec_stores 1165063 # Number of stores executed +system.cpu1.iew.exec_rate 0.606457 # Inst execution rate +system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4916782 # num instructions producing a value +system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 5811574 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5811574 # Number of instructions committed -system.cpu1.commit.committedOps 5811574 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9615778 # Number of instructions committed +system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1881487 # Number of memory references committed -system.cpu1.commit.loads 1153406 # Number of loads committed -system.cpu1.commit.membars 20496 # Number of memory barriers committed -system.cpu1.commit.branches 821024 # Number of branches committed -system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89377 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2823987 # Number of memory references committed +system.cpu1.commit.loads 1739300 # Number of loads committed +system.cpu1.commit.membars 35653 # Number of memory barriers committed +system.cpu1.commit.branches 1422938 # Number of branches committed +system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. +system.cpu1.commit.function_calls 153476 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15919643 # The number of ROB reads -system.cpu1.rob.rob_writes 14461697 # The number of ROB writes -system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5588082 # Number of Instructions Simulated -system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated -system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads -system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes -system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes -system.cpu1.icache.replacements 110606 # number of replacements -system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use -system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 453.435417 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 936898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 936898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 936898 # number of overall hits -system.cpu1.icache.overall_hits::total 936898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 116421 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 116421 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 116421 # number of overall misses -system.cpu1.icache.overall_misses::total 116421 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1750783999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1750783999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1053319 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1053319 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110528 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 25542136 # The number of ROB reads +system.cpu1.rob.rob_writes 23473924 # The number of ROB writes +system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9164096 # Number of Instructions Simulated +system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated +system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads +system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes +system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads +system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes +system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads +system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes +system.cpu1.icache.replacements 177236 # number of replacements +system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use +system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits +system.cpu1.icache.overall_hits::total 1491482 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses +system.cpu1.icache.overall_misses::total 188398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 37 # number of writebacks -system.cpu1.icache.writebacks::total 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5236 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 5236 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 5236 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 5236 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 111185 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 111185 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 111185 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 111185 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 52 # number of writebacks +system.cpu1.icache.writebacks::total 52 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62388 # number of replacements -system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 392.324021 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1127254 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 549515 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16791 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14923 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1676769 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1676769 # number of overall hits -system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 106582 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 157839 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1481 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 695 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 264421 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 264421 # number of overall misses -system.cpu1.dcache.overall_misses::total 264421 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6969056280 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6969056280 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked +system.cpu1.dcache.replacements 156190 # number of replacements +system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 22430 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2413851 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2413851 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2413851 # number of overall hits +system.cpu1.dcache.overall_hits::total 2413851 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 229184 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 229184 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 231703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 231703 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 3831 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 3831 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 1979 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 1979 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses +system.cpu1.dcache.overall_misses::total 460887 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks -system.cpu1.dcache.writebacks::total 35937 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks +system.cpu1.dcache.writebacks::total 116478 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.88% 28.37% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 28.84% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.72% 32.56% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.65% 37.21% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.79% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 40.47% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.40% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.79% 44.65% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 45.58% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.35% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.40% 62.33% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.65% 66.98% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.65% 71.63% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 72.09% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.79% 74.88% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.70% 85.58% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 86.98% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.79% 89.77% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 90.23% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.40% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.19% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.14% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed +system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed +system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed +system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184665 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches +system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed +system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 175342 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1248 -system.cpu0.kern.mode_good::user 1249 +system.cpu0.kern.mode_good::kernel 1161 +system.cpu0.kern.mode_good::user 1162 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3841 # number of times the context was actually changed +system.cpu0.kern.swap_context 3714 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.90% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.31% 27.93% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.70% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.70% 33.33% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.50% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::45 21 18.92% 56.76% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.70% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.90% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::71 31 27.93% 88.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.01% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed +system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed +system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed -system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed +system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed +system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed +system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed +system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31730 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches -system.cpu1.kern.mode_switch::user 491 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 491 -system.cpu1.kern.mode_good::idle 30 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 42196 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 747 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 169 +system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 394 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 735 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index c3587ff5d..52235dbd6 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:47 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:10:30 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1859850554500 because m5_exit instruction encountered +Exiting @ tick 1858684403000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3b4a45a9b..da1fed07c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,115 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859851 # Number of seconds simulated -sim_ticks 1859850554500 # Number of ticks simulated -final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.858684 # Number of seconds simulated +sim_ticks 1858684403000 # Number of ticks simulated +final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188989 # Simulator instruction rate (inst/s) -host_op_rate 188989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6621174751 # Simulator tick rate (ticks/s) -host_mem_usage 292896 # Number of bytes of host memory used -host_seconds 280.89 # Real time elapsed on the host -sim_insts 53085804 # Number of instructions simulated -sim_ops 53085804 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29820864 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10193536 # Number of bytes written to this memory -system.physmem.num_reads 465951 # Number of read requests responded to by this memory -system.physmem.num_writes 159274 # Number of write requests responded to by this memory +host_inst_rate 192280 # Simulator instruction rate (inst/s) +host_op_rate 192280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6731751609 # Simulator tick rate (ticks/s) +host_mem_usage 292636 # Number of bytes of host memory used +host_seconds 276.11 # Real time elapsed on the host +sim_insts 53089851 # Number of instructions simulated +sim_ops 53089851 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 29847552 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10195968 # Number of bytes written to this memory +system.physmem.num_reads 466368 # Number of read requests responded to by this memory +system.physmem.num_writes 159312 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391353 # number of replacements -system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use -system.l2c.total_refs 2406767 # Total number of references to valid blocks. -system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits -system.l2c.Writeback_hits::total 835189 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 391653 # number of replacements +system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use +system.l2c.total_refs 2427420 # Total number of references to valid blocks. +system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits +system.l2c.Writeback_hits::total 834721 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 988583 # number of overall hits -system.l2c.overall_hits::cpu.data 995422 # number of overall hits -system.l2c.overall_hits::total 1984005 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 16626 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 994510 # 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number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21306631500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22191372500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,69 +121,81 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117762 # number of writebacks -system.l2c.writebacks::total 117762 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.writebacks::writebacks 117800 # number of writebacks +system.l2c.writebacks::total 117800 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1343000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1343000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4714582500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4714582500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 677644000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 16382770000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17060414000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 677644000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.276011 # Cycle average of tags in use +system.iocache.tagsinuse 1.266745 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -191,12 +206,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -210,14 +225,14 @@ system.iocache.WriteReq_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -233,20 +248,20 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -264,22 +279,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10136178 # DTB read hits -system.cpu.dtb.read_misses 46729 # DTB read misses -system.cpu.dtb.read_acv 584 # DTB read access violations -system.cpu.dtb.read_accesses 970980 # DTB read accesses -system.cpu.dtb.write_hits 6626287 # DTB write hits -system.cpu.dtb.write_misses 12218 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 347267 # DTB write accesses -system.cpu.dtb.data_hits 16762465 # DTB hits -system.cpu.dtb.data_misses 58947 # DTB misses -system.cpu.dtb.data_acv 1003 # DTB access violations -system.cpu.dtb.data_accesses 1318247 # DTB accesses -system.cpu.itb.fetch_hits 1326719 # ITB hits -system.cpu.itb.fetch_misses 39613 # ITB misses -system.cpu.itb.fetch_acv 1063 # ITB acv -system.cpu.itb.fetch_accesses 1366332 # ITB accesses +system.cpu.dtb.read_hits 10017178 # DTB read hits +system.cpu.dtb.read_misses 45828 # DTB read misses +system.cpu.dtb.read_acv 561 # DTB read access violations +system.cpu.dtb.read_accesses 954843 # DTB read accesses +system.cpu.dtb.write_hits 6639084 # DTB write hits +system.cpu.dtb.write_misses 10800 # DTB write misses +system.cpu.dtb.write_acv 415 # DTB write access violations +system.cpu.dtb.write_accesses 340295 # DTB write accesses +system.cpu.dtb.data_hits 16656262 # DTB hits +system.cpu.dtb.data_misses 56628 # DTB misses +system.cpu.dtb.data_acv 976 # DTB access violations +system.cpu.dtb.data_accesses 1295138 # DTB accesses +system.cpu.itb.fetch_hits 1345400 # ITB hits +system.cpu.itb.fetch_misses 36691 # ITB misses +system.cpu.itb.fetch_acv 1385 # ITB acv +system.cpu.itb.fetch_accesses 1382091 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,279 +307,279 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116271514 # number of cpu cycles simulated +system.cpu.numCycles 115937106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits +system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued -system.cpu.iq.rate 0.498544 # Inst issue rate -system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued +system.cpu.iq.rate 0.495930 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3625473 # number of nop insts executed -system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed -system.cpu.iew.exec_branches 9097936 # Number of branches executed -system.cpu.iew.exec_stores 6653902 # Number of stores executed -system.cpu.iew.exec_rate 0.492563 # Inst execution rate -system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28030988 # num instructions producing a value -system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value +system.cpu.iew.exec_nop 3587167 # number of nop insts executed +system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed +system.cpu.iew.exec_branches 9006504 # Number of branches executed +system.cpu.iew.exec_stores 6665235 # Number of stores executed +system.cpu.iew.exec_rate 0.490534 # Inst execution rate +system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27888094 # num instructions producing a value +system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back +system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56280196 # Number of instructions committed -system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56284358 # Number of instructions committed +system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15504446 # Number of memory references committed -system.cpu.commit.loads 9112319 # Number of loads committed -system.cpu.commit.membars 227818 # Number of memory barriers committed -system.cpu.commit.branches 8461284 # Number of branches committed +system.cpu.commit.refs 15505080 # Number of memory references committed +system.cpu.commit.loads 9112848 # Number of loads committed +system.cpu.commit.membars 227858 # Number of memory barriers committed +system.cpu.commit.branches 8462387 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52119152 # Number of committed integer instructions. -system.cpu.commit.function_calls 744404 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. +system.cpu.commit.function_calls 744427 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 143937484 # The number of ROB reads -system.cpu.rob.rob_writes 132136289 # The number of ROB writes -system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53085804 # Number of Instructions Simulated -system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated -system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75080091 # number of integer regfile reads -system.cpu.int_regfile_writes 40965330 # number of integer regfile writes -system.cpu.fp_regfile_reads 166532 # number of floating regfile reads -system.cpu.fp_regfile_writes 167403 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads -system.cpu.misc_regfile_writes 949674 # number of misc regfile writes +system.cpu.rob.rob_reads 142888950 # The number of ROB reads +system.cpu.rob.rob_writes 130907900 # The number of ROB writes +system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53089851 # Number of Instructions Simulated +system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated +system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads +system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74514493 # number of integer regfile reads +system.cpu.int_regfile_writes 40703979 # number of integer regfile writes +system.cpu.fp_regfile_reads 166152 # number of floating regfile reads +system.cpu.fp_regfile_writes 167434 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads +system.cpu.misc_regfile_writes 949957 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -596,237 +611,237 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004588 # number of replacements -system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use -system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits -system.cpu.icache.overall_hits::total 7985770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses -system.cpu.icache.overall_misses::total 1065446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # 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number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks -system.cpu.dcache.writebacks::total 834955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834483 # number of writebacks +system.cpu.dcache.writebacks::total 834483 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718769 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718769 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643008 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643008 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5385 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5385 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299852 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299852 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17992 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17992 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1385299 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1385299 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1385299 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1385299 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24777383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24777383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8529644820 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8529644820 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212567500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212567500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 74000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 74000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307028320 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33307028320 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33307028320 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33307028320 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904080500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904080500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1233731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -865,29 +880,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192344 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 192407 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 6921c92e4..aac888352 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:40:16 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 21:03:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582494330500 because m5_exit instruction encountered +Exiting @ tick 2572328372500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6605c6d1b..68d9a148e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582494 # Number of seconds simulated -sim_ticks 2582494330500 # Number of ticks simulated -final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.572328 # Number of seconds simulated +sim_ticks 2572328372500 # Number of ticks simulated +final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80373 # Simulator instruction rate (inst/s) -host_op_rate 103823 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3357432165 # Simulator tick rate (ticks/s) -host_mem_usage 383300 # Number of bytes of host memory used -host_seconds 769.19 # Real time elapsed on the host -sim_insts 61822124 # Number of instructions simulated -sim_ops 79859495 # Number of ops (including micro ops) simulated +host_inst_rate 81734 # Simulator instruction rate (inst/s) +host_op_rate 105574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3400147622 # Simulator tick rate (ticks/s) +host_mem_usage 384052 # Number of bytes of host memory used +host_seconds 756.53 # Real time elapsed on the host +sim_insts 61834256 # Number of instructions simulated +sim_ops 79870174 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,249 +20,249 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131499364 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10236688 # Number of bytes written to this memory -system.physmem.num_reads 15129208 # Number of read requests responded to by this memory -system.physmem.num_writes 869902 # Number of write requests responded to by this memory +system.physmem.bytes_read 131402148 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10205776 # Number of bytes written to this memory +system.physmem.num_reads 15127689 # Number of read requests responded to by this memory +system.physmem.num_writes 869419 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 132156 # number of replacements -system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use -system.l2c.total_refs 1820044 # Total number of references to valid blocks. -system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. +system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 130931 # number of replacements +system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use +system.l2c.total_refs 1850900 # Total number of references to valid blocks. +system.l2c.sampled_refs 160584 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.526055 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15356.692298 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 22.670587 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.636552 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3410.170856 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1587.790766 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 18.616033 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 3.576285 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2636.430831 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4539.259596 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.234325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000346 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.052035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.024228 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000284 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000055 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.040229 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.069264 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420789 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 89183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 17213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 526448 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 212618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 73946 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 477126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 150598 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 599046 # number of Writeback hits -system.l2c.Writeback_hits::total 599046 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 443 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 38925 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 89183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 17213 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 526448 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 73946 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 477126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 189523 # number of demand (read+write) hits -system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 89183 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 17213 # number of overall hits -system.l2c.overall_hits::cpu0.inst 526448 # number of overall hits -system.l2c.overall_hits::cpu0.data 271221 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 73946 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3915 # number of overall hits -system.l2c.overall_hits::cpu1.inst 477126 # number of overall hits -system.l2c.overall_hits::cpu1.data 189523 # number of overall hits -system.l2c.overall_hits::total 1648575 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10849 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 78 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7504 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 13059 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3816 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 849 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 97885 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 106823 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 78 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7504 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 63453 # number of demand (read+write) misses -system.l2c.demand_misses::total 188799 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 70 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses -system.l2c.overall_misses::cpu0.data 106823 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 78 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7504 # number of overall misses -system.l2c.overall_misses::cpu1.data 63453 # number of overall misses -system.l2c.overall_misses::total 188799 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3650500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 521000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 567333500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 466408000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 4067500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 625000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 392575500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 681928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2117109000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 27539500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 32790500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 60330000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1772000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5901500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7673500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5139681999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2639420000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7779101999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 3650500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 521000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 567333500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5606089999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 4067500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 625000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 392575500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3321348000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9896210999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 3650500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3927 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 484630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 163657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 599046 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 8343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4816 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1024 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 891 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 156488 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 89319 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 89253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 17223 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 537297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 378044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 74024 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3927 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 484630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 252976 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 89253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 17223 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 537297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 378044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 74024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3927 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 484630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 252976 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000581 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.020192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.040342 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.003056 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015484 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.079795 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.881098 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792359 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.829102 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.502806 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.625511 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564202 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000581 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.020192 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282568 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.003056 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015484 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.250826 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000581 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.020192 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282568 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.003056 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015484 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.250826 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52100 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # 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number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 162000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 377008500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3020427499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 356843500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3743640500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7503369999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468870500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -452,27 +455,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42410626 # DTB read hits -system.cpu0.dtb.read_misses 55840 # DTB read misses -system.cpu0.dtb.write_hits 6900244 # DTB write hits -system.cpu0.dtb.write_misses 11203 # DTB write misses +system.cpu0.dtb.read_hits 7800657 # DTB read hits +system.cpu0.dtb.read_misses 37871 # DTB read misses +system.cpu0.dtb.write_hits 4594363 # DTB write hits +system.cpu0.dtb.write_misses 6405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42466466 # DTB read accesses -system.cpu0.dtb.write_accesses 6911447 # DTB write accesses +system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7838528 # DTB read accesses +system.cpu0.dtb.write_accesses 4600768 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49310870 # DTB hits -system.cpu0.dtb.misses 67043 # DTB misses -system.cpu0.dtb.accesses 49377913 # DTB accesses -system.cpu0.itb.inst_hits 6428492 # ITB inst hits -system.cpu0.itb.inst_misses 17283 # ITB inst misses +system.cpu0.dtb.hits 12395020 # DTB hits +system.cpu0.dtb.misses 44276 # DTB misses +system.cpu0.dtb.accesses 12439296 # DTB accesses +system.cpu0.itb.inst_hits 4047811 # ITB inst hits +system.cpu0.itb.inst_misses 4513 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -481,534 +484,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses -system.cpu0.itb.hits 6428492 # DTB hits -system.cpu0.itb.misses 17283 # DTB misses -system.cpu0.itb.accesses 6445775 # DTB accesses -system.cpu0.numCycles 352483912 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses +system.cpu0.itb.hits 4047811 # DTB hits +system.cpu0.itb.misses 4513 # DTB misses +system.cpu0.itb.accesses 4052324 # DTB accesses +system.cpu0.numCycles 58217040 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued -system.cpu0.iq.rate 0.227743 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued +system.cpu0.iq.rate 0.564768 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 506933 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 642785 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 205792 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 324258 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 173953 # number of nop insts executed -system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6431362 # Number of branches executed -system.cpu0.iew.exec_stores 7171156 # Number of stores executed -system.cpu0.iew.exec_rate 0.225691 # Inst execution rate -system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24791862 # num instructions producing a value -system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value +system.cpu0.iew.exec_nop 54681 # number of nop insts executed +system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4282280 # Number of branches executed +system.cpu0.iew.exec_stores 4857867 # Number of stores executed +system.cpu0.iew.exec_rate 0.557341 # Inst execution rate +system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 16076835 # num instructions producing a value +system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 31935522 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 41923639 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31935522 # Number of instructions committed -system.cpu0.commit.committedOps 41923639 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 20629504 # Number of instructions committed +system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15936098 # Number of memory references committed -system.cpu0.commit.loads 9243307 # Number of loads committed -system.cpu0.commit.membars 288653 # Number of memory barriers committed -system.cpu0.commit.branches 5542289 # Number of branches committed -system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620184 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached +system.cpu0.commit.refs 10038315 # Number of memory references committed +system.cpu0.commit.loads 5430093 # Number of loads committed +system.cpu0.commit.membars 201113 # Number of memory barriers committed +system.cpu0.commit.branches 3777887 # Number of branches committed +system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions. +system.cpu0.commit.function_calls 441072 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157931724 # The number of ROB reads -system.cpu0.rob.rob_writes 106372981 # The number of ROB writes -system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31809695 # Number of Instructions Simulated -system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated -system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads -system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads -system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes -system.cpu0.icache.replacements 538787 # number of replacements -system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use -system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.612990 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5838964 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5838964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5838964 # number of overall hits -system.cpu0.icache.overall_hits::total 5838964 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 583385 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 583385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 583385 # number of overall misses -system.cpu0.icache.overall_misses::total 583385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8740145988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8740145988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6422349 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6422349 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090837 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090837 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090837 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked +system.cpu0.rob.rob_reads 68594693 # The number of ROB reads +system.cpu0.rob.rob_writes 67665332 # The number of ROB writes +system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 20604950 # Number of Instructions Simulated +system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated +system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads +system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads +system.cpu0.fp_regfile_writes 420 # number of floating regfile writes +system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes +system.cpu0.icache.replacements 364224 # number of replacements +system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use +system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits +system.cpu0.icache.overall_hits::total 3649617 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses +system.cpu0.icache.overall_misses::total 395923 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7411.116751 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 29665 # number of writebacks -system.cpu0.icache.writebacks::total 29665 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44065 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44065 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44065 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44065 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539320 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 539320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539320 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 18468 # number of writebacks +system.cpu0.icache.writebacks::total 18468 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 364861 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 364861 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 364861 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 364861 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 364861 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 364861 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4524888490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4524888490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4524888490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4524888490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4524888490 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4524888490 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 372182 # number of replacements -system.cpu0.dcache.tagsinuse 487.992960 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 487.992960 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7966835 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4346487 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 221211 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 199868 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12313322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12313322 # number of overall hits -system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 463412 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1864293 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10042 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7686 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 76899520327 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 76899520327 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.054970 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.300171 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.043424 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 854 # 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number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 337108 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1466456 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1466456 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8650 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8650 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1803564 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1803564 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1803564 # number of overall misses +system.cpu0.dcache.overall_misses::total 1803564 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4776619000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4776619000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60194469903 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60194469903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98955000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98955000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83321000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 83321000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64971088903 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64971088903 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64971088903 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64971088903 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5345709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5345709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4177158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167459 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167459 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164050 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 164050 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9522867 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9522867 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9522867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9522867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063061 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351065 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051654 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189393 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 327766 # number of writebacks -system.cpu0.dcache.writebacks::total 327766 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1909869 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1909869 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 417836 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 417836 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 64109000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks +system.cpu0.dcache.writebacks::total 213312 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028413 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9047.202797 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10576968 # DTB read hits -system.cpu1.dtb.read_misses 41875 # DTB read misses -system.cpu1.dtb.write_hits 5530754 # DTB write hits -system.cpu1.dtb.write_misses 15302 # DTB write misses +system.cpu1.dtb.read_hits 44928224 # DTB read hits +system.cpu1.dtb.read_misses 73602 # DTB read misses +system.cpu1.dtb.write_hits 7780505 # DTB write hits +system.cpu1.dtb.write_misses 20150 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10618843 # DTB read accesses -system.cpu1.dtb.write_accesses 5546056 # DTB write accesses +system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45001826 # DTB read accesses +system.cpu1.dtb.write_accesses 7800655 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16107722 # DTB hits -system.cpu1.dtb.misses 57177 # DTB misses -system.cpu1.dtb.accesses 16164899 # DTB accesses -system.cpu1.itb.inst_hits 8214514 # ITB inst hits -system.cpu1.itb.inst_misses 3039 # ITB inst misses +system.cpu1.dtb.hits 52708729 # DTB hits +system.cpu1.dtb.misses 93752 # DTB misses +system.cpu1.dtb.accesses 52802481 # DTB accesses +system.cpu1.itb.inst_hits 10224529 # ITB inst hits +system.cpu1.itb.inst_misses 7346 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1017,504 +1020,507 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses -system.cpu1.itb.hits 8214514 # DTB hits -system.cpu1.itb.misses 3039 # DTB misses -system.cpu1.itb.accesses 8217553 # DTB accesses -system.cpu1.numCycles 69079827 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses +system.cpu1.itb.hits 10224529 # DTB hits +system.cpu1.itb.misses 7346 # DTB misses +system.cpu1.itb.accesses 10231875 # DTB accesses +system.cpu1.numCycles 361675233 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits +system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued -system.cpu1.iq.rate 0.728958 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued +system.cpu1.iq.rate 0.267369 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50586 # number of nop insts executed -system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5808702 # Number of branches executed -system.cpu1.iew.exec_stores 5821790 # Number of stores executed -system.cpu1.iew.exec_rate 0.688543 # Inst execution rate -system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24255669 # num instructions producing a value -system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value +system.cpu1.iew.exec_nop 169844 # number of nop insts executed +system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7814764 # Number of branches executed +system.cpu1.iew.exec_stores 8083565 # Number of stores executed +system.cpu1.iew.exec_rate 0.259338 # Inst execution rate +system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 32803499 # num instructions producing a value +system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 30036983 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 38086237 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30036983 # Number of instructions committed -system.cpu1.commit.committedOps 38086237 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41355133 # Number of instructions committed +system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12651383 # Number of memory references committed -system.cpu1.commit.loads 7112761 # Number of loads committed -system.cpu1.commit.membars 148646 # Number of memory barriers committed -system.cpu1.commit.branches 4805168 # Number of branches committed -system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433251 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached +system.cpu1.commit.refs 18556919 # Number of memory references committed +system.cpu1.commit.loads 10922280 # Number of loads committed +system.cpu1.commit.membars 235767 # Number of memory barriers committed +system.cpu1.commit.branches 6572492 # Number of branches committed +system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions. +system.cpu1.commit.function_calls 612387 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102142645 # The number of ROB reads -system.cpu1.rob.rob_writes 116493771 # The number of ROB writes -system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30012429 # Number of Instructions Simulated -system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated -system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads -system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes -system.cpu1.icache.replacements 485586 # number of replacements -system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use -system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.788681 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7684975 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7684975 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7684975 # number of overall hits -system.cpu1.icache.overall_hits::total 7684975 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527035 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527035 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527035 # number of overall misses -system.cpu1.icache.overall_misses::total 527035 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7752735997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7752735997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8212010 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8212010 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.064179 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.064179 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.064179 # 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Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated +system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads +system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes +system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads +system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes +system.cpu1.icache.replacements 696666 # number of replacements +system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use +system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 697178 # 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average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 231 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6290.021645 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 18538 # number of writebacks -system.cpu1.icache.writebacks::total 18538 # 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number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2517500 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272200 # number of replacements -system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.953212 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 7085363 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3139669 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75360 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72622 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10225032 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10225032 # number of overall hits -system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 323287 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1273508 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12669 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11046 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1596795 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1596795 # number of overall misses -system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87512500 # 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number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9771721 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4750886 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4750886 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123631 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 123631 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116540 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 116540 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14522607 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14522607 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14522607 # number of overall hits +system.cpu1.dcache.overall_hits::total 14522607 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 451897 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 451897 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1700738 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1700738 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14109 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14109 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10120 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10120 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2152635 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2152635 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2152635 # number of overall misses +system.cpu1.dcache.overall_misses::total 2152635 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6794357500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6794357500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56737247402 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 56737247402 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 169367000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 169367000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85782500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 85782500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 63531604902 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 63531604902 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 63531604902 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 63531604902 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10223618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10223618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6451624 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6451624 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137740 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 137740 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126660 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 126660 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16675242 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16675242 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16675242 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16675242 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044201 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263614 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102432 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079899 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129092 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129092 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15035.190541 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33360.369088 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12004.181728 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8476.531621 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 14045059 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5012000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3121 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 132 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4500.179109 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37969.696970 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks -system.cpu1.dcache.writebacks::total 223077 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1291206 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1291206 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 305589 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 305589 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025557 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132468 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.132022 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8505.231112 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4915.535035 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks +system.cpu1.dcache.writebacks::total 337861 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -1533,16 +1539,16 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 1c96dc767..a1c7f49b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:39:00 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 21:01:11 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503580880500 because m5_exit instruction encountered +Exiting @ tick 2503289265500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 1df010cb5..d8269d3fd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503581 # Number of seconds simulated -sim_ticks 2503580880500 # Number of ticks simulated -final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503289 # Number of seconds simulated +sim_ticks 2503289265500 # Number of ticks simulated +final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80550 # Simulator instruction rate (inst/s) -host_op_rate 104045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3392180683 # Simulator tick rate (ticks/s) -host_mem_usage 382816 # Number of bytes of host memory used -host_seconds 738.04 # Real time elapsed on the host -sim_insts 59449329 # Number of instructions simulated -sim_ops 76789886 # Number of ops (including micro ops) simulated +host_inst_rate 81468 # Simulator instruction rate (inst/s) +host_op_rate 105230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3430236303 # Simulator tick rate (ticks/s) +host_mem_usage 383240 # Number of bytes of host memory used +host_seconds 729.77 # Real time elapsed on the host +sim_insts 59452703 # Number of instructions simulated +sim_ops 76793713 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130729872 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1100224 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585224 # Number of bytes written to this memory -system.physmem.num_reads 15117120 # Number of read requests responded to by this memory -system.physmem.num_writes 856661 # Number of write requests responded to by this memory +system.physmem.bytes_read 130753040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9587720 # Number of bytes written to this memory +system.physmem.num_reads 15117482 # Number of read requests responded to by this memory +system.physmem.num_writes 856700 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52217155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 439460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3828606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56045761 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119505 # number of replacements -system.l2c.tagsinuse 25834.929390 # Cycle average of tags in use -system.l2c.total_refs 1795685 # Total number of references to valid blocks. -system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. +system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 446670 # 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av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102643 # number of writebacks -system.l2c.writebacks::total 102643 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 102682 # number of writebacks +system.l2c.writebacks::total 102682 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.itb.walker 1 # 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number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 462000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 696908500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765299500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1468682000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6012000 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131761112000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131766619000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -275,27 +278,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52219999 # DTB read hits -system.cpu.dtb.read_misses 90279 # DTB read misses -system.cpu.dtb.write_hits 11976179 # DTB write hits -system.cpu.dtb.write_misses 25577 # DTB write misses +system.cpu.dtb.read_hits 51991464 # DTB read hits +system.cpu.dtb.read_misses 102104 # DTB read misses +system.cpu.dtb.write_hits 11910179 # DTB write hits +system.cpu.dtb.write_misses 24558 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4346 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 6089 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 654 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4433 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2193 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52310278 # DTB read accesses -system.cpu.dtb.write_accesses 12001756 # DTB write accesses +system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52093568 # DTB read accesses +system.cpu.dtb.write_accesses 11934737 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64196178 # DTB hits -system.cpu.dtb.misses 115856 # DTB misses -system.cpu.dtb.accesses 64312034 # DTB accesses -system.cpu.itb.inst_hits 14123674 # ITB inst hits -system.cpu.itb.inst_misses 9885 # ITB inst misses +system.cpu.dtb.hits 63901643 # DTB hits +system.cpu.dtb.misses 126662 # DTB misses +system.cpu.dtb.accesses 64028305 # DTB accesses +system.cpu.itb.inst_hits 13706914 # ITB inst hits +system.cpu.itb.inst_misses 11634 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -304,504 +307,504 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2599 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2596 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 7902 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14133559 # ITB inst accesses -system.cpu.itb.hits 14123674 # DTB hits -system.cpu.itb.misses 9885 # DTB misses -system.cpu.itb.accesses 14133559 # DTB accesses -system.cpu.numCycles 415943429 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13718548 # ITB inst accesses +system.cpu.itb.hits 13706914 # DTB hits +system.cpu.itb.misses 11634 # DTB misses +system.cpu.itb.accesses 13718548 # DTB accesses +system.cpu.numCycles 414369636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16201364 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12549421 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1109380 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13917593 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10243002 # Number of BTB hits +system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1423675 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 227604 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32912368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104836271 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16201364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11666677 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24487466 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7079059 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131458 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92859775 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145565 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217503 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14115008 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1041610 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4861 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155569254 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838536 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184070 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131107551 84.28% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1739904 1.12% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2616632 1.68% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3657999 2.35% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2164577 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1434404 0.92% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2630326 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 851935 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9365926 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155569254 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038951 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.252045 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35134284 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92713878 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21991115 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092987 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4636990 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2313958 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177730 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122065816 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 573184 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4636990 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37283411 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36813700 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49928995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20929371 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5976787 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113968448 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 915244 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3983499 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42655 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118524115 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 524000264 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523903687 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 96577 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492548 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 41031566 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1204512 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098851 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12310506 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21988549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14164932 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1902928 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2266136 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102902284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1875395 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126904684 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 253228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27017748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 72978464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 375688 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155569254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505343 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108923700 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15131938 9.73% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7543329 4.85% 84.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6524442 4.19% 88.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12759852 8.20% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2730334 1.76% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1400610 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422368 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132681 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155569254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45526 0.51% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8417505 94.61% 95.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 433723 4.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60099266 47.36% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96421 0.08% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2248 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53941927 42.51% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12658279 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126904684 # Type of FU issued -system.cpu.iq.rate 0.305101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896761 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070106 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418619840 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131813494 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87332577 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23940 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13540 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10418 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135682181 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12734 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614286 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued +system.cpu.iq.rate 0.304001 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6307786 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32675 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2385852 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061916 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151020 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4636990 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28345844 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 418518 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104992332 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 473238 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21988549 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14164932 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 597023 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 929866 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 214653 # number of nop insts executed -system.cpu.iew.exec_refs 65406640 # number of memory reference insts executed -system.cpu.iew.exec_branches 11708135 # Number of branches executed -system.cpu.iew.exec_stores 12489378 # Number of stores executed -system.cpu.iew.exec_rate 0.296843 # Inst execution rate -system.cpu.iew.wb_sent 121811310 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87342995 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47060292 # num instructions producing a value -system.cpu.iew.wb_consumers 86666260 # num instructions consuming a value +system.cpu.iew.exec_nop 216034 # number of nop insts executed +system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed +system.cpu.iew.exec_branches 11571925 # Number of branches executed +system.cpu.iew.exec_stores 12419635 # Number of stores executed +system.cpu.iew.exec_rate 0.296062 # Inst execution rate +system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46911516 # num instructions producing a value +system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151014616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509489 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459114 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122165210 80.90% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14833013 9.82% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4110348 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2186082 1.45% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788351 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1361296 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1264343 0.84% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665414 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2640559 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59599710 # Number of instructions committed -system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59603084 # Number of instructions committed +system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459843 # Number of memory references committed -system.cpu.commit.loads 15680763 # Number of loads committed -system.cpu.commit.membars 413065 # Number of memory barriers committed -system.cpu.commit.branches 9891047 # Number of branches committed +system.cpu.commit.refs 27461448 # Number of memory references committed +system.cpu.commit.loads 15681836 # Number of loads committed +system.cpu.commit.membars 413071 # Number of memory barriers committed +system.cpu.commit.branches 9891470 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68493330 # Number of committed integer instructions. -system.cpu.commit.function_calls 995601 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2640559 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. +system.cpu.commit.function_calls 995631 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251393815 # The number of ROB reads -system.cpu.rob.rob_writes 214319630 # The number of ROB writes -system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59449329 # Number of Instructions Simulated -system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated -system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads -system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559798057 # number of integer regfile reads -system.cpu.int_regfile_writes 89741069 # number of integer regfile writes -system.cpu.fp_regfile_reads 8257 # number of floating regfile reads -system.cpu.fp_regfile_writes 2814 # number of floating regfile writes -system.cpu.misc_regfile_reads 137366935 # number of misc regfile reads -system.cpu.misc_regfile_writes 912292 # number of misc regfile writes -system.cpu.icache.replacements 991177 # number of replacements -system.cpu.icache.tagsinuse 511.615293 # Cycle average of tags in use -system.cpu.icache.total_refs 13035657 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked +system.cpu.rob.rob_reads 248361579 # The number of ROB reads +system.cpu.rob.rob_writes 211126300 # The number of ROB writes +system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59452703 # Number of Instructions Simulated +system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated +system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556236612 # number of integer regfile reads +system.cpu.int_regfile_writes 88987615 # number of integer regfile writes +system.cpu.fp_regfile_reads 8813 # number of floating regfile reads +system.cpu.fp_regfile_writes 2942 # number of floating regfile writes +system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads +system.cpu.misc_regfile_writes 912350 # number of misc regfile writes +system.cpu.icache.replacements 1015901 # number of replacements +system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use +system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits +system.cpu.icache.overall_hits::total 12592690 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses +system.cpu.icache.overall_misses::total 1106667 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 57255 # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 58562 # number of writebacks +system.cpu.icache.writebacks::total 58562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643728 # number of replacements -system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22270301 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645034 # number of replacements +system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use +system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits -system.cpu.dcache.overall_hits::total 21681508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses -system.cpu.dcache.overall_misses::total 3688917 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 14161876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14161876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7265482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7265482 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 286317 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 286317 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285516 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285516 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21427358 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21427358 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21427358 # number of overall hits +system.cpu.dcache.overall_hits::total 21427358 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 733645 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 733645 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966203 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966203 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13700 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13700 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699848 # number of overall misses +system.cpu.dcache.overall_misses::total 3699848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121460107261 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121460107261 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25127206 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25127206 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25127206 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25127206 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045664 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.147245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15060.913657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37222.922120 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16284.562044 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16049941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7647500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2833 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5665.351571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27910.583942 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks -system.cpu.dcache.writebacks::total 572893 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 574496 # number of writebacks +system.cpu.dcache.writebacks::total 574496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3063259 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3063259 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387019 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387019 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249570 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249570 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636589 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636589 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.242895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35766.179593 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13401.288597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -820,14 +823,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 7b718bc11..e4f17be50 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:31:16 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:53:18 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5163317092500 because m5_exit instruction encountered +Exiting @ tick 5155288336500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 477cac0b5..1c3be5421 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,151 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.163317 # Number of seconds simulated -sim_ticks 5163317092500 # Number of ticks simulated -final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.155288 # Number of seconds simulated +sim_ticks 5155288336500 # Number of ticks simulated +final_tick 5155288336500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184798 # Simulator instruction rate (inst/s) -host_op_rate 364169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2236864416 # Simulator tick rate (ticks/s) -host_mem_usage 361200 # Number of bytes of host memory used -host_seconds 2308.28 # Real time elapsed on the host -sim_insts 426565585 # Number of instructions simulated -sim_ops 840604148 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15861056 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12134976 # Number of bytes written to this memory -system.physmem.num_reads 247829 # Number of read requests responded to by this memory -system.physmem.num_writes 189609 # Number of write requests responded to by this memory +host_inst_rate 187724 # Simulator instruction rate (inst/s) +host_op_rate 369929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2268413480 # Simulator tick rate (ticks/s) +host_mem_usage 362380 # Number of bytes of host memory used +host_seconds 2272.64 # Real time elapsed on the host +sim_insts 426629675 # Number of instructions simulated +sim_ops 840716593 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15943680 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1259264 # Number of instructions bytes read from this memory +system.physmem.bytes_written 12043648 # Number of bytes written to this memory +system.physmem.num_reads 249120 # Number of read requests responded to by this memory +system.physmem.num_writes 188182 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3071873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 238879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2350229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5422102 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 168510 # number of replacements -system.l2c.tagsinuse 37865.450237 # Cycle average of tags in use -system.l2c.total_refs 3777661 # Total number of references to valid blocks. -system.l2c.sampled_refs 200841 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.809212 # Average number of references to valid blocks. +system.physmem.bw_read 3092684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 244266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2336174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 5428858 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 167456 # number of replacements +system.l2c.tagsinuse 37822.927931 # Cycle average of tags in use +system.l2c.total_refs 3846980 # Total number of references to valid blocks. +system.l2c.sampled_refs 202165 # Sample count of references to valid blocks. +system.l2c.avg_refs 19.028912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 26765.864627 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.948564 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.042262 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2364.419048 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8723.175736 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.408415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 26706.608582 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.179185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.034739 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2430.963092 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8674.142332 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.407511 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000171 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.036078 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.133105 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.577781 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 134155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 7302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001370 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1325429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1603120 # number of Writeback hits -system.l2c.Writeback_hits::total 1603120 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.037094 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.132357 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.577132 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 117941 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9215 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1064505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1335031 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2526692 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1602581 # number of Writeback hits +system.l2c.Writeback_hits::total 1602581 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 150704 # 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miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.484055 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000611 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001368 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.018883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.112085 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000611 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001368 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.018883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.112085 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52170.731707 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52100 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52257.251077 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1084182 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1380274 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2591717 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1602581 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1602581 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3009 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3009 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292947 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292947 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 118039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9222 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1084182 # 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miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.483002 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000830 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000759 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.018149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.111603 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000830 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000759 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.018149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.111603 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52204.081633 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52255.653809 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52565.866543 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 14585.783402 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.141080 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -154,8 +154,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 142942 # number of writebacks -system.l2c.writebacks::total 142942 # number of writebacks +system.l2c.writebacks::writebacks 141515 # number of writebacks +system.l2c.writebacks::total 141515 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -165,157 +165,157 @@ system.l2c.demand_mshr_hits::total 2 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59975987000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230144500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1230144500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206131500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61206131500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032778 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.892988 # 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average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47580 # number of replacements -system.iocache.tagsinuse 0.183883 # Cycle average of tags in use +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.159321 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47596 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.183883 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.011493 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.011493 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 915 # number of ReadReq misses +system.iocache.warmup_cycle 4996368196000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.159321 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009958 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009958 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # 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number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6370894160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6370894160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6485090092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6485090092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6485090092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6485090092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125219.597814 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136250.303082 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125352.285401 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136363.316781 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 68835510 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11261 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6112.735103 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66972982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66972982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3935855798 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3935855798 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4002828780 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4002828780 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66802976 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66802976 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3941136864 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3941136864 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4007939840 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4007939840 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73194.515847 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84243.488827 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73329.282108 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84356.525342 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -329,395 +329,395 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 462460674 # number of cpu cycles simulated +system.cpu.numCycles 461736319 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91001984 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91001984 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1246670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89740974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83587498 # Number of BTB hits +system.cpu.BPredUnit.lookups 90084371 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90084371 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1179546 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84316538 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81732802 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28956413 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449639850 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91001984 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83587498 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171222727 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5870168 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 127753 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 101915873 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 38952 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9672092 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 512695 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3312 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 306883426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.884320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.377751 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29640549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 447158079 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90084371 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81732802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169862026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5320379 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 145881 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102119338 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 39504 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9392758 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 524186 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5360 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 305948772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.876024 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.383488 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136151197 44.37% 44.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1833476 0.60% 44.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72801112 23.72% 68.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1413943 0.46% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1812929 0.59% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3984448 1.30% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1563806 0.51% 71.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1664583 0.54% 72.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85657932 27.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136524607 44.62% 44.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1781462 0.58% 45.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72780882 23.79% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 993009 0.32% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1639605 0.54% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3682017 1.20% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1148071 0.38% 71.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1456036 0.48% 71.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85943083 28.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 306883426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.196778 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.972277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34101035 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98103338 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165554285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4539875 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4584893 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881320225 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 609 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4584893 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38485909 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67729275 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11421097 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165177226 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19485026 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 876989303 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10814 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12483638 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3869558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 878639289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1719877661 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1719877141 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843209199 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35430083 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491480 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 496551 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46051608 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19446241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10506071 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1193626 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 915732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869497074 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1725725 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866404799 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123854 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29753009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42786279 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206033 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 306883426 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.823238 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.403588 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 305948772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195099 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.968427 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34742596 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98230101 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164036692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4836131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4103252 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876669813 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 827 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4103252 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39030266 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68185463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10584671 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 164072016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19973104 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872862955 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10194 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12946310 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3889382 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 874188806 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1710305089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1710304369 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 720 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843320455 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30868344 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 477917 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 485258 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46626951 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18944692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10483519 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1301190 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1038101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865973387 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1727922 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864611178 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114248 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26054957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37073399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 305948772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.826000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.403043 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 100067522 32.61% 32.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25349299 8.26% 40.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 13936726 4.54% 45.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9650933 3.14% 48.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79503599 25.91% 74.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4853866 1.58% 76.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72832557 23.73% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 561211 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127713 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99370843 32.48% 32.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25451279 8.32% 40.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14262788 4.66% 45.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9410835 3.08% 48.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79123808 25.86% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4863158 1.59% 75.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72802263 23.80% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533166 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130632 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 306883426 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 305948772 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 188296 8.84% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1773429 83.29% 92.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 167520 7.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 169581 8.02% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1777046 84.08% 92.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 166802 7.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304337 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831186392 95.94% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25424398 2.93% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9489672 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 304260 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829639344 95.96% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25194661 2.91% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472913 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866404799 # Type of FU issued -system.cpu.iq.rate 1.873467 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2129245 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2042097119 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 900986111 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855761606 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 229 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868229599 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1634850 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864611178 # Type of FU issued +system.cpu.iq.rate 1.872521 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2113429 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2037542293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893767044 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 854207329 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 316 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866420202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1589122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4122229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17231 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11383 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2082513 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3614563 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21772 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12029 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2051269 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821289 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4333 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821662 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2623 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4584893 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45441721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6142722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871222799 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 285751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19446241 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10506071 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 891740 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5368443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12385 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11383 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 896223 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525625 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1421848 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864338156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24982156 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2066642 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4103252 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45514835 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6136303 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867701309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 314417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18944692 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10483519 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 889203 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5413874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12817 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12029 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 702671 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628126 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1330797 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862708188 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24767979 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1902989 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34234409 # number of memory reference insts executed -system.cpu.iew.exec_branches 86668621 # Number of branches executed -system.cpu.iew.exec_stores 9252253 # Number of stores executed -system.cpu.iew.exec_rate 1.868998 # Inst execution rate -system.cpu.iew.wb_sent 863811947 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855761668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 670084242 # num instructions producing a value -system.cpu.iew.wb_consumers 1169301773 # num instructions consuming a value +system.cpu.iew.exec_refs 33996128 # number of memory reference insts executed +system.cpu.iew.exec_branches 86527576 # Number of branches executed +system.cpu.iew.exec_stores 9228149 # Number of stores executed +system.cpu.iew.exec_rate 1.868400 # Inst execution rate +system.cpu.iew.wb_sent 862244747 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 854207409 # cumulative count of insts written-back +system.cpu.iew.wb_producers 668533054 # num instructions producing a value +system.cpu.iew.wb_consumers 1167360089 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back +system.cpu.iew.wb_rate 1.849990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572688 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426565585 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840604148 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 302314482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.780562 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862970 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426629675 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840716593 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26871696 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1520650 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1183899 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 301861557 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.785107 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863294 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547491 40.21% 40.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14447999 4.78% 44.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4300765 1.42% 46.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76650469 25.35% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3947228 1.31% 73.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1803648 0.60% 73.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1077125 0.36% 74.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984746 23.81% 97.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6555011 2.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121093745 40.12% 40.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14426665 4.78% 44.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4304237 1.43% 46.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76676312 25.40% 71.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3920373 1.30% 73.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1782325 0.59% 73.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109784 0.37% 73.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71984231 23.85% 97.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6563885 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426565585 # Number of instructions committed -system.cpu.commit.committedOps 840604148 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 301861557 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426629675 # Number of instructions committed +system.cpu.commit.committedOps 840716593 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23747567 # Number of memory references committed -system.cpu.commit.loads 15324009 # Number of loads committed -system.cpu.commit.membars 781567 # Number of memory barriers committed -system.cpu.commit.branches 85515141 # Number of branches committed +system.cpu.commit.refs 23762376 # Number of memory references committed +system.cpu.commit.loads 15330126 # Number of loads committed +system.cpu.commit.membars 781563 # Number of memory barriers committed +system.cpu.commit.branches 85529575 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768433298 # Number of committed integer instructions. +system.cpu.commit.int_insts 768542107 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6555011 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6563885 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166791668 # The number of ROB reads -system.cpu.rob.rob_writes 1746826364 # The number of ROB writes -system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426565585 # Number of Instructions Simulated -system.cpu.committedOps 840604148 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426565585 # Number of Instructions Simulated -system.cpu.cpi 1.084149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.084149 # CPI: Total CPI of All Threads -system.cpu.ipc 0.922382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.922382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads -system.cpu.int_regfile_writes 857070459 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.misc_regfile_reads 281985005 # number of misc regfile reads -system.cpu.misc_regfile_writes 409504 # number of misc regfile writes -system.cpu.icache.replacements 1020153 # number of replacements -system.cpu.icache.tagsinuse 509.928344 # Cycle average of tags in use -system.cpu.icache.total_refs 8587640 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.928344 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995954 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995954 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8587640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8587640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8587640 # number of overall hits -system.cpu.icache.overall_hits::total 8587640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1084449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1084449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1084449 # number of overall misses -system.cpu.icache.overall_misses::total 1084449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16282601991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16282601991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16282601991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16282601991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16282601991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16282601991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9672089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9672089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9672089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.112121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.112121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15014.631385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1162802870 # The number of ROB reads +system.cpu.rob.rob_writes 1739294618 # The number of ROB writes +system.cpu.timesIdled 2882631 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155787547 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9848837790 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426629675 # Number of Instructions Simulated +system.cpu.committedOps 840716593 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426629675 # Number of Instructions Simulated +system.cpu.cpi 1.082288 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.082288 # CPI: Total CPI of All Threads +system.cpu.ipc 0.923968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.923968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1404705112 # number of integer regfile reads +system.cpu.int_regfile_writes 855482985 # number of integer regfile writes +system.cpu.fp_regfile_reads 80 # number of floating regfile reads +system.cpu.misc_regfile_reads 281196998 # number of misc regfile reads +system.cpu.misc_regfile_writes 410876 # number of misc regfile writes +system.cpu.icache.replacements 1083725 # number of replacements +system.cpu.icache.tagsinuse 510.022776 # Cycle average of tags in use +system.cpu.icache.total_refs 8238065 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1084236 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.598037 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56617488000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.022776 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996138 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8238065 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8238065 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8238065 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8238065 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8238065 # number of overall hits +system.cpu.icache.overall_hits::total 8238065 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154689 # number of overall misses +system.cpu.icache.overall_misses::total 1154689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17243109487 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17243109487 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17243109487 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17243109487 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17243109487 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17243109487 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9392754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9392754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9392754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9392754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9392754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9392754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122934 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122934 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122934 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14933.120076 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2884989 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9616.630000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1551 # number of writebacks -system.cpu.icache.writebacks::total 1551 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1024341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1024341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1024341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1024341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1024341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1024341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12392610492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12392610492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12392610492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12392610492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12392610492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12392610492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12098.129912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1570 # number of writebacks +system.cpu.icache.writebacks::total 1570 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1085525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1085525 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1085525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1085525 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1085525 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1085525 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13103385489 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13103385489 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13103385489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13103385489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13103385489 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13103385489 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12071.012173 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 8553 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26637 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.010935 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375683 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375683 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26742 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11375 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.006905 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28918 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11386 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.539786 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5142961834000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006905 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375432 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375432 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28987 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28987 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26745 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9424 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9424 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9424 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 120935500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 120935500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 120935500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 120935500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 120935500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 120935500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36166 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28990 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28990 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28990 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28990 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12232 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12232 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12232 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12232 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12232 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12232 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 154656000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 154656000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 154656000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 154656000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 154656000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 154656000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41219 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36169 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36169 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.260576 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.260555 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.260555 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12832.714346 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.296756 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.296735 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.296735 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12643.557881 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -726,66 +726,66 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9424 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9424 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9424 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9424 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9424 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9424 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 92324000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 92324000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 92324000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 92324000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 92324000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 92324000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.260576 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1402 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1402 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12232 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12232 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12232 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12232 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12232 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12232 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 117502000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 117502000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 117502000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 117502000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 117502000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 117502000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.296756 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 140574 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 148049 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.858803 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866175 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866175 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 148058 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 148058 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 148058 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 141571 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 141571 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 141571 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1989434500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1989434500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1989434500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1989434500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1989434500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1989434500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 289629 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 289629 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 289629 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.488801 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.488801 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.488801 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 14052.556668 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 125889 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.942075 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 147310 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 125903 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.170028 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108639465000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942075 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808880 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808880 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 147324 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 147324 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 147324 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 147324 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 147324 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 147324 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 126858 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 126858 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 126858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 126858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 126858 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 126858 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1765137000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1765137000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1765137000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1765137000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1765137000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1765137000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 274182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 274182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 274182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 274182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 274182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 274182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.462678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.462678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.462678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13914.274228 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,124 +794,124 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 49457 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 49457 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 141571 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 141571 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 141571 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 141571 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 141571 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 141571 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1560743500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1560743500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1560743500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 38155 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 38155 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 126858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 126858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 126858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 126858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 126858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 126858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1381422000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1381422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1381422000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1662584 # number of replacements -system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use -system.cpu.dcache.total_refs 19274168 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995323 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11173849 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093995 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19267844 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19267844 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36160191000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10588613980 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10588613980 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46748804980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46748804980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46748804980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46748804980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13391673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13391673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8422897 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422897 # 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average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23292480 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3427 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.755179 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1550496 # number of writebacks -system.cpu.dcache.writebacks::total 1550496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018010 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1018010 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22803 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22803 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1040813 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1040813 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1040813 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1040813 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371571 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371571 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 297402 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 297402 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1668973 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1668973 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1668973 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1668973 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013626000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013626000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9484899492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9484899492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27498525492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27498525492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27498525492 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27498525492 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207760000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207760000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600268500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600268500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101123 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208380500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208380500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393791500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393791500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602172000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602172000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035124 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13145.140180 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31679.405772 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |