diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-20 15:09:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-20 15:09:43 -0700 |
| commit | 93c4527128591f9337b9700a0898b229dc49c61d (patch) | |
| tree | 95cc99d7f3d5a647f3ca0512d22d4baa1d27e00e /tests/long/fs/10.linux-boot | |
| parent | cd76e34056afab83697beef1d1ced94ee671a20d (diff) | |
| download | gem5-93c4527128591f9337b9700a0898b229dc49c61d.tar.xz | |
stats: update a few stats from long O3 runs
Very small changes to iew.predictedNotTakenIncorrect
and iew.branchMispredicts. Looks like similar updates
were committed on April 3 (changeset 235ff1c046df), but
only for the quick tests.
Diffstat (limited to 'tests/long/fs/10.linux-boot')
14 files changed, 297 insertions, 155 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 23b34b238..172f27cee 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -189,7 +190,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] -type=BranchPredictor +type=BiModeBP BTBEntries=2048 BTBTagSize=18 RASSize=16 @@ -199,11 +200,7 @@ eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 numThreads=1 -predType=bi-mode [system.cpu0.dcache] type=BaseCache @@ -211,6 +208,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -245,6 +243,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] @@ -262,7 +261,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -552,8 +550,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -620,6 +619,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] @@ -637,7 +637,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -662,6 +661,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -683,19 +683,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -712,13 +720,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu0.l2cache.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -816,7 +827,7 @@ dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] -type=BranchPredictor +type=BiModeBP BTBEntries=2048 BTBTagSize=18 RASSize=16 @@ -826,11 +837,7 @@ eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 numThreads=1 -predType=bi-mode [system.cpu1.dcache] type=BaseCache @@ -838,6 +845,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -872,6 +880,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] @@ -889,7 +898,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -1179,8 +1187,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -1247,6 +1256,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] @@ -1264,7 +1274,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -1289,6 +1298,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -1310,19 +1320,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -1339,13 +1357,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu1.l2cache.cpu_side -slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -1376,9 +1397,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -1389,6 +1412,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1424,6 +1448,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -1458,13 +1483,16 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1512,7 +1540,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -1816,7 +1844,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -2003,7 +2030,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -2185,7 +2212,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory @@ -2223,11 +2250,14 @@ port=3456 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false -width=8 +width=32 master=system.l2c.cpu_side slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 061d104e8..d6745503c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -27,11 +27,10 @@ warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: instruction 'mcr bpiall' unimplemented warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: allocating bonus target for snoop warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index deb0b678e..4506577d0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,17 +1,18 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 31 2014 10:01:44 -gem5 started Oct 31 2014 11:38:41 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Apr 20 2015 13:24:23 +gem5 started Apr 20 2015 13:24:39 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual + Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x479a680 0x479a680 - 0: system.cpu1.isa: ISA system set to: 0x479a680 0x479a680 +info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x4157820 0x4157820 + 0: system.cpu1.isa: ISA system set to: 0x4157820 0x4157820 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +30,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2824340874000 because m5_exit instruction encountered +Exiting @ tick 2625395606000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 13d2ff07c..19c12f6bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.625396 # Nu sim_ticks 2625395606000 # Number of ticks simulated final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95828 # Simulator instruction rate (inst/s) -host_op_rate 116265 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2090645655 # Simulator tick rate (ticks/s) -host_mem_usage 649348 # Number of bytes of host memory used -host_seconds 1255.78 # Real time elapsed on the host +host_inst_rate 105565 # Simulator instruction rate (inst/s) +host_op_rate 128079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2303070285 # Simulator tick rate (ticks/s) +host_mem_usage 586092 # Number of bytes of host memory used +host_seconds 1139.95 # Real time elapsed on the host sim_insts 120339436 # Number of instructions simulated sim_ops 146004136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -779,9 +779,9 @@ system.cpu0.iew.iewDispNonSpecInsts 851019 # Nu system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 275682 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 650409 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal index cc9c3e898..d38aec98b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal @@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33 scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
@@ -199,7 +199,7 @@ oprofile: using timer interrupt. TCP: cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
ALSA device list:
No soundcards found.
@@ -209,6 +209,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 680, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
S: devpts
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index c717b9b07..200432120 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -142,6 +143,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -176,6 +178,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] @@ -193,7 +196,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -218,6 +220,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -286,6 +289,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] @@ -303,7 +307,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -364,6 +367,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] @@ -433,6 +437,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] @@ -561,7 +566,7 @@ wbWidth=8 workload= [system.cpu2.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -575,13 +580,13 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu2.dstage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu2.dtb [system.cpu2.dstage2_mmu.stage2_tlb] @@ -958,6 +963,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu2.itb [system.cpu2.istage2_mmu.stage2_tlb] @@ -1021,9 +1027,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -1034,6 +1042,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1069,6 +1078,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -1103,13 +1113,16 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1157,7 +1170,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -1461,7 +1474,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1648,7 +1660,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1830,7 +1842,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory @@ -1868,13 +1880,16 @@ port=3456 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false -width=8 +width=32 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 40aa358a7..2ca4d069e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: instruction 'mcr dccimvac' unimplemented warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist @@ -23,34 +25,119 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7183, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 9208, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 9352, Bank: 2 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] -warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] -warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 7 +WARNING: Bank is already active! +Command: 0, Timestamp: 6590, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 6595, Bank: 6 warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3] +warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9610, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: instruction 'mcr bpiall' unimplemented +WARNING: Bank is already active! +Command: 0, Timestamp: 7104, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 7593, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 8685, Bank: 7 +WARNING: Bank is already active! +Command: 0, Timestamp: 8108, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10142, Bank: 1 warn: instruction 'mcr dcisw' unimplemented +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7230, Bank: 7 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] -warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index ed22091e6..e3b97ab4a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 31 2014 10:01:44 -gem5 started Oct 31 2014 11:41:22 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Apr 20 2015 13:24:23 +gem5 started Apr 20 2015 13:24:39 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full + Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x40eb680 0x40eb680 - 0: system.cpu1.isa: ISA system set to: 0x40eb680 0x40eb680 - 0: system.cpu2.isa: ISA system set to: 0x40eb680 0x40eb680 + 0: system.cpu0.isa: ISA system set to: 0x2ceff00 0x2ceff00 + 0: system.cpu1.isa: ISA system set to: 0x2ceff00 0x2ceff00 + 0: system.cpu2.isa: ISA system set to: 0x2ceff00 0x2ceff00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 670631f0f..3091cfc63 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.817778 # Nu sim_ticks 2817777605000 # Number of ticks simulated final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297325 # Simulator instruction rate (inst/s) -host_op_rate 361032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6636656496 # Simulator tick rate (ticks/s) -host_mem_usage 622556 # Number of bytes of host memory used -host_seconds 424.58 # Real time elapsed on the host +host_inst_rate 307401 # Simulator instruction rate (inst/s) +host_op_rate 373266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6861547245 # Simulator tick rate (ticks/s) +host_mem_usage 555284 # Number of bytes of host memory used +host_seconds 410.66 # Real time elapsed on the host sim_insts 126237777 # Number of instructions simulated sim_ops 153286368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -321,10 +321,10 @@ system.physmem_0.preEnergy 71094375 # En system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68967548145 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860586619370 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.497600 # Core power per rank (mW) +system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.497599 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal index b3be0ec54..ad91d76dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal @@ -193,7 +193,7 @@ oprofile: using timer interrupt. TCP: cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
ALSA device list:
No soundcards found.
@@ -203,6 +203,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 673, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
S: devpts
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index b4e8db156..f1b645e28 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,15 +20,16 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 -readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -185,7 +186,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -199,7 +200,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -738,8 +738,11 @@ size=4194304 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -1194,9 +1197,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=false -width=8 +width=16 default=system.pc.pciconfig.pio master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master @@ -1242,11 +1247,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side @@ -1584,7 +1592,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1607,7 +1615,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1822,7 +1830,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 7183ecafd..7670d16aa 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 6 2015 22:19:56 -gem5 started Jan 6 2015 22:27:08 -gem5 executing on gabeblackz620.mtv.corp.google.com -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Apr 20 2015 13:24:00 +gem5 started Apr 20 2015 13:25:09 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing + Global frequency set at 1000000000000 ticks per second -info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5125946039500 because m5_exit instruction encountered +Exiting @ tick 5154239928000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index afda1aff8..ca071852e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.154240 # Nu sim_ticks 5154239928000 # Number of ticks simulated final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129299 # Simulator instruction rate (inst/s) -host_op_rate 255578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633591785 # Simulator tick rate (ticks/s) -host_mem_usage 806864 # Number of bytes of host memory used -host_seconds 3155.16 # Real time elapsed on the host +host_inst_rate 179131 # Simulator instruction rate (inst/s) +host_op_rate 354077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2263170239 # Simulator tick rate (ticks/s) +host_mem_usage 759084 # Number of bytes of host memory used +host_seconds 2277.44 # Real time elapsed on the host sim_insts 407959851 # Number of instructions simulated sim_ops 806389826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -512,8 +512,8 @@ system.cpu.iew.iewIQFullEvents 416558 # Nu system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 537061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1047363 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 640ecede9..32adca57b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -29,7 +29,7 @@ Built 1 zonelists. Total pages: 30610 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.008 MHz processor.
+time.c: Detected 2000.006 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -46,7 +46,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812558
+result 7812552
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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