diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot')
11 files changed, 11128 insertions, 9677 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 40315f031..8dbc85977 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,146 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.898811 # Number of seconds simulated -sim_ticks 1898811181000 # Number of ticks simulated -final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899762 # Number of seconds simulated +sim_ticks 1899762444000 # Number of ticks simulated +final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163774 # Simulator instruction rate (inst/s) -host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5540525376 # Simulator tick rate (ticks/s) -host_mem_usage 339592 # Number of bytes of host memory used -host_seconds 342.71 # Real time elapsed on the host -sim_insts 56127436 # Number of instructions simulated -sim_ops 56127436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory -system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450881 # Total number of read requests seen -system.physmem.writeReqs 122253 # Total number of write requests seen -system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28856384 # Total number of bytes read from memory -system.physmem.bytesWritten 7824192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis +host_inst_rate 165662 # Simulator instruction rate (inst/s) +host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5547317951 # Simulator tick rate (ticks/s) +host_mem_usage 338604 # Number of bytes of host memory used +host_seconds 342.47 # Real time elapsed on the host +sim_insts 56733550 # Number of instructions simulated +sim_ops 56733550 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory +system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450402 # Total number of read requests seen +system.physmem.writeReqs 121804 # Total number of write requests seen +system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28825728 # Total number of bytes read from memory +system.physmem.bytesWritten 7795456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry -system.physmem.totGap 1898811160000 # Total gap between requests +system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry +system.physmem.totGap 1899757983000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450881 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 124126 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 121804 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests -system.physmem.totBusLat 2254075000 # Total cycles spent in databus access -system.physmem.totBankLat 5576518750 # Total cycles spent in bank access -system.physmem.avgQLat 18325.99 # Average queueing delay per request -system.physmem.avgBankLat 12369.86 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5296 # 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Total cycles spent in databus access +system.physmem.totBankLat 5553295000 # Total cycles spent in bank access +system.physmem.avgQLat 17222.89 # Average queueing delay per request +system.physmem.avgBankLat 12331.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35695.85 # Average memory access latency -system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34554.21 # Average memory access latency +system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.10 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28764500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2009193000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 611400000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2620593000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3372566000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 640164500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4012730500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271875 # 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miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -549,40 +534,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120840.897727 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256518.502262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255946.242427 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284980 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41522 # number of writebacks -system.iocache.writebacks::total 41522 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 10581841 # Number of BP lookups -system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits +system.cpu0.branchPred.lookups 12335027 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7560815 # DTB read hits -system.cpu0.dtb.read_misses 30461 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 623625 # DTB read accesses -system.cpu0.dtb.write_hits 5040625 # DTB write hits -system.cpu0.dtb.write_misses 7520 # DTB write misses -system.cpu0.dtb.write_acv 334 # DTB write access violations -system.cpu0.dtb.write_accesses 206551 # DTB write accesses -system.cpu0.dtb.data_hits 12601440 # DTB hits -system.cpu0.dtb.data_misses 37981 # DTB misses -system.cpu0.dtb.data_acv 872 # DTB access violations -system.cpu0.dtb.data_accesses 830176 # DTB accesses -system.cpu0.itb.fetch_hits 911527 # ITB hits -system.cpu0.itb.fetch_misses 30644 # ITB misses -system.cpu0.itb.fetch_acv 921 # ITB acv -system.cpu0.itb.fetch_accesses 942171 # ITB accesses +system.cpu0.dtb.read_hits 8753494 # DTB read hits +system.cpu0.dtb.read_misses 29787 # DTB read misses +system.cpu0.dtb.read_acv 536 # DTB read access violations +system.cpu0.dtb.read_accesses 623801 # DTB read accesses +system.cpu0.dtb.write_hits 5745053 # DTB write hits +system.cpu0.dtb.write_misses 8131 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 207769 # DTB write accesses +system.cpu0.dtb.data_hits 14498547 # DTB hits +system.cpu0.dtb.data_misses 37918 # DTB misses +system.cpu0.dtb.data_acv 882 # DTB access violations +system.cpu0.dtb.data_accesses 831570 # DTB accesses +system.cpu0.itb.fetch_hits 986254 # ITB hits +system.cpu0.itb.fetch_misses 27996 # ITB misses +system.cpu0.itb.fetch_acv 985 # ITB acv +system.cpu0.itb.fetch_accesses 1014250 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 89753559 # number of cpu cycles simulated +system.cpu0.numCycles 101860002 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued -system.cpu0.iq.rate 0.488941 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued +system.cpu0.iq.rate 0.500378 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2697587 # number of nop insts executed -system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6879787 # Number of branches executed -system.cpu0.iew.exec_stores 5059363 # Number of stores executed -system.cpu0.iew.exec_rate 0.485294 # Inst execution rate -system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21537449 # num instructions producing a value -system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value +system.cpu0.iew.exec_nop 3200571 # number of nop insts executed +system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8058196 # Number of branches executed +system.cpu0.iew.exec_stores 5766685 # Number of stores executed +system.cpu0.iew.exec_rate 0.496575 # Inst execution rate +system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25063994 # num instructions producing a value +system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 43662606 # Number of instructions committed -system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50693798 # Number of instructions committed +system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11854981 # Number of memory references committed -system.cpu0.commit.loads 6964106 # Number of loads committed -system.cpu0.commit.membars 168172 # Number of memory barriers committed -system.cpu0.commit.branches 6551324 # Number of branches committed -system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. -system.cpu0.commit.function_calls 540020 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13627446 # Number of memory references committed +system.cpu0.commit.loads 8065517 # Number of loads committed +system.cpu0.commit.membars 196376 # Number of memory barriers committed +system.cpu0.commit.branches 7658577 # Number of branches committed +system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. +system.cpu0.commit.function_calls 646517 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 110111593 # The number of ROB reads -system.cpu0.rob.rob_writes 98948174 # The number of ROB writes -system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41199881 # Number of Instructions Simulated -system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated -system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes -system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads -system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads -system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes +system.cpu0.rob.rob_reads 129054613 # The number of ROB reads +system.cpu0.rob.rob_writes 115056832 # The number of ROB writes +system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47774945 # Number of Instructions Simulated +system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated +system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads +system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads +system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 728874 # number of replacements -system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use -system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits -system.cpu0.icache.overall_hits::total 5890439 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses -system.cpu0.icache.overall_misses::total 766860 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked +system.cpu0.icache.replacements 863258 # number of replacements +system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use +system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits +system.cpu0.icache.overall_hits::total 6729374 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses +system.cpu0.icache.overall_misses::total 907848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 729542 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 729542 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 729542 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 729542 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8901782997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1051655 # number of replacements -system.cpu0.dcache.tagsinuse 479.291529 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8945957 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1052167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.502412 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1272639 # number of replacements +system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits -system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses -system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits +system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses +system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks -system.cpu0.dcache.writebacks::total 554167 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks +system.cpu0.dcache.writebacks::total 748565 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4327546 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits +system.cpu1.branchPred.lookups 2650086 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3068448 # DTB read hits -system.cpu1.dtb.read_misses 13337 # DTB read misses -system.cpu1.dtb.read_acv 21 # DTB read access violations -system.cpu1.dtb.read_accesses 325420 # DTB read accesses -system.cpu1.dtb.write_hits 1915630 # DTB write hits -system.cpu1.dtb.write_misses 2521 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 132592 # DTB write accesses -system.cpu1.dtb.data_hits 4984078 # DTB hits -system.cpu1.dtb.data_misses 15858 # DTB misses -system.cpu1.dtb.data_acv 89 # DTB access violations -system.cpu1.dtb.data_accesses 458012 # DTB accesses -system.cpu1.itb.fetch_hits 498592 # ITB hits -system.cpu1.itb.fetch_misses 6957 # ITB misses -system.cpu1.itb.fetch_acv 210 # ITB acv -system.cpu1.itb.fetch_accesses 505549 # ITB accesses +system.cpu1.dtb.read_hits 1963408 # DTB read hits +system.cpu1.dtb.read_misses 10761 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325022 # DTB read accesses +system.cpu1.dtb.write_hits 1266270 # DTB write hits +system.cpu1.dtb.write_misses 2185 # DTB write misses +system.cpu1.dtb.write_acv 66 # DTB write access violations +system.cpu1.dtb.write_accesses 133146 # DTB write accesses +system.cpu1.dtb.data_hits 3229678 # DTB hits +system.cpu1.dtb.data_misses 12946 # DTB misses +system.cpu1.dtb.data_acv 93 # DTB access violations +system.cpu1.dtb.data_accesses 458168 # DTB accesses +system.cpu1.itb.fetch_hits 437746 # ITB hits +system.cpu1.itb.fetch_misses 6892 # ITB misses +system.cpu1.itb.fetch_acv 236 # ITB acv +system.cpu1.itb.fetch_accesses 444638 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1219,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 28341850 # number of cpu cycles simulated +system.cpu1.numCycles 16144974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued -system.cpu1.iq.rate 0.572889 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued +system.cpu1.iq.rate 0.600865 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 989430 # number of nop insts executed -system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2535241 # Number of branches executed -system.cpu1.iew.exec_stores 1924592 # Number of stores executed -system.cpu1.iew.exec_rate 0.567378 # Inst execution rate -system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7724743 # num instructions producing a value -system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value +system.cpu1.iew.exec_nop 515192 # number of nop insts executed +system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1435370 # Number of branches executed +system.cpu1.iew.exec_stores 1274468 # Number of stores executed +system.cpu1.iew.exec_rate 0.595272 # Inst execution rate +system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4461159 # num instructions producing a value +system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15801951 # Number of instructions committed -system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9413351 # Number of instructions committed +system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4623326 # Number of memory references committed -system.cpu1.commit.loads 2789628 # Number of loads committed -system.cpu1.commit.membars 68640 # Number of memory barriers committed -system.cpu1.commit.branches 2366242 # Number of branches committed -system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. -system.cpu1.commit.function_calls 250839 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3003807 # Number of memory references committed +system.cpu1.commit.loads 1788957 # Number of loads committed +system.cpu1.commit.membars 45075 # Number of memory barriers committed +system.cpu1.commit.branches 1347256 # Number of branches committed +system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. +system.cpu1.commit.function_calls 150668 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 42991260 # The number of ROB reads -system.cpu1.rob.rob_writes 37176651 # The number of ROB writes -system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14927555 # Number of Instructions Simulated -system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated -system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads -system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads -system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes -system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads -system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes -system.cpu1.icache.replacements 359909 # number of replacements -system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use -system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits -system.cpu1.icache.overall_hits::total 2054105 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses -system.cpu1.icache.overall_misses::total 376623 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 25388124 # The number of ROB reads +system.cpu1.rob.rob_writes 22088528 # The number of ROB writes +system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8958605 # Number of Instructions Simulated +system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated +system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads +system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes +system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes +system.cpu1.icache.replacements 226821 # number of replacements +system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use +system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits +system.cpu1.icache.overall_hits::total 1277714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses +system.cpu1.icache.overall_misses::total 235963 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 377681 # number of replacements -system.cpu1.dcache.tagsinuse 497.778191 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3769592 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 378084 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.970250 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 35370260000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 497.778191 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.972223 # 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number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses -system.cpu1.dcache.overall_misses::total 950793 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.959975 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1619180 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1619180 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 952866 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 952866 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33989 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33989 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32614 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32614 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2572046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2572046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2572046 # 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number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3001407 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143053 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks -system.cpu1.dcache.writebacks::total 289966 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks +system.cpu1.dcache.writebacks::total 72108 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1786,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed -system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed -system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 144957 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed +system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 166884 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1257 system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2839 # number of times the context was actually changed +system.cpu0.kern.swap_context 3470 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1863,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed -system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71331 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches +system.cpu1.kern.callpal::total 51275 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 709 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 69 -system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 221 +system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1408 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1141 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 02dc83699..856de11b9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,137 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854310111000 # Number of ticks simulated -final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854307 # Number of seconds simulated +sim_ticks 1854307399500 # Number of ticks simulated +final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145253 # Simulator instruction rate (inst/s) -host_op_rate 145253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5083862253 # Simulator tick rate (ticks/s) -host_mem_usage 332668 # Number of bytes of host memory used -host_seconds 364.74 # Real time elapsed on the host -sim_insts 52980262 # Number of instructions simulated -sim_ops 52980262 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445214 # Total number of read requests seen -system.physmem.writeReqs 117421 # Total number of write requests seen -system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28493696 # Total number of bytes read from memory -system.physmem.bytesWritten 7514944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis +host_inst_rate 106006 # Simulator instruction rate (inst/s) +host_op_rate 106006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3711029376 # Simulator tick rate (ticks/s) +host_mem_usage 333480 # Number of bytes of host memory used +host_seconds 499.67 # Real time elapsed on the host +sim_insts 52968721 # Number of instructions simulated +sim_ops 52968721 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445178 # Total number of read requests seen +system.physmem.writeReqs 117206 # Total number of write requests seen +system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28491392 # Total number of bytes read from memory +system.physmem.bytesWritten 7501184 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854304705000 # Total gap between requests +system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854301986000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445214 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118367 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 174 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 445178 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 117206 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -141,70 +128,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests -system.physmem.totBusLat 2225790000 # Total cycles spent in databus access -system.physmem.totBankLat 5510477500 # Total cycles spent in bank access -system.physmem.avgQLat 17776.60 # Average queueing delay per request -system.physmem.avgBankLat 12378.70 # Average bank access latency per request +system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests +system.physmem.totBusLat 2225595000 # Total cycles spent in databus access +system.physmem.totBankLat 5484971250 # Total cycles spent in bank access +system.physmem.avgQLat 16848.23 # Average queueing delay per request +system.physmem.avgBankLat 12322.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35155.30 # Average memory access latency -system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 34170.72 # Average memory access latency +system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 417628 # Number of row buffer hits during reads -system.physmem.writeRowHits 91533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes -system.physmem.avgGap 3295750.72 # Average gap between requests +system.physmem.avgWrQLen 14.44 # Average write queue length over time +system.physmem.readRowHits 417746 # Number of row buffer hits during reads +system.physmem.writeRowHits 91351 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes +system.physmem.avgGap 3297216.82 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265053 # Cycle average of tags in use +system.iocache.tagsinuse 1.265036 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +248,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +264,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13838840 # Number of BP lookups -system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits +system.cpu.branchPred.lookups 13852347 # Number of BP lookups +system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926019 # DTB read hits -system.cpu.dtb.read_misses 41533 # DTB read misses -system.cpu.dtb.read_acv 530 # DTB read access violations -system.cpu.dtb.read_accesses 942239 # DTB read accesses -system.cpu.dtb.write_hits 6593693 # DTB write hits -system.cpu.dtb.write_misses 10528 # DTB write misses -system.cpu.dtb.write_acv 400 # DTB write access violations -system.cpu.dtb.write_accesses 337995 # DTB write accesses -system.cpu.dtb.data_hits 16519712 # DTB hits -system.cpu.dtb.data_misses 52061 # DTB misses -system.cpu.dtb.data_acv 930 # DTB access violations -system.cpu.dtb.data_accesses 1280234 # DTB accesses -system.cpu.itb.fetch_hits 1304342 # ITB hits -system.cpu.itb.fetch_misses 39856 # ITB misses -system.cpu.itb.fetch_acv 1022 # ITB acv -system.cpu.itb.fetch_accesses 1344198 # ITB accesses +system.cpu.dtb.read_hits 9912757 # DTB read hits +system.cpu.dtb.read_misses 41466 # DTB read misses +system.cpu.dtb.read_acv 543 # DTB read access violations +system.cpu.dtb.read_accesses 941271 # DTB read accesses +system.cpu.dtb.write_hits 6601987 # DTB write hits +system.cpu.dtb.write_misses 10361 # DTB write misses +system.cpu.dtb.write_acv 401 # DTB write access violations +system.cpu.dtb.write_accesses 337783 # DTB write accesses +system.cpu.dtb.data_hits 16514744 # DTB hits +system.cpu.dtb.data_misses 51827 # DTB misses +system.cpu.dtb.data_acv 944 # DTB access violations +system.cpu.dtb.data_accesses 1279054 # DTB accesses +system.cpu.itb.fetch_hits 1307981 # ITB hits +system.cpu.itb.fetch_misses 36519 # ITB misses +system.cpu.itb.fetch_acv 1105 # ITB acv +system.cpu.itb.fetch_accesses 1344500 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +326,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109629781 # number of cpu cycles simulated +system.cpu.numCycles 108624305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued -system.cpu.iq.rate 0.518227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued +system.cpu.iq.rate 0.522989 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3526575 # number of nop insts executed -system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed -system.cpu.iew.exec_branches 8926807 # Number of branches executed -system.cpu.iew.exec_stores 6619441 # Number of stores executed -system.cpu.iew.exec_rate 0.513966 # Inst execution rate -system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27769565 # num instructions producing a value -system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value +system.cpu.iew.exec_nop 3528457 # number of nop insts executed +system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925181 # Number of branches executed +system.cpu.iew.exec_stores 6627584 # Number of stores executed +system.cpu.iew.exec_rate 0.518660 # Inst execution rate +system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27773544 # num instructions producing a value +system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56171016 # Number of instructions committed -system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56158922 # Number of instructions committed +system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470138 # Number of memory references committed -system.cpu.commit.loads 9092263 # Number of loads committed -system.cpu.commit.membars 226349 # Number of memory barriers committed -system.cpu.commit.branches 8440338 # Number of branches committed +system.cpu.commit.refs 15466723 # Number of memory references committed +system.cpu.commit.loads 9090045 # Number of loads committed +system.cpu.commit.membars 226335 # Number of memory barriers committed +system.cpu.commit.branches 8439344 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020652 # Number of committed integer instructions. -system.cpu.commit.function_calls 740552 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52009184 # Number of committed integer instructions. +system.cpu.commit.function_calls 740395 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140865752 # The number of ROB reads -system.cpu.rob.rob_writes 128516921 # The number of ROB writes -system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52980262 # Number of Instructions Simulated -system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated -system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads -system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73880365 # number of integer regfile reads -system.cpu.int_regfile_writes 40316413 # number of integer regfile writes -system.cpu.fp_regfile_reads 166011 # number of floating regfile reads -system.cpu.fp_regfile_writes 167446 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads -system.cpu.misc_regfile_writes 938994 # number of misc regfile writes +system.cpu.rob.rob_reads 140815408 # The number of ROB reads +system.cpu.rob.rob_writes 128505533 # The number of ROB writes +system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52968721 # Number of Instructions Simulated +system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated +system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73881531 # number of integer regfile reads +system.cpu.int_regfile_writes 40312822 # number of integer regfile writes +system.cpu.fp_regfile_reads 166061 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads +system.cpu.misc_regfile_writes 938918 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +620,197 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008798 # number of replacements -system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use -system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits -system.cpu.icache.overall_hits::total 7480627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses -system.cpu.icache.overall_misses::total 1065018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked +system.cpu.icache.replacements 1008795 # number of replacements +system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use +system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits +system.cpu.icache.overall_hits::total 7484837 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses +system.cpu.icache.overall_misses::total 1065140 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55619 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55619 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994342 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15055 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288830 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15055 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389170 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15055 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389170 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404225 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8594985001 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9446607751 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +900,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401332 # number of replacements -system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use -system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1400597 # number of replacements +system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use +system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits -system.cpu.dcache.overall_hits::total 11417051 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses -system.cpu.dcache.overall_misses::total 3745325 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits +system.cpu.dcache.overall_hits::total 11402525 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses +system.cpu.dcache.overall_misses::total 3745583 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks -system.cpu.dcache.writebacks::total 840875 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks +system.cpu.dcache.writebacks::total 840320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1063,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,7 +1123,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1131,7 +1132,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191985 # number of callpals executed +system.cpu.kern.callpal::total 191959 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1142,9 +1143,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326552 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 014619ced..1f0f241e7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,154 +1,141 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841686 # Number of seconds simulated -sim_ticks 1841685645500 # Number of ticks simulated -final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841685557500 # Number of ticks simulated +final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300759 # Simulator instruction rate (inst/s) -host_op_rate 300759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7981184825 # Simulator tick rate (ticks/s) -host_mem_usage 313952 # Number of bytes of host memory used -host_seconds 230.75 # Real time elapsed on the host -sim_insts 69401254 # Number of instructions simulated -sim_ops 69401254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory +host_inst_rate 244491 # Simulator instruction rate (inst/s) +host_op_rate 244491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6478446279 # Simulator tick rate (ticks/s) +host_mem_usage 315916 # Number of bytes of host memory used +host_seconds 284.28 # Real time elapsed on the host +sim_insts 69503534 # Number of instructions simulated +sim_ops 69503534 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19348096 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2814720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2705088 # Number of bytes read from this memory +system.physmem.bytes_read::total 28439424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302314 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 2345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444366 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116828 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10505646 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1528339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 160132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1468811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 160132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10505646 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109303 # Total number of read requests seen -system.physmem.writeReqs 45531 # Total number of write requests seen -system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6995392 # Total number of bytes read from memory -system.physmem.bytesWritten 2913984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 81491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1528339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 160132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1468811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109963 # Total number of read requests seen +system.physmem.writeReqs 45515 # Total number of write requests seen +system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7037632 # Total number of bytes read from memory +system.physmem.bytesWritten 2912960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2912960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 40 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6845 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2595 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3044 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2867 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2811 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840673558000 # Total gap between requests +system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673470000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109303 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 41 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.readPktSize::6 109963 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 45515 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,240 +148,242 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests -system.physmem.totBusLat 546485000 # Total cycles spent in databus access -system.physmem.totBankLat 1450817500 # Total cycles spent in bank access -system.physmem.avgQLat 22145.05 # Average queueing delay per request -system.physmem.avgBankLat 13274.08 # Average bank access latency per request +system.physmem.wrQLenPdf::18 1963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests +system.physmem.totBusLat 549785000 # Total cycles spent in databus access +system.physmem.totBankLat 1460648750 # Total cycles spent in bank access +system.physmem.avgQLat 21612.10 # Average queueing delay per request +system.physmem.avgBankLat 13283.82 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40419.14 # Average memory access latency -system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 39895.91 # Average memory access latency +system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52183.727932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33865.108789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 54830.353299 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44582.685919 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40224.412026 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,12 +494,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255467 # Cycle average of tags in use +system.iocache.tagsinuse 1.255479 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.warmup_cycle 1693875860000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255479 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses @@ -521,14 +510,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 10497998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 10497998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4320435904 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4320435904 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4330933902 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4330933902 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4330933902 # 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number of WriteReq accesses(hits+misses) @@ -545,19 +534,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.406331 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,14 +560,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16837 system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6909249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6909249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3447972406 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3454881655 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3454881655 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -587,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4870222 # DTB read hits -system.cpu0.dtb.read_misses 6004 # DTB read misses -system.cpu0.dtb.read_acv 119 # DTB read access violations -system.cpu0.dtb.read_accesses 427226 # DTB read accesses -system.cpu0.dtb.write_hits 3495920 # DTB write hits -system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.read_hits 4874109 # DTB read hits +system.cpu0.dtb.read_misses 5989 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 427176 # DTB read accesses +system.cpu0.dtb.write_hits 3500725 # DTB write hits +system.cpu0.dtb.write_misses 661 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162893 # DTB write accesses -system.cpu0.dtb.data_hits 8366142 # DTB hits -system.cpu0.dtb.data_misses 6666 # DTB misses -system.cpu0.dtb.data_acv 201 # DTB access violations -system.cpu0.dtb.data_accesses 590119 # DTB accesses -system.cpu0.itb.fetch_hits 2742252 # ITB hits -system.cpu0.itb.fetch_misses 2999 # ITB misses -system.cpu0.itb.fetch_acv 100 # ITB acv -system.cpu0.itb.fetch_accesses 2745251 # ITB accesses +system.cpu0.dtb.write_accesses 162885 # DTB write accesses +system.cpu0.dtb.data_hits 8374834 # DTB hits +system.cpu0.dtb.data_misses 6650 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 590061 # DTB accesses +system.cpu0.itb.fetch_hits 2743092 # ITB hits +system.cpu0.itb.fetch_misses 2995 # ITB misses +system.cpu0.itb.fetch_acv 98 # ITB acv +system.cpu0.itb.fetch_accesses 2746087 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -640,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928524557 # number of cpu cycles simulated +system.cpu0.numCycles 928539725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32346409 # Number of instructions committed -system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses -system.cpu0.num_func_calls 807221 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30227600 # number of integer instructions -system.cpu0.num_fp_insts 167714 # number of float instructions -system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written -system.cpu0.num_mem_refs 8395829 # number of memory refs -system.cpu0.num_load_insts 4891258 # Number of load instructions -system.cpu0.num_store_insts 3504571 # Number of store instructions -system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles -system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles -system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles +system.cpu0.committedInsts 32518253 # Number of instructions committed +system.cpu0.committedOps 32518253 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30397519 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168035 # Number of float alu accesses +system.cpu0.num_func_calls 808172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4307008 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30397519 # number of integer instructions +system.cpu0.num_fp_insts 168035 # number of float instructions +system.cpu0.num_int_register_reads 42396693 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22221610 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86774 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88345 # number of times the floating registers were written +system.cpu0.num_mem_refs 8404498 # number of memory refs +system.cpu0.num_load_insts 4895120 # Number of load instructions +system.cpu0.num_store_insts 3509378 # Number of store instructions +system.cpu0.num_idle_cycles 214025441196.436279 # Number of idle cycles +system.cpu0.num_busy_cycles -213096901471.436279 # Number of busy cycles +system.cpu0.not_idle_fraction -229.496806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.496806 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818586321500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38755000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363405500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696319000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684801000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694792 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -720,10 +709,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -732,21 +721,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192218 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.callpal::total 192213 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4178 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::total 0.391349 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29734416500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2561211500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809389169500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -778,356 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 952688 # number of replacements -system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use -system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7734855 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2288179 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41854962 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7734855 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2288179 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41854962 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7734855 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2288179 # number of overall hits -system.cpu0.icache.overall_hits::total 41854962 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970349 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970349 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320072 # number of overall misses -system.cpu0.icache.overall_misses::total 970349 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473861486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287825986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4473861486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287825986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4473861486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287825986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked +system.cpu0.icache.replacements 953667 # number of replacements +system.cpu0.icache.tagsinuse 511.197543 # Cycle average of tags in use +system.cpu0.icache.total_refs 42031546 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 954178 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.050005 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10246755000 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32525103 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7872875 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2604896 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43002874 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016051 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016394 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122925 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022588 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016051 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016394 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122925 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14051.789727 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.787680 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6475.089755 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4631 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.168478 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285653 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 476174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1502 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 761827 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 761827 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 761827 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 104504 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262049 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366553 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85019 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133082 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7751 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152567 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347068 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 499635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152567 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347068 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 499635 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1975725000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4306208500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6281933500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1299140000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2144349624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3443489624 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24977000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70824000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95801000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3274865000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6450558124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9725423124 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3274865000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6450558124 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9725423124 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287731500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 345150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 632882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357324500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 421745500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 779070000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645056000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 766896000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411952000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086890 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088411 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041068 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.052979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021633 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.100173 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033138 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072309 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071790 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033138 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18905.735666 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.836989 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17137.858645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27029.939871 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25222.004775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25874.946454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11389.420885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12742.713206 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12359.824539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21465.094024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.862494 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.055739 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1142,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220324 # DTB read hits -system.cpu1.dtb.read_misses 1556 # DTB read misses -system.cpu1.dtb.read_acv 46 # DTB read access violations -system.cpu1.dtb.read_accesses 144016 # DTB read accesses -system.cpu1.dtb.write_hits 928239 # DTB write hits -system.cpu1.dtb.write_misses 207 # DTB write misses +system.cpu1.dtb.read_hits 1221793 # DTB read hits +system.cpu1.dtb.read_misses 1550 # DTB read misses +system.cpu1.dtb.read_acv 45 # DTB read access violations +system.cpu1.dtb.read_accesses 143987 # DTB read accesses +system.cpu1.dtb.write_hits 928954 # DTB write hits +system.cpu1.dtb.write_misses 206 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 60107 # DTB write accesses -system.cpu1.dtb.data_hits 2148563 # DTB hits -system.cpu1.dtb.data_misses 1763 # DTB misses -system.cpu1.dtb.data_acv 70 # DTB access violations -system.cpu1.dtb.data_accesses 204123 # DTB accesses -system.cpu1.itb.fetch_hits 875123 # ITB hits -system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.dtb.write_accesses 60098 # DTB write accesses +system.cpu1.dtb.data_hits 2150747 # DTB hits +system.cpu1.dtb.data_misses 1756 # DTB misses +system.cpu1.dtb.data_acv 69 # DTB access violations +system.cpu1.dtb.data_accesses 204085 # DTB accesses +system.cpu1.itb.fetch_hits 875028 # ITB hits +system.cpu1.itb.fetch_misses 772 # ITB misses system.cpu1.itb.fetch_acv 46 # ITB acv -system.cpu1.itb.fetch_accesses 875897 # ITB accesses +system.cpu1.itb.fetch_accesses 875800 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1170,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953544041 # number of cpu cycles simulated +system.cpu1.numCycles 953543873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861950 # Number of instructions committed -system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses -system.cpu1.num_func_calls 212083 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7314131 # number of integer instructions -system.cpu1.num_fp_insts 45433 # number of float instructions -system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156447 # number of memory refs -system.cpu1.num_load_insts 1225739 # Number of load instructions -system.cpu1.num_store_insts 930708 # Number of store instructions -system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles -system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles -system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles +system.cpu1.committedInsts 7871049 # Number of instructions committed +system.cpu1.committedOps 7871049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7322486 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45486 # Number of float alu accesses +system.cpu1.num_func_calls 212361 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 961543 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7322486 # number of integer instructions +system.cpu1.num_fp_insts 45486 # number of float instructions +system.cpu1.num_int_register_reads 10177666 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5328829 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24537 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24857 # number of times the floating registers were written +system.cpu1.num_mem_refs 2158619 # number of memory refs +system.cpu1.num_load_insts 1227197 # Number of load instructions +system.cpu1.num_store_insts 931422 # Number of store instructions +system.cpu1.num_idle_cycles -1678612352.135852 # Number of idle cycles +system.cpu1.num_busy_cycles 2632156225.135852 # Number of busy cycles +system.cpu1.not_idle_fraction 2.760393 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.760393 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1209,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8412639 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits +system.cpu2.branchPred.lookups 8388883 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7698653 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129790 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6809522 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5746337 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.386790 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 285994 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3230838 # DTB read hits -system.cpu2.dtb.read_misses 11458 # DTB read misses -system.cpu2.dtb.read_acv 112 # DTB read access violations -system.cpu2.dtb.read_accesses 217040 # DTB read accesses -system.cpu2.dtb.write_hits 2001661 # DTB write hits -system.cpu2.dtb.write_misses 2605 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 81606 # DTB write accesses -system.cpu2.dtb.data_hits 5232499 # DTB hits -system.cpu2.dtb.data_misses 14063 # DTB misses -system.cpu2.dtb.data_acv 255 # DTB access violations -system.cpu2.dtb.data_accesses 298646 # DTB accesses -system.cpu2.itb.fetch_hits 371716 # ITB hits -system.cpu2.itb.fetch_misses 5691 # ITB misses -system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 377407 # ITB accesses +system.cpu2.dtb.read_hits 3222753 # DTB read hits +system.cpu2.dtb.read_misses 11767 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 216394 # DTB read accesses +system.cpu2.dtb.write_hits 1997746 # DTB write hits +system.cpu2.dtb.write_misses 2597 # DTB write misses +system.cpu2.dtb.write_acv 133 # DTB write access violations +system.cpu2.dtb.write_accesses 81219 # DTB write accesses +system.cpu2.dtb.data_hits 5220499 # DTB hits +system.cpu2.dtb.data_misses 14364 # DTB misses +system.cpu2.dtb.data_acv 247 # DTB access violations +system.cpu2.dtb.data_accesses 297613 # DTB accesses +system.cpu2.itb.fetch_hits 371919 # ITB hits +system.cpu2.itb.fetch_misses 5650 # ITB misses +system.cpu2.itb.fetch_acv 270 # ITB acv +system.cpu2.itb.fetch_accesses 377569 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1250,141 +1255,141 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30535693 # number of cpu cycles simulated +system.cpu2.numCycles 30487191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8524791 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34873991 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8388883 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6032331 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8111828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 622665 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9676306 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62420 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 80561 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2604903 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90729 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297649 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18762923 69.82% 69.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 273694 1.02% 70.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440641 1.64% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4237897 15.77% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 736346 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166761 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196079 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433619 1.61% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1626791 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26874751 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275161 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.143890 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8657787 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9768162 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7515953 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293497 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 393434 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168963 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12933 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34472576 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40526 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 393434 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9012684 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2836795 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5769605 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7372565 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1243759 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33316352 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2373 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 408588 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22366948 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41510379 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41345500 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 164879 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20534540 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832408 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 504738 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60071 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3686935 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3385510 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2088081 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 373278 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254690 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30792200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 629969 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30337437 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2187587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1093629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 444846 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26874751 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128845 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565283 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15311841 56.97% 56.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3103500 11.55% 68.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1551808 5.77% 74.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5059769 18.83% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 912287 3.39% 96.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 489619 1.82% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286015 1.06% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141615 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18297 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26874751 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34821 13.89% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112497 44.88% 58.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103352 41.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24640378 81.22% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20252 0.07% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8482 0.03% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued @@ -1406,114 +1411,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3354206 11.06% 92.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2020424 6.66% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290023 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued -system.cpu2.iq.rate 0.996064 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30337437 # Type of FU issued +system.cpu2.iq.rate 0.995088 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 250670 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008263 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87595744 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33498169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29934734 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 236555 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115613 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112132 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30462481 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123178 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 189585 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 417411 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 964 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4105 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 161809 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4731 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 22958 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 393434 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2055085 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212014 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32707784 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224122 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3385510 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2088081 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 559310 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 150319 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2295 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4105 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130024 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196897 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30173481 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3242841 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 163956 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1286376 # number of nop insts executed -system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6817857 # Number of branches executed -system.cpu2.iew.exec_stores 2008777 # Number of stores executed -system.cpu2.iew.exec_rate 0.990668 # Inst execution rate -system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17393530 # num instructions producing a value -system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285615 # number of nop insts executed +system.cpu2.iew.exec_refs 5247672 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6797242 # Number of branches executed +system.cpu2.iew.exec_stores 2004831 # Number of stores executed +system.cpu2.iew.exec_rate 0.989710 # Inst execution rate +system.cpu2.iew.wb_sent 30079535 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30046866 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17352028 # num instructions producing a value +system.cpu2.iew.wb_consumers 20589621 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.985557 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842756 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2372790 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185123 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182681 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26481317 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.143824 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.850690 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16366667 61.80% 61.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2324205 8.78% 70.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1216165 4.59% 75.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4790733 18.09% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501931 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186373 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179761 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180772 0.68% 97.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 734710 2.77% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370564 # Number of instructions committed -system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26481317 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30289973 # Number of instructions committed +system.cpu2.commit.committedOps 30289973 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4905590 # Number of memory references committed -system.cpu2.commit.loads 2973683 # Number of loads committed -system.cpu2.commit.membars 65235 # Number of memory barriers committed -system.cpu2.commit.branches 6667985 # Number of branches committed -system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions. -system.cpu2.commit.function_calls 232233 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4894371 # Number of memory references committed +system.cpu2.commit.loads 2968099 # Number of loads committed +system.cpu2.commit.membars 65019 # Number of memory barriers committed +system.cpu2.commit.branches 6647353 # Number of branches committed +system.cpu2.commit.fp_insts 110870 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28830509 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231619 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 734710 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58454819 # The number of ROB reads -system.cpu2.rob.rob_writes 65882909 # The number of ROB writes -system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29192895 # Number of Instructions Simulated -system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated -system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads -system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads -system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes +system.cpu2.rob.rob_reads 58337288 # The number of ROB reads +system.cpu2.rob.rob_writes 65718838 # The number of ROB writes +system.cpu2.timesIdled 243105 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3612440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745337726 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29114232 # Number of Instructions Simulated +system.cpu2.committedOps 29114232 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29114232 # Number of Instructions Simulated +system.cpu2.cpi 1.047158 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047158 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954966 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954966 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39679960 # number of integer regfile reads +system.cpu2.int_regfile_writes 21237504 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68414 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68689 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4591435 # number of misc regfile reads +system.cpu2.misc_regfile_writes 259923 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 9c75c4e0e..b54fd326b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,153 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533148 # Number of seconds simulated -sim_ticks 2533147650000 # Number of ticks simulated -final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533144 # Number of seconds simulated +sim_ticks 2533143504000 # Number of ticks simulated +final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55856 # Simulator instruction rate (inst/s) -host_op_rate 71871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2346171672 # Simulator tick rate (ticks/s) -host_mem_usage 407620 # Number of bytes of host memory used -host_seconds 1079.69 # Real time elapsed on the host -sim_insts 60307315 # Number of instructions simulated -sim_ops 77598799 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 65433 # Simulator instruction rate (inst/s) +host_op_rate 84194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2748425484 # Simulator tick rate (ticks/s) +host_mem_usage 408856 # Number of bytes of host memory used +host_seconds 921.67 # Real time elapsed on the host +sim_insts 60307579 # Number of instructions simulated +sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096808 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195712 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096820 # Total number of read requests seen +system.physmem.writeReqs 813121 # Total number of write requests seen +system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196480 # Total number of bytes read from memory +system.physmem.bytesWritten 52039744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533146526000 # Total gap between requests +system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533142364000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154564 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2990994 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59094 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59103 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -164,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see @@ -181,31 +155,30 @@ system.physmem.wrQLenPdf::12 35353 # Wh system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access -system.physmem.totBankLat 16909805000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.29 # Average queueing delay per request -system.physmem.avgBankLat 1120.11 # Average bank access latency per request +system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482965000 # Total cycles spent in databus access +system.physmem.totBankLat 16912788750 # Total cycles spent in bank access +system.physmem.avgQLat 26048.65 # Average queueing delay per request +system.physmem.avgBankLat 1120.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgMemAccLat 32168.96 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -213,32 +186,44 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.48 # Average write queue length over time -system.physmem.readRowHits 15020221 # Number of row buffer hits during reads -system.physmem.writeRowHits 793131 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.55 # Average write queue length over time +system.physmem.readRowHits 15020273 # Number of row buffer hits during reads +system.physmem.writeRowHits 793117 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159218.06 # Average gap between requests +system.physmem.avgGap 159217.58 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14676489 # Number of BP lookups -system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits +system.cpu.branchPred.lookups 14678084 # Number of BP lookups +system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987326 # DTB read hits +system.cpu.checker.dtb.read_hits 14987411 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227680 # DTB write hits +system.cpu.checker.dtb.write_hits 11227746 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -249,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215006 # DTB hits +system.cpu.checker.dtb.hits 26215157 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224497 # DTB accesses -system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits +system.cpu.checker.dtb.accesses 26224648 # DTB accesses +system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -272,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses -system.cpu.checker.itb.hits 61481313 # DTB hits +system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses +system.cpu.checker.itb.hits 61481576 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61485784 # DTB accesses -system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486047 # DTB accesses +system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51394402 # DTB read hits -system.cpu.dtb.read_misses 64202 # DTB read misses -system.cpu.dtb.write_hits 11700782 # DTB write hits -system.cpu.dtb.write_misses 15842 # DTB write misses +system.cpu.dtb.read_hits 51401633 # DTB read hits +system.cpu.dtb.read_misses 64365 # DTB read misses +system.cpu.dtb.write_hits 11702282 # DTB write hits +system.cpu.dtb.write_misses 15903 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51458604 # DTB read accesses -system.cpu.dtb.write_accesses 11716624 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465998 # DTB read accesses +system.cpu.dtb.write_accesses 11718185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63095184 # DTB hits -system.cpu.dtb.misses 80044 # DTB misses -system.cpu.dtb.accesses 63175228 # DTB accesses -system.cpu.itb.inst_hits 12330326 # ITB inst hits -system.cpu.itb.inst_misses 11351 # ITB inst misses +system.cpu.dtb.hits 63103915 # DTB hits +system.cpu.dtb.misses 80268 # DTB misses +system.cpu.dtb.accesses 63184183 # DTB accesses +system.cpu.itb.inst_hits 12333169 # ITB inst hits +system.cpu.itb.inst_misses 11311 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -310,114 +295,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12341677 # ITB inst accesses -system.cpu.itb.hits 12330326 # DTB hits -system.cpu.itb.misses 11351 # DTB misses -system.cpu.itb.accesses 12341677 # DTB accesses -system.cpu.numCycles 471833351 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12344480 # ITB inst accesses +system.cpu.itb.hits 12333169 # DTB hits +system.cpu.itb.misses 11311 # DTB misses +system.cpu.itb.accesses 12344480 # DTB accesses +system.cpu.numCycles 471839315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available @@ -445,13 +430,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -464,11 +449,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued @@ -477,351 +462,351 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued -system.cpu.iq.rate 0.263486 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued +system.cpu.iq.rate 0.263513 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220665 # number of nop insts executed -system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561887 # Number of branches executed -system.cpu.iew.exec_stores 12212575 # Number of stores executed -system.cpu.iew.exec_rate 0.257603 # Inst execution rate -system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47219839 # num instructions producing a value -system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value +system.cpu.iew.exec_nop 220929 # number of nop insts executed +system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed +system.cpu.iew.exec_branches 11562998 # Number of branches executed +system.cpu.iew.exec_stores 12213915 # Number of stores executed +system.cpu.iew.exec_rate 0.257621 # Inst execution rate +system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47225460 # num instructions producing a value +system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457696 # Number of instructions committed -system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457960 # Number of instructions committed +system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386450 # Number of memory references committed -system.cpu.commit.loads 15654440 # Number of loads committed -system.cpu.commit.membars 403595 # Number of memory barriers committed -system.cpu.commit.branches 9961299 # Number of branches committed +system.cpu.commit.refs 27386605 # Number of memory references committed +system.cpu.commit.loads 15654525 # Number of loads committed +system.cpu.commit.membars 403599 # Number of memory barriers committed +system.cpu.commit.branches 9961316 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. -system.cpu.commit.function_calls 991256 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. +system.cpu.commit.function_calls 991257 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242385214 # The number of ROB reads -system.cpu.rob.rob_writes 202032533 # The number of ROB writes -system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307315 # Number of Instructions Simulated -system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated -system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550300284 # number of integer regfile reads -system.cpu.int_regfile_writes 88460224 # number of integer regfile writes -system.cpu.fp_regfile_reads 8330 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads -system.cpu.misc_regfile_writes 831885 # number of misc regfile writes -system.cpu.icache.replacements 979919 # number of replacements -system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use -system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242401590 # The number of ROB reads +system.cpu.rob.rob_writes 202045449 # The number of ROB writes +system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307579 # Number of Instructions Simulated +system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated +system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550352195 # number of integer regfile reads +system.cpu.int_regfile_writes 88467764 # number of integer regfile writes +system.cpu.fp_regfile_reads 8269 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.misc_regfile_writes 831890 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4420 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -942,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21011164 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1118,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 93139ea5d..434326c81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,180 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102937 # Number of seconds simulated -sim_ticks 1102937390000 # Number of ticks simulated -final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102950 # Number of seconds simulated +sim_ticks 1102950399000 # Number of ticks simulated +final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67484 # Simulator instruction rate (inst/s) -host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208579190 # Simulator tick rate (ticks/s) -host_mem_usage 412736 # Number of bytes of host memory used -host_seconds 912.59 # Real time elapsed on the host -sim_insts 61585042 # Number of instructions simulated -sim_ops 79274675 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 57810 # Simulator instruction rate (inst/s) +host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1035290197 # Simulator tick rate (ticks/s) +host_mem_usage 414988 # Number of bytes of host memory used +host_seconds 1065.35 # Real time elapsed on the host +sim_insts 61588287 # Number of instructions simulated +sim_ops 79281553 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory -system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory +system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257788 # Total number of read requests seen -system.physmem.writeReqs 823390 # Total number of write requests seen -system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400498432 # Total number of bytes read from memory -system.physmem.bytesWritten 52696960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257953 # Total number of read requests seen +system.physmem.writeReqs 823537 # Total number of write requests seen +system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508992 # Total number of bytes read from memory +system.physmem.bytesWritten 52706368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102936257500 # Total gap between requests +system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102949217500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162835 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2999773 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66554 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see +system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66701 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -187,292 +160,322 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests -system.physmem.totBusLat 31288540000 # Total cycles spent in databus access -system.physmem.totBankLat 8531820000 # Total cycles spent in bank access -system.physmem.avgQLat 31828.06 # Average queueing delay per request -system.physmem.avgBankLat 1363.41 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see +system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests +system.physmem.totBusLat 31289160000 # Total cycles spent in databus access +system.physmem.totBankLat 8530335000 # Total cycles spent in bank access +system.physmem.avgQLat 31830.81 # Average queueing delay per request +system.physmem.avgBankLat 1363.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38191.47 # Average memory access latency -system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 6213872 # Number of row buffer hits during reads -system.physmem.writeRowHits 799892 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.98 # Average write queue length over time +system.physmem.readRowHits 6213974 # Number of row buffer hits during reads +system.physmem.writeRowHits 800028 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155756.04 # Average gap between requests -system.l2c.replacements 72539 # number of replacements -system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use -system.l2c.total_refs 1841179 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. +system.physmem.avgGap 155751.01 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72704 # number of replacements +system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use +system.l2c.total_refs 1840692 # Total number of references to valid blocks. +system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits -system.l2c.Writeback_hits::total 581178 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061165 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998436 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits +system.cpu0.branchPred.lookups 6001263 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8902974 # DTB read hits -system.cpu0.dtb.read_misses 28685 # DTB read misses -system.cpu0.dtb.write_hits 5134917 # DTB write hits -system.cpu0.dtb.write_misses 5599 # DTB write misses +system.cpu0.dtb.read_hits 8907872 # DTB read hits +system.cpu0.dtb.read_misses 28815 # DTB read misses +system.cpu0.dtb.write_hits 5138143 # DTB write hits +system.cpu0.dtb.write_misses 5606 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8931659 # DTB read accesses -system.cpu0.dtb.write_accesses 5140516 # DTB write accesses +system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936687 # DTB read accesses +system.cpu0.dtb.write_accesses 5143749 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14037891 # DTB hits -system.cpu0.dtb.misses 34284 # DTB misses -system.cpu0.dtb.accesses 14072175 # DTB accesses -system.cpu0.itb.inst_hits 4215172 # ITB inst hits -system.cpu0.itb.inst_misses 5141 # ITB inst misses +system.cpu0.dtb.hits 14046015 # DTB hits +system.cpu0.dtb.misses 34421 # DTB misses +system.cpu0.dtb.accesses 14080436 # DTB accesses +system.cpu0.itb.inst_hits 4220167 # ITB inst hits +system.cpu0.itb.inst_misses 5223 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,148 +718,148 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses -system.cpu0.itb.hits 4215172 # DTB hits -system.cpu0.itb.misses 5141 # DTB misses -system.cpu0.itb.accesses 4220313 # DTB accesses -system.cpu0.numCycles 67779631 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses +system.cpu0.itb.hits 4220167 # DTB hits +system.cpu0.itb.misses 5223 # DTB misses +system.cpu0.itb.accesses 4225390 # DTB accesses +system.cpu0.numCycles 67827032 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -872,361 +887,361 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued -system.cpu0.iq.rate 0.549060 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued +system.cpu0.iq.rate 0.549010 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118422 # number of nop insts executed -system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852888 # Number of branches executed -system.cpu0.iew.exec_stores 5394475 # Number of stores executed -system.cpu0.iew.exec_rate 0.543552 # Inst execution rate -system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18273947 # num instructions producing a value -system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value +system.cpu0.iew.exec_nop 118689 # number of nop insts executed +system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4854206 # Number of branches executed +system.cpu0.iew.exec_stores 5397839 # Number of stores executed +system.cpu0.iew.exec_rate 0.543462 # Inst execution rate +system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18281082 # num instructions producing a value +system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670531 # Number of instructions committed -system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23679748 # Number of instructions committed +system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418468 # Number of memory references committed -system.cpu0.commit.loads 6271892 # Number of loads committed -system.cpu0.commit.membars 229609 # Number of memory barriers committed -system.cpu0.commit.branches 4243643 # Number of branches committed +system.cpu0.commit.refs 11426897 # Number of memory references committed +system.cpu0.commit.loads 6276420 # Number of loads committed +system.cpu0.commit.membars 229667 # Number of memory barriers committed +system.cpu0.commit.branches 4245051 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489165 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489354 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75500320 # The number of ROB reads -system.cpu0.rob.rob_writes 75691570 # The number of ROB writes -system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589789 # Number of Instructions Simulated -system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated -system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads -system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads +system.cpu0.rob.rob_reads 75566033 # The number of ROB reads +system.cpu0.rob.rob_writes 75750322 # The number of ROB writes +system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23599006 # Number of Instructions Simulated +system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated +system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads +system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes -system.cpu0.icache.replacements 392135 # number of replacements -system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use -system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes +system.cpu0.icache.replacements 392871 # number of replacements +system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use +system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits -system.cpu0.icache.overall_hits::total 3790159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses -system.cpu0.icache.overall_misses::total 423214 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits +system.cpu0.icache.overall_hits::total 3794104 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses +system.cpu0.icache.overall_misses::total 424196 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276137 # number of replacements -system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits -system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses -system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 276008 # number of replacements +system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits +system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks -system.cpu0.dcache.writebacks::total 256527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks +system.cpu0.dcache.writebacks::total 256612 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9086614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits +system.cpu1.branchPred.lookups 9071093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42908069 # DTB read hits -system.cpu1.dtb.read_misses 37093 # DTB read misses -system.cpu1.dtb.write_hits 6828111 # DTB write hits -system.cpu1.dtb.write_misses 10566 # DTB write misses +system.cpu1.dtb.read_hits 42899284 # DTB read hits +system.cpu1.dtb.read_misses 36667 # DTB read misses +system.cpu1.dtb.write_hits 6823776 # DTB write hits +system.cpu1.dtb.write_misses 10740 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42945162 # DTB read accesses -system.cpu1.dtb.write_accesses 6838677 # DTB write accesses +system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42935951 # DTB read accesses +system.cpu1.dtb.write_accesses 6834516 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49736180 # DTB hits -system.cpu1.dtb.misses 47659 # DTB misses -system.cpu1.dtb.accesses 49783839 # DTB accesses -system.cpu1.itb.inst_hits 8400139 # ITB inst hits -system.cpu1.itb.inst_misses 5511 # ITB inst misses +system.cpu1.dtb.hits 49723060 # DTB hits +system.cpu1.dtb.misses 47407 # DTB misses +system.cpu1.dtb.accesses 49770467 # DTB accesses +system.cpu1.itb.inst_hits 8396614 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses -system.cpu1.itb.hits 8400139 # DTB hits -system.cpu1.itb.misses 5511 # DTB misses -system.cpu1.itb.accesses 8405650 # DTB accesses -system.cpu1.numCycles 408778710 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses +system.cpu1.itb.hits 8396614 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8402110 # DTB accesses +system.cpu1.numCycles 408759365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,399 +1424,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued -system.cpu1.iq.rate 0.218115 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued +system.cpu1.iq.rate 0.218037 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104517 # number of nop insts executed -system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7007502 # Number of branches executed -system.cpu1.iew.exec_stores 7113991 # Number of stores executed -system.cpu1.iew.exec_rate 0.212186 # Inst execution rate -system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29917161 # num instructions producing a value -system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value +system.cpu1.iew.exec_nop 104622 # number of nop insts executed +system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7000416 # Number of branches executed +system.cpu1.iew.exec_stores 7109526 # Number of stores executed +system.cpu1.iew.exec_rate 0.212092 # Inst execution rate +system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29911901 # num instructions producing a value +system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38064892 # Number of instructions committed -system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058920 # Number of instructions committed +system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595277 # Number of memory references committed -system.cpu1.commit.loads 9755144 # Number of loads committed -system.cpu1.commit.membars 190149 # Number of memory barriers committed -system.cpu1.commit.branches 5967637 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534638 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16590474 # Number of memory references committed +system.cpu1.commit.loads 9752596 # Number of loads committed +system.cpu1.commit.membars 190088 # Number of memory barriers committed +system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534484 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 173015978 # The number of ROB reads -system.cpu1.rob.rob_writes 131360292 # The number of ROB writes -system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995253 # Number of Instructions Simulated -system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated -system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads -system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes -system.cpu1.icache.replacements 597992 # number of replacements -system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use -system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits -system.cpu1.icache.overall_hits::total 7754983 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses -system.cpu1.icache.overall_misses::total 643188 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked +system.cpu1.rob.rob_reads 172926580 # The number of ROB reads +system.cpu1.rob.rob_writes 131236338 # The number of ROB writes +system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37989281 # Number of Instructions Simulated +system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated +system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads +system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes +system.cpu1.icache.replacements 596801 # number of replacements +system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use +system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits +system.cpu1.icache.overall_hits::total 7752714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses +system.cpu1.icache.overall_misses::total 641884 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # 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mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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number of replacements +system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks -system.cpu1.dcache.writebacks::total 324651 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks +system.cpu1.dcache.writebacks::total 324455 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1823,18 +1834,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5e631440d..21b68a213 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,153 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533148 # Number of seconds simulated -sim_ticks 2533147650000 # Number of ticks simulated -final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533144 # Number of seconds simulated +sim_ticks 2533143504000 # Number of ticks simulated +final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66149 # Simulator instruction rate (inst/s) -host_op_rate 85115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2778505291 # Simulator tick rate (ticks/s) -host_mem_usage 406592 # Number of bytes of host memory used -host_seconds 911.69 # Real time elapsed on the host -sim_insts 60307315 # Number of instructions simulated -sim_ops 77598799 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 80573 # Simulator instruction rate (inst/s) +host_op_rate 103675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3384348477 # Simulator tick rate (ticks/s) +host_mem_usage 408856 # Number of bytes of host memory used +host_seconds 748.49 # Real time elapsed on the host +sim_insts 60307579 # Number of instructions simulated +sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096808 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195712 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096820 # Total number of read requests seen +system.physmem.writeReqs 813121 # Total number of write requests seen +system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196480 # Total number of bytes read from memory +system.physmem.bytesWritten 52039744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533146526000 # Total gap between requests +system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533142364000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154564 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2990994 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59094 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59103 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -164,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see @@ -181,31 +155,30 @@ system.physmem.wrQLenPdf::12 35353 # Wh system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests -system.physmem.totBusLat 75482565000 # Total cycles spent in databus access -system.physmem.totBankLat 16909805000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.29 # Average queueing delay per request -system.physmem.avgBankLat 1120.11 # Average bank access latency per request +system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482965000 # Total cycles spent in databus access +system.physmem.totBankLat 16912788750 # Total cycles spent in bank access +system.physmem.avgQLat 26048.65 # Average queueing delay per request +system.physmem.avgBankLat 1120.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgMemAccLat 32168.96 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -213,50 +186,62 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.48 # Average write queue length over time -system.physmem.readRowHits 15020221 # Number of row buffer hits during reads -system.physmem.writeRowHits 793131 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.55 # Average write queue length over time +system.physmem.readRowHits 15020273 # Number of row buffer hits during reads +system.physmem.writeRowHits 793117 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159218.06 # Average gap between requests +system.physmem.avgGap 159217.58 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14676489 # Number of BP lookups -system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits +system.cpu.branchPred.lookups 14678084 # Number of BP lookups +system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51394402 # DTB read hits -system.cpu.dtb.read_misses 64202 # DTB read misses -system.cpu.dtb.write_hits 11700782 # DTB write hits -system.cpu.dtb.write_misses 15842 # DTB write misses +system.cpu.dtb.read_hits 51401633 # DTB read hits +system.cpu.dtb.read_misses 64365 # DTB read misses +system.cpu.dtb.write_hits 11702282 # DTB write hits +system.cpu.dtb.write_misses 15903 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3559 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51458604 # DTB read accesses -system.cpu.dtb.write_accesses 11716624 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465998 # DTB read accesses +system.cpu.dtb.write_accesses 11718185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63095184 # DTB hits -system.cpu.dtb.misses 80044 # DTB misses -system.cpu.dtb.accesses 63175228 # DTB accesses -system.cpu.itb.inst_hits 12330326 # ITB inst hits -system.cpu.itb.inst_misses 11351 # ITB inst misses +system.cpu.dtb.hits 63103915 # DTB hits +system.cpu.dtb.misses 80268 # DTB misses +system.cpu.dtb.accesses 63184183 # DTB accesses +system.cpu.itb.inst_hits 12333169 # ITB inst hits +system.cpu.itb.inst_misses 11311 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -265,114 +250,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2477 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12341677 # ITB inst accesses -system.cpu.itb.hits 12330326 # DTB hits -system.cpu.itb.misses 11351 # DTB misses -system.cpu.itb.accesses 12341677 # DTB accesses -system.cpu.numCycles 471833351 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12344480 # ITB inst accesses +system.cpu.itb.hits 12333169 # DTB hits +system.cpu.itb.misses 11311 # DTB misses +system.cpu.itb.accesses 12344480 # DTB accesses +system.cpu.numCycles 471839315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available @@ -400,13 +385,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -419,11 +404,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued @@ -432,351 +417,351 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued -system.cpu.iq.rate 0.263486 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued +system.cpu.iq.rate 0.263513 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220665 # number of nop insts executed -system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561887 # Number of branches executed -system.cpu.iew.exec_stores 12212575 # Number of stores executed -system.cpu.iew.exec_rate 0.257603 # Inst execution rate -system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47219839 # num instructions producing a value -system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value +system.cpu.iew.exec_nop 220929 # number of nop insts executed +system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed +system.cpu.iew.exec_branches 11562998 # Number of branches executed +system.cpu.iew.exec_stores 12213915 # Number of stores executed +system.cpu.iew.exec_rate 0.257621 # Inst execution rate +system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47225460 # num instructions producing a value +system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457696 # Number of instructions committed -system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457960 # Number of instructions committed +system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386450 # Number of memory references committed -system.cpu.commit.loads 15654440 # Number of loads committed -system.cpu.commit.membars 403595 # Number of memory barriers committed -system.cpu.commit.branches 9961299 # Number of branches committed +system.cpu.commit.refs 27386605 # Number of memory references committed +system.cpu.commit.loads 15654525 # Number of loads committed +system.cpu.commit.membars 403599 # Number of memory barriers committed +system.cpu.commit.branches 9961316 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. -system.cpu.commit.function_calls 991256 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. +system.cpu.commit.function_calls 991257 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242385214 # The number of ROB reads -system.cpu.rob.rob_writes 202032533 # The number of ROB writes -system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307315 # Number of Instructions Simulated -system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated -system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550300281 # number of integer regfile reads -system.cpu.int_regfile_writes 88460223 # number of integer regfile writes -system.cpu.fp_regfile_reads 8330 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads -system.cpu.misc_regfile_writes 831885 # number of misc regfile writes -system.cpu.icache.replacements 979919 # number of replacements -system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use -system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242401590 # The number of ROB reads +system.cpu.rob.rob_writes 202045449 # The number of ROB writes +system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307579 # Number of Instructions Simulated +system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated +system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550352189 # number of integer regfile reads +system.cpu.int_regfile_writes 88467762 # number of integer regfile writes +system.cpu.fp_regfile_reads 8269 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.misc_regfile_writes 831890 # number of misc regfile writes +system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use +system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits -system.cpu.icache.overall_hits::total 11266751 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses -system.cpu.icache.overall_misses::total 1059755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits +system.cpu.icache.overall_hits::total 11270072 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses +system.cpu.icache.overall_misses::total 1059286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -897,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643325 # number of replacements +system.cpu.dcache.replacements 643539 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits -system.cpu.dcache.overall_hits::total 21011164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses -system.cpu.dcache.overall_misses::total 3699958 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits +system.cpu.dcache.overall_hits::total 21015683 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses +system.cpu.dcache.overall_misses::total 3700421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks -system.cpu.dcache.writebacks::total 607515 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks +system.cpu.dcache.writebacks::total 607840 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index e69de29bb..cb0094499 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -0,0 +1,1539 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.401342 # Number of seconds simulated +sim_ticks 2401342466000 # Number of ticks simulated +final_tick 2401342466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 244723 # Simulator instruction rate (inst/s) +host_op_rate 314293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9740625246 # Simulator tick rate (ticks/s) +host_mem_usage 401684 # Number of bytes of host memory used +host_seconds 246.53 # Real time elapsed on the host +sim_insts 60331304 # Number of instructions simulated +sim_ops 77482270 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 501920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7085968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 678144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 178368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1313020 # Number of bytes read from this memory +system.physmem.bytes_read::total 124662764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 765600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3747328 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6763144 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10596 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20530 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58552 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2950836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 546786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 551965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3571700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 74278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1098750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54730181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12618170 # Total number of read requests seen +system.physmem.writeReqs 398699 # Total number of write requests seen +system.physmem.cpureqs 55066 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807562880 # Total number of bytes read from memory +system.physmem.bytesWritten 25516736 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102918908 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2643116 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788875 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788649 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788136 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788749 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24766 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24890 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24969 # 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Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 17472 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 816053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see +system.physmem.totQLat 277225501500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353051170250 # Sum of mem lat for all requests +system.physmem.totBusLat 63090845000 # Total cycles spent in databus access +system.physmem.totBankLat 12734823750 # Total cycles spent in bank access +system.physmem.avgQLat 21970.34 # Average queueing delay per request +system.physmem.avgBankLat 1009.24 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27979.59 # Average memory access latency +system.physmem.avgRdBW 336.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.71 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 0.39 # Average write queue length over time +system.physmem.readRowHits 12563520 # Number of row buffer hits during reads +system.physmem.writeRowHits 392353 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes +system.physmem.avgGap 184399.74 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 63278 # number of replacements +system.l2c.tagsinuse 50361.338948 # Cycle average of tags in use +system.l2c.total_refs 1750374 # Total number of references to valid blocks. +system.l2c.sampled_refs 128673 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.603273 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374434052500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36832.479753 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5142.503015 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3774.307963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 800.237683 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.699491 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 9.796874 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.004225 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1464.578885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.737598 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562019 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078468 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.012211 # 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number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 66093 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4298 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284840 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 138220 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1292045 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597703 # number of Writeback hits +system.l2c.Writeback_hits::total 597703 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60564 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017847 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018183 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006008 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992233 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985830 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.506308 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.331266 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.356087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.114242 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45138.593672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48491.855078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48464.037248 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.162427 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.928620 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32454.030209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40493.172075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37739.190459 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 8066281 # DTB read hits +system.cpu0.dtb.read_misses 6214 # DTB read misses +system.cpu0.dtb.write_hits 6622863 # DTB write hits +system.cpu0.dtb.write_misses 2042 # DTB write misses +system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8072495 # DTB read accesses +system.cpu0.dtb.write_accesses 6624905 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 14689144 # DTB hits +system.cpu0.dtb.misses 8256 # DTB misses +system.cpu0.dtb.accesses 14697400 # DTB accesses +system.cpu0.itb.inst_hits 32699803 # ITB inst hits +system.cpu0.itb.inst_misses 3478 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 32703281 # ITB inst accesses +system.cpu0.itb.hits 32699803 # DTB hits +system.cpu0.itb.misses 3478 # DTB misses +system.cpu0.itb.accesses 32703281 # DTB accesses +system.cpu0.numCycles 113984620 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 32203473 # Number of instructions committed +system.cpu0.committedOps 42387015 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37536520 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses +system.cpu0.num_func_calls 1187911 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4237941 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37536520 # number of integer instructions +system.cpu0.num_fp_insts 5136 # number of float instructions +system.cpu0.num_int_register_reads 191230728 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39632670 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu0.num_mem_refs 15352482 # number of memory refs +system.cpu0.num_load_insts 8433499 # Number of load instructions +system.cpu0.num_store_insts 6918983 # Number of store instructions +system.cpu0.num_idle_cycles 13416591638.099268 # Number of idle cycles +system.cpu0.num_busy_cycles -13302607018.099268 # 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number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32232511 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8306544 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3748671 # number of overall hits +system.cpu0.icache.overall_hits::total 44287726 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 469964 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 134928 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311926 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 469964 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 134928 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311926 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 469964 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 134928 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311926 # number of overall misses +system.cpu0.icache.overall_misses::total 916818 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820105000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4164885486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5984990486 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1820105000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4164885486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5984990486 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1820105000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4164885486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5984990486 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32702475 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8441472 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4060597 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45204544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32702475 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8441472 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4060597 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45204544 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32702475 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8441472 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4060597 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45204544 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014371 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015984 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076818 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020282 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014371 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015984 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076818 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020282 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014371 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015984 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076818 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020282 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.453635 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13352.158800 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6528.002816 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6528.002816 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6528.002816 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3429 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.485577 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23868 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23868 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23868 # 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number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95267 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190403 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285670 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782830500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1785427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568258000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 670558000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1431904990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102462990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19087500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40642000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59729500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1453388500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3217332490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4670720990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1453388500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3217332490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4670720990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27581235500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28989086000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56570321500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280021500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14116548125 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396569625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861257000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43105634125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71966891125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028942 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021517 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019471 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008098 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047893 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011882 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011882 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.305400 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12998.161765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.694244 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22582.272513 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26995.173538 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25411.399857 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.935503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11722.526680 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11513.010794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 2177390 # DTB read hits +system.cpu1.dtb.read_misses 2104 # DTB read misses +system.cpu1.dtb.write_hits 1466734 # DTB write hits +system.cpu1.dtb.write_misses 391 # DTB write misses +system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2179494 # DTB read accesses +system.cpu1.dtb.write_accesses 1467125 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 3644124 # DTB hits +system.cpu1.dtb.misses 2495 # DTB misses +system.cpu1.dtb.accesses 3646619 # DTB accesses +system.cpu1.itb.inst_hits 8441472 # ITB inst hits +system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 829 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 8442603 # ITB inst accesses +system.cpu1.itb.hits 8441472 # DTB hits +system.cpu1.itb.misses 1131 # DTB misses +system.cpu1.itb.accesses 8442603 # DTB accesses +system.cpu1.numCycles 574629535 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 8231527 # Number of instructions committed +system.cpu1.committedOps 10483049 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9384758 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses +system.cpu1.num_func_calls 317840 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1148947 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9384758 # number of integer instructions +system.cpu1.num_fp_insts 1998 # number of float instructions +system.cpu1.num_int_register_reads 54113079 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10168310 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written +system.cpu1.num_mem_refs 3817736 # number of memory refs +system.cpu1.num_load_insts 2273251 # Number of load instructions +system.cpu1.num_store_insts 1544485 # Number of store instructions +system.cpu1.num_idle_cycles 533738024.963358 # Number of idle cycles +system.cpu1.num_busy_cycles 40891510.036642 # Number of busy cycles +system.cpu1.not_idle_fraction 0.071162 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.928838 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.branchPred.lookups 4718167 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3836083 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222496 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3137475 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2530778 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 80.662890 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410861 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21436 # Number of incorrect RAS predictions. +system.cpu2.dtb.inst_hits 0 # ITB inst hits +system.cpu2.dtb.inst_misses 0 # ITB inst misses +system.cpu2.dtb.read_hits 10866526 # DTB read hits +system.cpu2.dtb.read_misses 22717 # DTB read misses +system.cpu2.dtb.write_hits 3271799 # DTB write hits +system.cpu2.dtb.write_misses 5746 # DTB write misses +system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 908 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 162 # Number of TLB faults due to prefetch +system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dtb.perms_faults 438 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10889243 # DTB read accesses +system.cpu2.dtb.write_accesses 3277545 # DTB write accesses +system.cpu2.dtb.inst_accesses 0 # ITB inst accesses +system.cpu2.dtb.hits 14138325 # DTB hits +system.cpu2.dtb.misses 28463 # DTB misses +system.cpu2.dtb.accesses 14166788 # DTB accesses +system.cpu2.itb.inst_hits 4062010 # ITB inst hits +system.cpu2.itb.inst_misses 4544 # ITB inst misses +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.itb.perms_faults 990 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.inst_accesses 4066554 # ITB inst accesses +system.cpu2.itb.hits 4062010 # DTB hits +system.cpu2.itb.misses 4544 # DTB misses +system.cpu2.itb.accesses 4066554 # DTB accesses +system.cpu2.numCycles 88259424 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 9446644 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32376030 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4718167 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941639 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6823560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1815993 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51150 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19328654 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 980 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33196 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57154 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4060600 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 310025 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2087 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36989038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30170666 81.57% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382975 1.04% 82.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509806 1.38% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812610 2.20% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 650446 1.76% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344174 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1009971 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 238143 0.64% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2870247 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 36989038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053458 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.366828 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10060365 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19264823 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6175765 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293250 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1193736 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 611236 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 54016 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36687044 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 183513 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1193736 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10634106 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6560148 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11167231 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5875066 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1557700 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34442910 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2428 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 416233 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 878364 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 86 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36942900 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157448988 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157420907 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 28081 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25732227 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11210672 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231165 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207502 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3338949 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6517311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3844285 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 533485 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 782358 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31699556 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 512260 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34239526 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54408 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7411685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19905699 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155950 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36989038 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925667 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.579936 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24424083 66.03% 66.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3914413 10.58% 76.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2344925 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1979398 5.35% 88.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782245 7.52% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 897303 2.43% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 479565 1.30% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 132664 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34442 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36989038 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16741 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1406719 91.75% 92.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109821 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 61341 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19346638 56.50% 56.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25970 0.08% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11366450 33.20% 89.96% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3438720 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 34239526 # Type of FU issued +system.cpu2.iq.rate 0.387942 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1533281 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044781 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107077115 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39628603 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27373114 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7012 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3867 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3171 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35707743 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3723 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207144 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 1578939 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1781 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9287 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 581487 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 5366547 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352710 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 1193736 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4865575 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91265 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32289220 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60072 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6517311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3844285 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 370110 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31382 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2364 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9287 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105801 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88656 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194457 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33253955 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11078248 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 985571 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 77404 # number of nop insts executed +system.cpu2.iew.exec_refs 14484069 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3693959 # Number of branches executed +system.cpu2.iew.exec_stores 3405821 # Number of stores executed +system.cpu2.iew.exec_rate 0.376775 # Inst execution rate +system.cpu2.iew.wb_sent 32835376 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27376285 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15639881 # num instructions producing a value +system.cpu2.iew.wb_consumers 28443914 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 0.310180 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549850 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 7353370 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356310 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169242 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35795177 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.689030 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.716377 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161144 75.88% 75.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4182796 11.69% 87.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1257934 3.51% 91.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 650072 1.82% 92.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 572405 1.60% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318145 0.89% 95.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 398611 1.11% 96.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 289517 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 964553 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 35795177 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19948032 # Number of instructions committed +system.cpu2.commit.committedOps 24663934 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 8201170 # Number of memory references committed +system.cpu2.commit.loads 4938372 # Number of loads committed +system.cpu2.commit.membars 94284 # Number of memory barriers committed +system.cpu2.commit.branches 3159330 # Number of branches committed +system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21896584 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294432 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 964553 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 66322359 # The number of ROB reads +system.cpu2.rob.rob_writes 65269716 # The number of ROB writes +system.cpu2.timesIdled 360610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51270386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567282777 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19896304 # Number of Instructions Simulated +system.cpu2.committedOps 24612206 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19896304 # Number of Instructions Simulated +system.cpu2.cpi 4.435971 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.435971 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225430 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225430 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153619479 # number of integer regfile reads +system.cpu2.int_regfile_writes 29201382 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22411 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20842 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9012056 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240747 # number of misc regfile writes +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs nan # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981147786186 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981147786186 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1af17ec8e..73a40b4c9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,162 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542296 # Number of seconds simulated -sim_ticks 2542295570500 # Number of ticks simulated -final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541289 # Number of seconds simulated +sim_ticks 2541288973500 # Number of ticks simulated +final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70655 # Simulator instruction rate (inst/s) -host_op_rate 90914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2978397497 # Simulator tick rate (ticks/s) -host_mem_usage 409668 # Number of bytes of host memory used -host_seconds 853.58 # Real time elapsed on the host -sim_insts 60309877 # Number of instructions simulated -sim_ops 77602149 # Number of ops (including micro ops) simulated +host_inst_rate 61532 # Simulator instruction rate (inst/s) +host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2592785663 # Simulator tick rate (ticks/s) +host_mem_usage 411940 # Number of bytes of host memory used +host_seconds 980.14 # Real time elapsed on the host +sim_insts 60309889 # Number of instructions simulated +sim_ops 77602313 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory -system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory -system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293509 # Total number of read requests seen -system.physmem.writeReqs 813201 # Total number of write requests seen -system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978784576 # Total number of bytes read from memory -system.physmem.bytesWritten 52044864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293479 # Total number of read requests seen +system.physmem.writeReqs 813168 # Total number of write requests seen +system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782656 # Total number of bytes read from memory +system.physmem.bytesWritten 52042752 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry -system.physmem.totGap 2542294418500 # Total gap between requests +system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287786000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154650 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2610507 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59173 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 59140 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests -system.physmem.totBusLat 76467475000 # Total cycles spent in databus access -system.physmem.totBankLat 16700378750 # Total cycles spent in bank access -system.physmem.avgQLat 22678.97 # Average queueing delay per request -system.physmem.avgBankLat 1091.99 # Average bank access latency per request +system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see +system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467345000 # Total cycles spent in databus access +system.physmem.totBankLat 16707116250 # Total cycles spent in bank access +system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28770.96 # Average memory access latency -system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28763.65 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -637,38 +622,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7620138 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits +system.cpu0.branchPred.lookups 7614306 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26058653 # DTB read hits -system.cpu0.dtb.read_misses 40101 # DTB read misses -system.cpu0.dtb.write_hits 5895373 # DTB write hits -system.cpu0.dtb.write_misses 9447 # DTB write misses +system.cpu0.dtb.read_hits 26054511 # DTB read hits +system.cpu0.dtb.read_misses 40169 # DTB read misses +system.cpu0.dtb.write_hits 5887052 # DTB write hits +system.cpu0.dtb.write_misses 9355 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26098754 # DTB read accesses -system.cpu0.dtb.write_accesses 5904820 # DTB write accesses +system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094680 # DTB read accesses +system.cpu0.dtb.write_accesses 5896407 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31954026 # DTB hits -system.cpu0.dtb.misses 49548 # DTB misses -system.cpu0.dtb.accesses 32003574 # DTB accesses -system.cpu0.itb.inst_hits 6112115 # ITB inst hits -system.cpu0.itb.inst_misses 7637 # ITB inst misses +system.cpu0.dtb.hits 31941563 # DTB hits +system.cpu0.dtb.misses 49524 # DTB misses +system.cpu0.dtb.accesses 31991087 # DTB accesses +system.cpu0.itb.inst_hits 6108612 # ITB inst hits +system.cpu0.itb.inst_misses 7590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -677,149 +662,149 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses -system.cpu0.itb.hits 6112115 # DTB hits -system.cpu0.itb.misses 7637 # DTB misses -system.cpu0.itb.accesses 6119752 # DTB accesses -system.cpu0.numCycles 239063312 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses +system.cpu0.itb.hits 6108612 # DTB hits +system.cpu0.itb.misses 7590 # DTB misses +system.cpu0.itb.accesses 6116202 # DTB accesses +system.cpu0.numCycles 239083473 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -832,485 +817,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued -system.cpu0.iq.rate 0.264347 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued +system.cpu0.iq.rate 0.264223 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116775 # number of nop insts executed -system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6028949 # Number of branches executed -system.cpu0.iew.exec_stores 6166881 # Number of stores executed -system.cpu0.iew.exec_rate 0.259451 # Inst execution rate -system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24314220 # num instructions producing a value -system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value +system.cpu0.iew.exec_nop 117384 # number of nop insts executed +system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6026978 # Number of branches executed +system.cpu0.iew.exec_stores 6158391 # Number of stores executed +system.cpu0.iew.exec_rate 0.259325 # Inst execution rate +system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24307807 # num instructions producing a value +system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31284581 # Number of instructions committed -system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31268406 # Number of instructions committed +system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13971736 # Number of memory references committed -system.cpu0.commit.loads 8078750 # Number of loads committed -system.cpu0.commit.membars 212403 # Number of memory barriers committed -system.cpu0.commit.branches 5205711 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13961713 # Number of memory references committed +system.cpu0.commit.loads 8074725 # Number of loads committed +system.cpu0.commit.membars 212370 # Number of memory barriers committed +system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513958 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123805555 # The number of ROB reads -system.cpu0.rob.rob_writes 102335061 # The number of ROB writes -system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31205252 # Number of Instructions Simulated -system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated -system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.660996 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130531 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130531 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280760557 # number of integer regfile reads -system.cpu0.int_regfile_writes 45445732 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22770 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15502985 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430013 # number of misc regfile writes -system.cpu0.icache.replacements 984427 # number of replacements -system.cpu0.icache.tagsinuse 510.429233 # Cycle average of tags in use -system.cpu0.icache.total_refs 11039860 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984939 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.208674 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123750130 # The number of ROB reads +system.cpu0.rob.rob_writes 102252787 # The number of ROB writes +system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31189179 # Number of Instructions Simulated +system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated +system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads +system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes +system.cpu0.icache.replacements 984233 # number of replacements +system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.685952 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.743281 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696652 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.300280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996932 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5569328 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470532 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11039860 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5569328 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470532 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11039860 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5569328 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470532 # number of overall hits -system.cpu0.icache.overall_hits::total 11039860 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540556 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065207 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540556 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065207 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540556 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524651 # number of overall misses -system.cpu0.icache.overall_misses::total 1065207 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7319258495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971682996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14290941491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7319258495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6971682996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14290941491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7319258495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6971682996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14290941491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6109884 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995183 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12105067 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6109884 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995183 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12105067 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6109884 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995183 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12105067 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087997 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088472 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087997 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088472 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087997 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.116765 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4720 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # 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number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses +system.cpu0.icache.overall_misses::total 1065336 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 314 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 353 # 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number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40959 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39286 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80245 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499597 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485365 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984962 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 499597 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 485365 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984962 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 499597 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 485365 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11655300986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5972321992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5682978994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11655300986 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080959 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643954 # 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miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269093 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310622 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289658 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051437 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054518 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052929 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143514 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149950 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143514 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149950 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14845.692761 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15427.048074 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.927526 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37885.320653 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39319.924972 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38647.128005 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.253810 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14070.649772 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13788.186026 # average LoadLockedReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6814329436 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13682866427 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91958825500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90402409000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361234500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888911816 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1325,38 +1310,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7047379 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits +system.cpu1.branchPred.lookups 7038093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308350 # DTB read hits -system.cpu1.dtb.read_misses 36279 # DTB read misses -system.cpu1.dtb.write_hits 5820677 # DTB write hits -system.cpu1.dtb.write_misses 9386 # DTB write misses +system.cpu1.dtb.read_hits 25308103 # DTB read hits +system.cpu1.dtb.read_misses 36468 # DTB read misses +system.cpu1.dtb.write_hits 5825949 # DTB write hits +system.cpu1.dtb.write_misses 9352 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344629 # DTB read accesses -system.cpu1.dtb.write_accesses 5830063 # DTB write accesses +system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344571 # DTB read accesses +system.cpu1.dtb.write_accesses 5835301 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31129027 # DTB hits -system.cpu1.dtb.misses 45665 # DTB misses -system.cpu1.dtb.accesses 31174692 # DTB accesses -system.cpu1.itb.inst_hits 5997294 # ITB inst hits -system.cpu1.itb.inst_misses 6928 # ITB inst misses +system.cpu1.dtb.hits 31134052 # DTB hits +system.cpu1.dtb.misses 45820 # DTB misses +system.cpu1.dtb.accesses 31179872 # DTB accesses +system.cpu1.itb.inst_hits 5997509 # ITB inst hits +system.cpu1.itb.inst_misses 6989 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1365,284 +1350,284 @@ system.cpu1.itb.flush_tlb 254 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses -system.cpu1.itb.hits 5997294 # DTB hits -system.cpu1.itb.misses 6928 # DTB misses -system.cpu1.itb.accesses 6004222 # DTB accesses -system.cpu1.numCycles 234192897 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses +system.cpu1.itb.hits 5997509 # DTB hits +system.cpu1.itb.misses 6989 # DTB misses +system.cpu1.itb.accesses 6004498 # DTB accesses +system.cpu1.numCycles 234155519 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued -system.cpu1.iq.rate 0.259674 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.rate 0.259727 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105579 # number of nop insts executed -system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5530994 # Number of branches executed -system.cpu1.iew.exec_stores 6061366 # Number of stores executed -system.cpu1.iew.exec_rate 0.253868 # Inst execution rate -system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22753184 # num instructions producing a value -system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value +system.cpu1.iew.exec_nop 105951 # number of nop insts executed +system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5524822 # Number of branches executed +system.cpu1.iew.exec_stores 6066892 # Number of stores executed +system.cpu1.iew.exec_rate 0.253883 # Inst execution rate +system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22765083 # num instructions producing a value +system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29175677 # Number of instructions committed -system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29191864 # Number of instructions committed +system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13416080 # Number of memory references committed -system.cpu1.commit.loads 7576491 # Number of loads committed -system.cpu1.commit.membars 191234 # Number of memory barriers committed -system.cpu1.commit.branches 4755917 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477112 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13426228 # Number of memory references committed +system.cpu1.commit.loads 7580614 # Number of loads committed +system.cpu1.commit.membars 191280 # Number of memory barriers committed +system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477362 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119309924 # The number of ROB reads -system.cpu1.rob.rob_writes 98406667 # The number of ROB writes -system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29104625 # Number of Instructions Simulated -system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated -system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads -system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes +system.cpu1.rob.rob_reads 119292034 # The number of ROB reads +system.cpu1.rob.rob_writes 98387822 # The number of ROB writes +system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29120710 # Number of Instructions Simulated +system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated +system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads +system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1657,17 +1642,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cc1497460..e925b6c9c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,63 +4,63 @@ sim_seconds 2.608779 # Nu sim_ticks 2608778789000 # Number of ticks simulated final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 458042 # Simulator instruction rate (inst/s) -host_op_rate 582855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19847185908 # Simulator tick rate (ticks/s) -host_mem_usage 403628 # Number of bytes of host memory used -host_seconds 131.44 # Real time elapsed on the host +host_inst_rate 616577 # Simulator instruction rate (inst/s) +host_op_rate 784589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26716567066 # Simulator tick rate (ticks/s) +host_mem_usage 403640 # Number of bytes of host memory used +host_seconds 97.65 # Real time elapsed on the host sim_insts 60206536 # Number of instructions simulated sim_ops 76612339 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4486348 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4557348 # Number of bytes read from this memory system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520260 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495880 # Number of bytes written to this memory system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70132 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71232 # Number of read requests responded to by this memory system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380065 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373970 # Number of write requests responded to by this memory system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1719712 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1746928 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 582748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 573402 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2302460 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2320330 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15494012 # Total number of read requests seen system.physmem.writeReqs 811397 # Total number of write requests seen @@ -113,42 +113,29 @@ system.physmem.readPktSize::3 15335424 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 151912 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754035 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57362 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754035 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 57362 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1116374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 959978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3651919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2754799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2759743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2734008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 61745 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 162677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8654 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -165,48 +152,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35286 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.totQLat 338360116500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 433225996500 # Sum of mem lat for all requests system.physmem.totBusLat 77469930000 # Total cycles spent in databus access -system.physmem.totBankLat 17396335000 # Total cycles spent in bank access -system.physmem.avgQLat 21836.98 # Average queueing delay per request -system.physmem.avgBankLat 1122.78 # Average bank access latency per request +system.physmem.totBankLat 17395950000 # Total cycles spent in bank access +system.physmem.avgQLat 21838.16 # Average queueing delay per request +system.physmem.avgBankLat 1122.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27959.76 # Average memory access latency +system.physmem.avgMemAccLat 27960.91 # Average memory access latency system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s @@ -215,8 +200,8 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.24 # Average write queue length over time -system.physmem.readRowHits 15419486 # Number of row buffer hits during reads -system.physmem.writeRowHits 793977 # Number of row buffer hits during writes +system.physmem.readRowHits 15419485 # Number of row buffer hits during reads +system.physmem.writeRowHits 793971 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes system.physmem.avgGap 159994.42 # Average gap between requests @@ -233,67 +218,67 @@ system.realview.nvmem.bw_inst_read::total 8 # I system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 61800 # number of replacements -system.l2c.tagsinuse 50918.253702 # Cycle average of tags in use -system.l2c.total_refs 1698591 # Total number of references to valid blocks. +system.l2c.tagsinuse 50918.274770 # Cycle average of tags in use +system.l2c.total_refs 1698590 # Total number of references to valid blocks. system.l2c.sampled_refs 127185 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.355278 # Average number of references to valid blocks. +system.l2c.avg_refs 13.355270 # Average number of references to valid blocks. system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37907.717848 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 37907.739724 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4327.115126 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3096.490855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2668.881351 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2918.047697 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4327.115083 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3097.452751 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2668.881349 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2917.085036 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.047249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.047263 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044526 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044511 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 10142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 10140 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 409497 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 409506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188271 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9561 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 434855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 182318 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 434846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182307 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241751 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits system.l2c.Writeback_hits::total 596435 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 57591 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56978 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 114569 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 10140 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 409497 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9560 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 409506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245862 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9561 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3405 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 434855 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239297 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356321 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10142 # number of overall hits +system.l2c.demand_hits::cpu1.inst 434846 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239285 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356320 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10140 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3715 # number of overall hits -system.l2c.overall_hits::cpu0.inst 409497 # number of overall hits -system.l2c.overall_hits::cpu0.data 245850 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9560 # number of overall hits +system.l2c.overall_hits::cpu0.inst 409506 # number of overall hits +system.l2c.overall_hits::cpu0.data 245862 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9561 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3405 # number of overall hits -system.l2c.overall_hits::cpu1.inst 434855 # number of overall hits -system.l2c.overall_hits::cpu1.data 239297 # number of overall hits -system.l2c.overall_hits::total 1356321 # number of overall hits +system.l2c.overall_hits::cpu1.inst 434846 # number of overall hits +system.l2c.overall_hits::cpu1.data 239285 # number of overall hits +system.l2c.overall_hits::total 1356320 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 6138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5512 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5513 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 4467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4338 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4337 # number of ReadReq misses system.l2c.ReadReq_misses::total 20458 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1394 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses @@ -304,133 +289,133 @@ system.l2c.ReadExReq_misses::total 133098 # nu system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39501.680210 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43350.723311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40931.064034 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.401490 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.096830 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.105197 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33566.811232 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.988490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.312086 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.875094 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33558.476402 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33072.702655 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39294.499511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33108.767860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42596.701813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34148.044868 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34119.658535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -588,10 +573,10 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7507423 # DTB read hits +system.cpu0.dtb.read_hits 7507395 # DTB read hits system.cpu0.dtb.read_misses 6880 # DTB read misses -system.cpu0.dtb.write_hits 5552288 # DTB write hits -system.cpu0.dtb.write_misses 1844 # DTB write misses +system.cpu0.dtb.write_hits 5552217 # DTB write hits +system.cpu0.dtb.write_misses 1843 # DTB write misses system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID @@ -601,13 +586,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7514303 # DTB read accesses -system.cpu0.dtb.write_accesses 5554132 # DTB write accesses +system.cpu0.dtb.read_accesses 7514275 # DTB read accesses +system.cpu0.dtb.write_accesses 5554060 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13059711 # DTB hits -system.cpu0.dtb.misses 8724 # DTB misses -system.cpu0.dtb.accesses 13068435 # DTB accesses -system.cpu0.itb.inst_hits 30766737 # ITB inst hits +system.cpu0.dtb.hits 13059612 # DTB hits +system.cpu0.dtb.misses 8723 # DTB misses +system.cpu0.dtb.accesses 13068335 # DTB accesses +system.cpu0.itb.inst_hits 30766787 # ITB inst hits system.cpu0.itb.inst_misses 3610 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -624,30 +609,30 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30770347 # ITB inst accesses -system.cpu0.itb.hits 30766737 # DTB hits +system.cpu0.itb.inst_accesses 30770397 # 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number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4017319 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34424567 # number of integer instructions +system.cpu0.num_func_calls 1041305 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4017298 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34424496 # number of integer instructions system.cpu0.num_fp_insts 5276 # number of float instructions -system.cpu0.num_int_register_reads 197342497 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37147622 # number of times the integer registers were written +system.cpu0.num_int_register_reads 197342644 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37147872 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written -system.cpu0.num_mem_refs 13659512 # number of memory refs -system.cpu0.num_load_insts 7847120 # Number of load instructions -system.cpu0.num_store_insts 5812392 # Number of store instructions -system.cpu0.num_idle_cycles 3486759367.777020 # Number of idle cycles -system.cpu0.num_busy_cycles -933867325.777020 # Number of busy cycles +system.cpu0.num_mem_refs 13659420 # number of memory refs +system.cpu0.num_load_insts 7847088 # Number of load instructions +system.cpu0.num_store_insts 5812332 # Number of store instructions +system.cpu0.num_idle_cycles 3486764467.544441 # Number of idle cycles +system.cpu0.num_busy_cycles -933868699.544441 # Number of busy cycles system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -658,65 +643,65 @@ system.cpu0.icache.total_refs 60644038 # To system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 354.105005 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 156.872348 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.691611 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.306391 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 354.101290 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 156.876063 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.691604 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.306399 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998003 # 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number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30293632 # number of overall hits system.cpu0.icache.overall_hits::total 60644038 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 416372 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 440222 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 416381 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 440213 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856594 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 416372 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 440222 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 416381 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 440213 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856594 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 416372 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 440222 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 416381 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 440213 # number of overall misses system.cpu0.icache.overall_misses::total 856594 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5679878500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933784000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11613662500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5679878500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5933784000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11613662500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5679878500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5933784000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11613662500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766737 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733895 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5680035500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933793500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11613829000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5680035500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5933793500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11613829000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5680035500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5933793500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11613829000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766787 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733845 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61500632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30766737 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30733895 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 30766787 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30733845 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61500632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30766737 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30733895 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30766787 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30733845 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61500632 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013533 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014324 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014323 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013533 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014324 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014323 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013533 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014324 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014323 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.355567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.071923 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13557.954527 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13557.954527 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13557.954527 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.437770 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.369078 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13558.148901 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13558.148901 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.437770 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.369078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13558.148901 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,46 +710,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416372 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416381 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440213 # 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number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847134500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053340000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900474500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847134500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053340000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9900474500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847134500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053340000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9900474500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847273500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053367500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900641000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847273500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053367500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9900641000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847273500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053367500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9900641000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014323 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11557.954527 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11558.148901 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.437770 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.369078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11558.148901 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -776,107 +761,107 @@ system.cpu0.dcache.total_refs 23658997 # To system.cpu0.dcache.sampled_refs 628094 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.667924 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 366.656660 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 145.256121 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052690500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12045426500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377755000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718296000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096051000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611257000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088544500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699801500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100989012000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806840500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795852500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026720 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024406 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048849 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043678 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026368 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025718 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12265.219794 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12158.017994 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.684919 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29620.617861 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30547.377682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30087.271116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.156919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11356.982952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.922470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19172.276556 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.347357 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.371290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -976,26 +961,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7490923 # DTB read hits -system.cpu1.dtb.read_misses 7080 # DTB read misses -system.cpu1.dtb.write_hits 5680189 # DTB write hits -system.cpu1.dtb.write_misses 1780 # DTB write misses +system.cpu1.dtb.read_hits 7490951 # DTB read hits +system.cpu1.dtb.read_misses 7083 # DTB read misses +system.cpu1.dtb.write_hits 5680260 # DTB write hits +system.cpu1.dtb.write_misses 1778 # DTB write misses system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6452 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7498003 # DTB read accesses -system.cpu1.dtb.write_accesses 5681969 # DTB write accesses +system.cpu1.dtb.read_accesses 7498034 # DTB read accesses +system.cpu1.dtb.write_accesses 5682038 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13171112 # DTB hits -system.cpu1.dtb.misses 8860 # DTB misses -system.cpu1.dtb.accesses 13179972 # DTB accesses -system.cpu1.itb.inst_hits 30733895 # ITB inst hits +system.cpu1.dtb.hits 13171211 # DTB hits +system.cpu1.dtb.misses 8861 # DTB misses +system.cpu1.dtb.accesses 13180072 # DTB accesses +system.cpu1.itb.inst_hits 30733845 # ITB inst hits system.cpu1.itb.inst_misses 3661 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1012,30 +997,30 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses -system.cpu1.itb.hits 30733895 # DTB hits +system.cpu1.itb.inst_accesses 30737506 # ITB inst accesses +system.cpu1.itb.hits 30733845 # DTB hits system.cpu1.itb.misses 3661 # DTB misses -system.cpu1.itb.accesses 30737556 # DTB accesses -system.cpu1.numCycles 2664665536 # number of cpu cycles simulated +system.cpu1.itb.accesses 30737506 # DTB accesses +system.cpu1.numCycles 2664661810 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30062453 # Number of instructions committed -system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses +system.cpu1.committedInsts 30062381 # Number of instructions committed +system.cpu1.committedOps 38319191 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34454554 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses -system.cpu1.num_func_calls 1098871 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34454483 # number of integer instructions +system.cpu1.num_func_calls 1098878 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3931539 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34454554 # number of integer instructions system.cpu1.num_fp_insts 4993 # number of float instructions -system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written +system.cpu1.num_int_register_reads 197476132 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37039734 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written -system.cpu1.num_mem_refs 13738954 # number of memory refs -system.cpu1.num_load_insts 7815473 # Number of load instructions -system.cpu1.num_store_insts 5923481 # Number of store instructions -system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles -system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles +system.cpu1.num_mem_refs 13739046 # number of memory refs +system.cpu1.num_load_insts 7815505 # Number of load instructions +system.cpu1.num_store_insts 5923541 # Number of store instructions +system.cpu1.num_idle_cycles 1359990951.127739 # Number of idle cycles +system.cpu1.num_busy_cycles 1304670858.872261 # Number of busy cycles system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1054,10 +1039,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1196198690564 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196198690564 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1196198690564 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f940daeff..171e4af9f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,143 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140861 # Number of seconds simulated -sim_ticks 5140860798000 # Number of ticks simulated -final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136865 # Number of seconds simulated +sim_ticks 5136864535500 # Number of ticks simulated +final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170494 # Simulator instruction rate (inst/s) -host_op_rate 337025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2148706625 # Simulator tick rate (ticks/s) -host_mem_usage 754648 # Number of bytes of host memory used -host_seconds 2392.54 # Real time elapsed on the host -sim_insts 407913764 # Number of instructions simulated -sim_ops 806343994 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +host_inst_rate 199949 # Simulator instruction rate (inst/s) +host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2517891877 # Simulator tick rate (ticks/s) +host_mem_usage 755196 # Number of bytes of host memory used +host_seconds 2040.15 # Real time elapsed on the host +sim_insts 407925588 # Number of instructions simulated +sim_ops 806363480 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory -system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory -system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory +system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224331 # Total number of read requests seen -system.physmem.writeReqs 149480 # Total number of write requests seen -system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14357184 # Total number of bytes read from memory -system.physmem.bytesWritten 9566720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224749 # Total number of read requests seen +system.physmem.writeReqs 149477 # Total number of write requests seen +system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14383936 # Total number of bytes read from memory +system.physmem.bytesWritten 9566528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140860745500 # Total gap between requests +system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136864483000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224331 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 150627 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see +system.physmem.readPktSize::6 224749 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 149477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,16 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see @@ -173,70 +159,69 @@ system.physmem.wrQLenPdf::19 6499 # Wh system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests -system.physmem.totBusLat 1121335000 # Total cycles spent in databus access -system.physmem.totBankLat 3387807500 # Total cycles spent in bank access -system.physmem.avgQLat 21377.08 # Average queueing delay per request -system.physmem.avgBankLat 15106.13 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests +system.physmem.totBusLat 1123260000 # Total cycles spent in databus access +system.physmem.totBankLat 3389952500 # Total cycles spent in bank access +system.physmem.avgQLat 21207.34 # Average queueing delay per request +system.physmem.avgBankLat 15089.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41483.22 # Average memory access latency -system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 41297.13 # Average memory access latency +system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.88 # Average write queue length over time -system.physmem.readRowHits 193356 # Number of row buffer hits during reads -system.physmem.writeRowHits 105797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes -system.physmem.avgGap 13752566.79 # Average gap between requests -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.128668 # Cycle average of tags in use +system.physmem.avgWrQLen 11.02 # Average write queue length over time +system.physmem.readRowHits 193727 # Number of row buffer hits during reads +system.physmem.writeRowHits 105780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes +system.physmem.avgGap 13726637.07 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.116322 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86195570 # Number of BP lookups -system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits +system.cpu.branchPred.lookups 86198193 # Number of BP lookups +system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448232203 # number of cpu cycles simulated +system.cpu.numCycles 448153841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -472,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued -system.cpu.iq.rate 1.836247 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued +system.cpu.iq.rate 1.836572 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed -system.cpu.iew.exec_branches 83195358 # Number of branches executed -system.cpu.iew.exec_stores 9146246 # Number of stores executed -system.cpu.iew.exec_rate 1.832068 # Inst execution rate -system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639788924 # num instructions producing a value -system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value +system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed +system.cpu.iew.exec_branches 83197450 # Number of branches executed +system.cpu.iew.exec_stores 9146557 # Number of stores executed +system.cpu.iew.exec_rate 1.832396 # Inst execution rate +system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639795417 # num instructions producing a value +system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back +system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407913764 # Number of instructions committed -system.cpu.commit.committedOps 806343994 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407925588 # Number of instructions committed +system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389743 # Number of memory references committed -system.cpu.commit.loads 13977902 # Number of loads committed -system.cpu.commit.membars 473467 # Number of memory barriers committed -system.cpu.commit.branches 82188680 # Number of branches committed +system.cpu.commit.refs 22390327 # Number of memory references committed +system.cpu.commit.loads 13977401 # Number of loads committed +system.cpu.commit.membars 473457 # Number of memory barriers committed +system.cpu.commit.branches 82191015 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735286834 # Number of committed integer instructions. +system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5328099 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078074430 # The number of ROB reads -system.cpu.rob.rob_writes 1661878047 # The number of ROB writes -system.cpu.timesIdled 1220922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190343714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9833486813 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407913764 # Number of Instructions Simulated -system.cpu.committedOps 806343994 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407913764 # Number of Instructions Simulated -system.cpu.cpi 1.098841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910050 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910050 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506675506 # number of integer regfile reads -system.cpu.int_regfile_writes 976772305 # number of integer regfile writes -system.cpu.fp_regfile_reads 81 # number of floating regfile reads -system.cpu.misc_regfile_reads 264620330 # number of misc regfile reads -system.cpu.misc_regfile_writes 402287 # number of misc regfile writes -system.cpu.icache.replacements 1047202 # number of replacements -system.cpu.icache.tagsinuse 510.392599 # Cycle average of tags in use -system.cpu.icache.total_refs 7900027 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1047714 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.540251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1078031216 # The number of ROB reads +system.cpu.rob.rob_writes 1661854677 # The number of ROB writes +system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407925588 # Number of Instructions Simulated +system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated +system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads +system.cpu.int_regfile_writes 976781809 # number of integer regfile writes +system.cpu.fp_regfile_reads 63 # number of floating regfile reads +system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads +system.cpu.misc_regfile_writes 402234 # number of misc regfile writes +system.cpu.icache.replacements 1045798 # number of replacements +system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use +system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.392599 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996861 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996861 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7900027 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900027 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900027 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900027 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900027 # number of overall hits -system.cpu.icache.overall_hits::total 7900027 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1110794 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1110794 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1110794 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1110794 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1110794 # number of overall misses -system.cpu.icache.overall_misses::total 1110794 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15299065993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15299065993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15299065993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15299065993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9010821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9010821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9010821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9010821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123273 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123273 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123273 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123273 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13773.090234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13773.090234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10781 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits +system.cpu.icache.overall_hits::total 7900747 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses +system.cpu.icache.overall_misses::total 1109320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 279 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.641577 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60632 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60632 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60632 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60632 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1050162 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1050162 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1050162 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1050162 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9719 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.023103 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25822 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9733 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.653036 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104044206500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.023103 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25827 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25827 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9600 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25829 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25829 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10616 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10616 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36443 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36443 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109067 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135158 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135158 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110111 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110111 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12577.598968 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 108181 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36570 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1659765 # number of replacements -system.cpu.dcache.tagsinuse 511.990842 # Cycle average of tags in use -system.cpu.dcache.total_refs 19082473 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660277 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.493548 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1660118 # number of replacements +system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use +system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.990842 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10992813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10992813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19077348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19077348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19077348 # number of overall hits -system.cpu.dcache.overall_hits::total 19077348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2235315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2235315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318075 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318075 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553390 # number of overall misses -system.cpu.dcache.overall_misses::total 2553390 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41745410997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41745410997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21630738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21630738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21630738 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21630738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14349.544248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14349.544248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30400.564323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30400.564323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 385443 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits +system.cpu.dcache.overall_hits::total 19073633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses +system.cpu.dcache.overall_misses::total 2554209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.115360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561573 # number of writebacks -system.cpu.dcache.writebacks::total 1561573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863477 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 863477 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24970 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24970 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 888447 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 888447 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 888447 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 888447 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371838 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371838 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293105 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 293105 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1664943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1664943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1664943 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1664943 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17433703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17433703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8829680997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8829680997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26263383997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26263383997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26263383997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26263383997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470922500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470922500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103706 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103706 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076971 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076971 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12708.281153 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12708.281153 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30124.634506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30124.634506 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks +system.cpu.dcache.writebacks::total 1561388 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e72c9ec7f..fbbf2dd62 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.204983 # Nu sim_ticks 5204982530500 # Number of ticks simulated final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181134 # Simulator instruction rate (inst/s) -host_op_rate 347511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8731335326 # Simulator tick rate (ticks/s) -host_mem_usage 804468 # Number of bytes of host memory used -host_seconds 596.13 # Real time elapsed on the host +host_inst_rate 107235 # Simulator instruction rate (inst/s) +host_op_rate 205734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5169140013 # Simulator tick rate (ticks/s) +host_mem_usage 810688 # Number of bytes of host memory used +host_seconds 1006.93 # Real time elapsed on the host sim_insts 107979054 # Number of instructions simulated sim_ops 207160582 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory @@ -123,26 +123,13 @@ system.physmem.readPktSize::3 298 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 48406 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 46736 # Categorize write packet sizes system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see @@ -175,7 +162,6 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see @@ -208,15 +194,14 @@ system.physmem.wrQLenPdf::28 36 # Wh system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40946729 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests +system.physmem.totQLat 40945522 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52544272 # Sum of mem lat for all requests system.physmem.totBusLat 4050000 # Total cycles spent in databus access system.physmem.totBankLat 7548750 # Total cycles spent in bank access -system.physmem.avgQLat 50551.52 # Average queueing delay per request +system.physmem.avgQLat 50550.03 # Average queueing delay per request system.physmem.avgBankLat 9319.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 64870.96 # Average memory access latency +system.physmem.avgMemAccLat 64869.47 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s |