diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/long/fs/10.linux-boot | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/long/fs/10.linux-boot')
22 files changed, 7587 insertions, 7363 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 028711e47..158e17e5b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -11,14 +11,15 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -460,6 +464,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -469,7 +476,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -517,6 +524,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -535,7 +543,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -569,16 +576,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -861,16 +870,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -884,6 +895,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -908,7 +922,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -928,7 +942,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -951,16 +965,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -976,20 +992,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1010,9 +1028,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1025,14 +1044,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -1044,7 +1077,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1057,7 +1090,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 @@ -1072,10 +1105,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -1083,8 +1117,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -1140,12 +1175,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -1162,9 +1195,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -1178,9 +1212,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1194,9 +1229,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1210,9 +1246,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1226,9 +1263,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1242,9 +1280,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1258,9 +1297,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1274,9 +1314,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1290,9 +1331,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1306,9 +1348,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1322,9 +1365,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1338,9 +1382,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1354,9 +1399,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1370,9 +1416,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1386,9 +1433,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1402,9 +1450,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1418,9 +1467,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1434,9 +1484,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1450,9 +1501,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1466,9 +1518,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1512,16 +1565,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1530,9 +1582,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1541,8 +1594,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1550,7 +1604,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1558,8 +1613,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index acdd4bc1c..200b08796 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:48 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:40:49 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530295500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107840000 +Exiting @ tick 1897857556000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 763ec5c7a..59d7770e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896908 # Number of seconds simulated -sim_ticks 1896907607500 # Number of ticks simulated -final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897858 # Number of seconds simulated +sim_ticks 1897857556000 # Number of ticks simulated +final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91997 # Simulator instruction rate (inst/s) -host_op_rate 91997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3111116066 # Simulator tick rate (ticks/s) -host_mem_usage 330780 # Number of bytes of host memory used -host_seconds 609.72 # Real time elapsed on the host -sim_insts 56092592 # Number of instructions simulated -sim_ops 56092592 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory -system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449911 # Total number of read requests seen -system.physmem.writeReqs 121282 # Total number of write requests seen -system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28794304 # Total number of bytes read from memory -system.physmem.bytesWritten 7762048 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis +host_inst_rate 131170 # Simulator instruction rate (inst/s) +host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4437782045 # Simulator tick rate (ticks/s) +host_mem_usage 332328 # Number of bytes of host memory used +host_seconds 427.66 # Real time elapsed on the host +sim_insts 56096024 # Number of instructions simulated +sim_ops 56096024 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory +system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450802 # Total number of read requests seen +system.physmem.writeReqs 121968 # Total number of write requests seen +system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28851328 # Total number of bytes read from memory +system.physmem.bytesWritten 7805952 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896888917000 # Total gap between requests +system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897852967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449911 # Categorize read packet sizes +system.physmem.readPktSize::6 450802 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121595 # categorize write packet sizes +system.physmem.writePktSize::6 122493 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,31 +116,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests -system.physmem.totBusLat 1799432000 # Total cycles spent in databus access -system.physmem.totBankLat 5490114000 # Total cycles spent in bank access -system.physmem.avgQLat 14265.44 # Average queueing delay per request -system.physmem.avgBankLat 12204.10 # Average bank access latency per request +system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests +system.physmem.totBusLat 1803000000 # Total cycles spent in databus access +system.physmem.totBankLat 5519080000 # Total cycles spent in bank access +system.physmem.avgQLat 14764.02 # Average queueing delay per request +system.physmem.avgBankLat 12244.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30469.54 # Average memory access latency -system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31008.23 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 429697 # Number of row buffer hits during reads -system.physmem.writeRowHits 77704 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes -system.physmem.avgGap 3320924.66 # Average gap between requests -system.l2c.replacements 342985 # number of replacements -system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use -system.l2c.total_refs 2664537 # Total number of references to valid blocks. -system.l2c.sampled_refs 407990 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.530888 # Average number of references to valid blocks. +system.physmem.avgWrQLen 7.39 # Average write queue length over time +system.physmem.readRowHits 429728 # Number of row buffer hits during reads +system.physmem.writeRowHits 77127 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes +system.physmem.avgGap 3313464.33 # Average gap between requests +system.l2c.replacements 343886 # number of replacements +system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use +system.l2c.total_refs 2612992 # Total number of references to valid blocks. +system.l2c.sampled_refs 408910 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.390140 # Average number of references to valid blocks. system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits -system.l2c.Writeback_hits::total 859408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits 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accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,39 +508,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # 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-system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses +system.iocache.demand_misses::total 41724 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses +system.iocache.overall_misses::total 41724 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles 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+system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -546,40 +549,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229206.002262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229206.002262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41523 # number of writebacks system.iocache.writebacks::total 41523 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 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+system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -588,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -613,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7007258 # DTB read hits -system.cpu0.dtb.read_misses 29214 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 627494 # DTB read accesses -system.cpu0.dtb.write_hits 4619142 # DTB write hits -system.cpu0.dtb.write_misses 6985 # DTB write misses -system.cpu0.dtb.write_acv 345 # DTB write access violations -system.cpu0.dtb.write_accesses 208744 # DTB write accesses -system.cpu0.dtb.data_hits 11626400 # DTB hits -system.cpu0.dtb.data_misses 36199 # DTB misses -system.cpu0.dtb.data_acv 900 # DTB access violations -system.cpu0.dtb.data_accesses 836238 # DTB accesses -system.cpu0.itb.fetch_hits 888386 # ITB hits -system.cpu0.itb.fetch_misses 27286 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 915672 # ITB accesses +system.cpu0.dtb.read_hits 7996955 # DTB read hits +system.cpu0.dtb.read_misses 29938 # DTB read misses +system.cpu0.dtb.read_acv 553 # DTB read access violations +system.cpu0.dtb.read_accesses 624438 # DTB read accesses +system.cpu0.dtb.write_hits 5309744 # DTB write hits +system.cpu0.dtb.write_misses 7955 # DTB write misses +system.cpu0.dtb.write_acv 319 # DTB write access violations +system.cpu0.dtb.write_accesses 207916 # DTB write accesses +system.cpu0.dtb.data_hits 13306699 # DTB hits +system.cpu0.dtb.data_misses 37893 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 832354 # DTB accesses +system.cpu0.itb.fetch_hits 944692 # ITB hits +system.cpu0.itb.fetch_misses 28693 # ITB misses +system.cpu0.itb.fetch_acv 988 # ITB acv +system.cpu0.itb.fetch_accesses 973385 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -641,277 +644,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 83155415 # number of cpu cycles simulated +system.cpu0.numCycles 92901317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued -system.cpu0.iq.rate 0.487352 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued +system.cpu0.iq.rate 0.496715 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2446064 # number of nop insts executed -system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6330042 # Number of branches executed -system.cpu0.iew.exec_stores 4636142 # Number of stores executed -system.cpu0.iew.exec_rate 0.483213 # Inst execution rate -system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 19855593 # num instructions producing a value -system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value +system.cpu0.iew.exec_nop 2855336 # number of nop insts executed +system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7249094 # Number of branches executed +system.cpu0.iew.exec_stores 5329658 # Number of stores executed +system.cpu0.iew.exec_rate 0.492967 # Inst execution rate +system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22555336 # num instructions producing a value +system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 40051259 # Number of instructions committed -system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45914377 # Number of instructions committed +system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10855795 # Number of memory references committed -system.cpu0.commit.loads 6384070 # Number of loads committed -system.cpu0.commit.membars 151085 # Number of memory barriers committed -system.cpu0.commit.branches 6007416 # Number of branches committed -system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489523 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12498719 # Number of memory references committed +system.cpu0.commit.loads 7343270 # Number of loads committed +system.cpu0.commit.membars 179286 # Number of memory barriers committed +system.cpu0.commit.branches 6902899 # Number of branches committed +system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. +system.cpu0.commit.function_calls 573621 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 101537476 # The number of ROB reads -system.cpu0.rob.rob_writes 91770556 # The number of ROB writes -system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 37835874 # Number of Instructions Simulated -system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated -system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads -system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads -system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads -system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes +system.cpu0.rob.rob_reads 116563585 # The number of ROB reads +system.cpu0.rob.rob_writes 104266102 # The number of ROB writes +system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43304295 # Number of Instructions Simulated +system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated +system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads +system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes +system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads +system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads +system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -943,245 +946,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 642913 # number of replacements -system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use -system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits -system.cpu0.icache.overall_hits::total 5670885 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses -system.cpu0.icache.overall_misses::total 678650 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 790851 # number of replacements +system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use +system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits +system.cpu0.icache.overall_hits::total 6144778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses +system.cpu0.icache.overall_misses::total 831804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits 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miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 932591 # number of replacements -system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits -system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses -system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles 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# miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency 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# Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits 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miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) 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22493.148628 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency 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system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks -system.cpu0.dcache.writebacks::total 453711 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles 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1116427 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,22 +1196,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3713266 # DTB read hits -system.cpu1.dtb.read_misses 14359 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 328215 # DTB read accesses -system.cpu1.dtb.write_hits 2351870 # DTB write hits -system.cpu1.dtb.write_misses 2326 # DTB write misses -system.cpu1.dtb.write_acv 62 # DTB write access violations -system.cpu1.dtb.write_accesses 130566 # DTB write accesses -system.cpu1.dtb.data_hits 6065136 # DTB hits -system.cpu1.dtb.data_misses 16685 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 458781 # DTB accesses -system.cpu1.itb.fetch_hits 552396 # ITB hits -system.cpu1.itb.fetch_misses 7861 # ITB misses -system.cpu1.itb.fetch_acv 226 # ITB acv -system.cpu1.itb.fetch_accesses 560257 # ITB accesses +system.cpu1.dtb.read_hits 2657978 # DTB read hits +system.cpu1.dtb.read_misses 12789 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325192 # DTB read accesses +system.cpu1.dtb.write_hits 1642917 # DTB write hits +system.cpu1.dtb.write_misses 2443 # DTB write misses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_accesses 132832 # DTB write accesses +system.cpu1.dtb.data_hits 4300895 # DTB hits +system.cpu1.dtb.data_misses 15232 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 458024 # DTB accesses +system.cpu1.itb.fetch_hits 468004 # ITB hits +system.cpu1.itb.fetch_misses 6860 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 474864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1221,516 +1224,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34615367 # number of cpu cycles simulated +system.cpu1.numCycles 24425153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued -system.cpu1.iq.rate 0.575485 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued +system.cpu1.iq.rate 0.571646 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1269370 # number of nop insts executed -system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3128191 # Number of branches executed -system.cpu1.iew.exec_stores 2361866 # Number of stores executed -system.cpu1.iew.exec_rate 0.569357 # Inst execution rate -system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 9462232 # num instructions producing a value -system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value +system.cpu1.iew.exec_nop 825136 # number of nop insts executed +system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2168898 # Number of branches executed +system.cpu1.iew.exec_stores 1651079 # Number of stores executed +system.cpu1.iew.exec_rate 0.566055 # Inst execution rate +system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6651311 # num instructions producing a value +system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19375400 # Number of instructions committed -system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13515996 # Number of instructions committed +system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5615142 # Number of memory references committed -system.cpu1.commit.loads 3365090 # Number of loads committed -system.cpu1.commit.membars 85627 # Number of memory barriers committed -system.cpu1.commit.branches 2912516 # Number of branches committed -system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions. -system.cpu1.commit.function_calls 300496 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3973553 # Number of memory references committed +system.cpu1.commit.loads 2406453 # Number of loads committed +system.cpu1.commit.membars 57533 # Number of memory barriers committed +system.cpu1.commit.branches 2017672 # Number of branches committed +system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. +system.cpu1.commit.function_calls 216490 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 52972716 # The number of ROB reads -system.cpu1.rob.rob_writes 45818344 # The number of ROB writes -system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 18256718 # Number of Instructions Simulated -system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated -system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads -system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes -system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads -system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes -system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads -system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes -system.cpu1.icache.replacements 454861 # number of replacements -system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use -system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits -system.cpu1.icache.overall_hits::total 2515591 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses -system.cpu1.icache.overall_misses::total 476773 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 36803153 # The number of ROB reads +system.cpu1.rob.rob_writes 31994561 # The number of ROB writes +system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 12791729 # Number of Instructions Simulated +system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated +system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads +system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads +system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes +system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes +system.cpu1.icache.replacements 297472 # number of replacements +system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use +system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits +system.cpu1.icache.overall_hits::total 1814154 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses +system.cpu1.icache.overall_misses::total 311692 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 520860 # number of replacements -system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits 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-system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency 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-system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.replacements 296647 # number of replacements +system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits +system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses +system.cpu1.dcache.overall_misses::total 774607 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles 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0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency 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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles 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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq 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13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks +system.cpu1.dcache.writebacks::total 225448 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1739,170 +1742,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 130177 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 154704 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1271 +system.cpu0.kern.mode_good::user 1272 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2436 # number of times the context was actually changed +system.cpu0.kern.swap_context 3083 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed -system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed -system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed +system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 86022 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 518 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 59 -system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 61585 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches +system.cpu1.kern.mode_switch::user 476 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 537 +system.cpu1.kern.mode_good::user 476 +system.cpu1.kern.mode_good::idle 61 +system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1814 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 353ee4820..4e3852a72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,17 +8,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -163,7 +165,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -455,15 +459,55 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + [system.cpu.tracer] type=ExeTracer @@ -484,7 +528,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -504,7 +548,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -527,16 +571,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -547,31 +593,6 @@ write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -582,13 +603,14 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -601,14 +623,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -620,7 +656,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -630,16 +666,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -648,10 +674,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -659,8 +686,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -716,12 +744,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -738,9 +764,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -754,9 +781,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -770,9 +798,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -786,9 +815,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -802,9 +832,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -818,9 +849,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -834,9 +866,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -850,9 +883,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -866,9 +900,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -882,9 +917,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -898,9 +934,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -914,9 +951,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -930,9 +968,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -946,9 +985,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -962,9 +1002,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -978,9 +1019,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -994,9 +1036,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1010,9 +1053,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1026,9 +1070,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1042,9 +1087,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1088,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1106,9 +1151,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1117,8 +1163,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1126,7 +1173,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1134,8 +1182,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f67dea3de..6a7037f2d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:38 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:34:06 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1864423957500 because m5_exit instruction encountered +Exiting @ tick 1854349611000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index e834f19f3..cbfa90061 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854370 # Number of seconds simulated -sim_ticks 1854370484500 # Number of ticks simulated -final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854350 # Number of seconds simulated +sim_ticks 1854349611000 # Number of ticks simulated +final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120780 # Simulator instruction rate (inst/s) -host_op_rate 120780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4226353954 # Simulator tick rate (ticks/s) -host_mem_usage 326684 # Number of bytes of host memory used -host_seconds 438.76 # Real time elapsed on the host -sim_insts 52993965 # Number of instructions simulated -sim_ops 52993965 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445277 # Total number of read requests seen -system.physmem.writeReqs 117308 # Total number of write requests seen -system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28497728 # Total number of bytes read from memory -system.physmem.bytesWritten 7507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +host_inst_rate 135035 # Simulator instruction rate (inst/s) +host_op_rate 135035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4724741522 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 392.48 # Real time elapsed on the host +sim_insts 52998188 # Number of instructions simulated +sim_ops 52998188 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445311 # Total number of read requests seen +system.physmem.writeReqs 117478 # Total number of write requests seen +system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28499904 # Total number of bytes read from memory +system.physmem.bytesWritten 7518592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854344226000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::6 445311 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::6 118032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,29 +109,29 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests -system.physmem.totBusLat 1780884000 # Total cycles spent in databus access -system.physmem.totBankLat 5429382000 # Total cycles spent in bank access -system.physmem.avgQLat 13870.65 # Average queueing delay per request -system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests +system.physmem.totBusLat 1781012000 # Total cycles spent in databus access +system.physmem.totBankLat 5426764000 # Total cycles spent in bank access +system.physmem.avgQLat 14044.85 # Average queueing delay per request +system.physmem.avgBankLat 12188.05 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.45 # Average memory access latency +system.physmem.avgMemAccLat 30232.89 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 425232 # Number of row buffer hits during reads -system.physmem.writeRowHits 76485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes -system.physmem.avgGap 3296150.90 # Average gap between requests +system.physmem.avgWrQLen 11.07 # Average write queue length over time +system.physmem.readRowHits 425296 # Number of row buffer hits during reads +system.physmem.writeRowHits 76454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes +system.physmem.avgGap 3294919.10 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265505 # Cycle average of tags in use +system.iocache.tagsinuse 1.265413 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -213,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -237,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10013236 # DTB read hits -system.cpu.dtb.read_misses 44959 # DTB read misses -system.cpu.dtb.read_acv 558 # DTB read access violations -system.cpu.dtb.read_accesses 947796 # DTB read accesses -system.cpu.dtb.write_hits 6616814 # DTB write hits -system.cpu.dtb.write_misses 10390 # DTB write misses -system.cpu.dtb.write_acv 394 # DTB write access violations -system.cpu.dtb.write_accesses 338465 # DTB write accesses -system.cpu.dtb.data_hits 16630050 # DTB hits -system.cpu.dtb.data_misses 55349 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1286261 # DTB accesses -system.cpu.itb.fetch_hits 1329992 # ITB hits -system.cpu.itb.fetch_misses 37108 # ITB misses -system.cpu.itb.fetch_acv 1110 # ITB acv -system.cpu.itb.fetch_accesses 1367100 # ITB accesses +system.cpu.dtb.read_hits 9959916 # DTB read hits +system.cpu.dtb.read_misses 41524 # DTB read misses +system.cpu.dtb.read_acv 557 # DTB read access violations +system.cpu.dtb.read_accesses 942700 # DTB read accesses +system.cpu.dtb.write_hits 6603148 # DTB write hits +system.cpu.dtb.write_misses 10669 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338186 # DTB write accesses +system.cpu.dtb.data_hits 16563064 # DTB hits +system.cpu.dtb.data_misses 52193 # DTB misses +system.cpu.dtb.data_acv 966 # DTB access violations +system.cpu.dtb.data_accesses 1280886 # DTB accesses +system.cpu.itb.fetch_hits 1308562 # ITB hits +system.cpu.itb.fetch_misses 36917 # ITB misses +system.cpu.itb.fetch_acv 1051 # ITB acv +system.cpu.itb.fetch_accesses 1345479 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,147 +332,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109331520 # number of cpu cycles simulated +system.cpu.numCycles 108866981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits +system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued @@ -495,114 +495,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued -system.cpu.iq.rate 0.522738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued +system.cpu.iq.rate 0.522549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3558099 # number of nop insts executed -system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed -system.cpu.iew.exec_branches 8966109 # Number of branches executed -system.cpu.iew.exec_stores 6642423 # Number of stores executed -system.cpu.iew.exec_rate 0.518007 # Inst execution rate -system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27860065 # num instructions producing a value -system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value +system.cpu.iew.exec_nop 3530593 # number of nop insts executed +system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed +system.cpu.iew.exec_branches 8937468 # Number of branches executed +system.cpu.iew.exec_stores 6629043 # Number of stores executed +system.cpu.iew.exec_rate 0.518254 # Inst execution rate +system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27785553 # num instructions producing a value +system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56184240 # Number of instructions committed -system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188709 # Number of instructions committed +system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15475347 # Number of memory references committed -system.cpu.commit.loads 9094466 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8447798 # Number of branches committed +system.cpu.commit.refs 15476798 # Number of memory references committed +system.cpu.commit.loads 9095345 # Number of loads committed +system.cpu.commit.membars 226320 # Number of memory barriers committed +system.cpu.commit.branches 8447896 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. -system.cpu.commit.function_calls 740415 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034633 # Number of committed integer instructions. +system.cpu.commit.function_calls 740447 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142220969 # The number of ROB reads -system.cpu.rob.rob_writes 129940455 # The number of ROB writes -system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52993965 # Number of Instructions Simulated -system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated -system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74218754 # number of integer regfile reads -system.cpu.int_regfile_writes 40498790 # number of integer regfile writes -system.cpu.fp_regfile_reads 166070 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads -system.cpu.misc_regfile_writes 947042 # number of misc regfile writes +system.cpu.rob.rob_reads 141230883 # The number of ROB reads +system.cpu.rob.rob_writes 128808067 # The number of ROB writes +system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998188 # Number of Instructions Simulated +system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated +system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73962724 # number of integer regfile reads +system.cpu.int_regfile_writes 40347354 # number of integer regfile writes +system.cpu.fp_regfile_reads 166024 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads +system.cpu.misc_regfile_writes 947074 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -634,355 +634,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020188 # number of replacements -system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use -system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits -system.cpu.icache.overall_hits::total 7717775 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses -system.cpu.icache.overall_misses::total 1079494 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.icache.replacements 1012720 # number of replacements +system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use +system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 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accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # 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ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 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ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback 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# miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses 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73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,80 +825,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks -system.cpu.l2cache.writebacks::total 75796 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks +system.cpu.l2cache.writebacks::total 75966 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses 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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,29 +898,191 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1400783 # number of replacements +system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use +system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits +system.cpu.dcache.overall_hits::total 11417555 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses +system.cpu.dcache.overall_misses::total 3744371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks +system.cpu.dcache.writebacks::total 840489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1133,29 +1121,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191972 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191934 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index f66d752af..219ef17ea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +70,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb tracer +children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -167,7 +168,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -200,10 +201,10 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.itb] type=ArmTLB @@ -213,10 +214,10 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer @@ -226,10 +227,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -237,7 +238,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -246,7 +247,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -256,10 +257,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -529,10 +530,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -540,7 +541,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -549,7 +550,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -562,10 +563,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -589,18 +627,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -611,33 +649,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -648,11 +659,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -668,15 +679,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -691,7 +715,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -700,7 +724,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -747,7 +771,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -778,7 +802,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -787,7 +811,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -804,7 +828,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -818,7 +842,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -828,7 +852,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -838,7 +862,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -848,7 +872,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -862,7 +886,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -875,7 +899,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -904,7 +928,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -914,7 +938,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -926,7 +950,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -938,7 +962,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -951,7 +975,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -961,7 +985,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -971,7 +995,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -981,7 +1005,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -991,7 +1015,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1005,7 +1029,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1018,7 +1042,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1033,7 +1057,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1043,7 +1067,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1053,7 +1077,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1063,7 +1087,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1077,16 +1101,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3e85e4166..2082cdfd9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,34 +10,27 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 5011d2336..a3de8bb34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:35:22 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 2 2012 01:09:00 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3725b6e15..a24f5a985 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68763 # Simulator instruction rate (inst/s) -host_op_rate 88448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2863680529 # Simulator tick rate (ticks/s) -host_mem_usage 399792 # Number of bytes of host memory used -host_seconds 881.25 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 54734 # Simulator instruction rate (inst/s) +host_op_rate 70403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2279341302 # Simulator tick rate (ticks/s) +host_mem_usage 401036 # Number of bytes of host memory used +host_seconds 1107.12 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048943 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11294215 # DTB write hits +system.cpu.checker.dtb.read_hits 15048842 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11294147 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056252 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296404 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343158 # DTB hits -system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26352656 # DTB accesses -system.cpu.checker.itb.inst_hits 61775988 # ITB inst hits +system.cpu.checker.dtb.hits 26342989 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26352486 # DTB accesses +system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780459 # ITB inst accesses -system.cpu.checker.itb.hits 61775988 # DTB hits +system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses +system.cpu.checker.itb.hits 61775601 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780459 # DTB accesses -system.cpu.checker.numCycles 78235930 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780072 # DTB accesses +system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7715 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,538 +301,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5202 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506178 # number of integer regfile reads -system.cpu.int_regfile_writes 88407138 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of 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(read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 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# average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked 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731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses 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13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked 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LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits 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misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses 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11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average 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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f00ea7875..966a7a822 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,9 +12,10 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -198,7 +199,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -496,6 +497,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -504,7 +522,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -514,7 +532,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -562,6 +580,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -613,10 +632,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -624,7 +643,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -643,7 +662,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -916,10 +935,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -927,7 +946,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -941,6 +960,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -949,7 +985,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -976,18 +1012,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -1003,22 +1039,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1039,7 +1075,7 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1055,15 +1091,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -1078,7 +1127,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -1087,7 +1136,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1134,7 +1183,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -1165,7 +1214,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1174,7 +1223,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1191,7 +1240,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1205,7 +1254,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1215,7 +1264,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1225,7 +1274,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1235,7 +1284,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1249,7 +1298,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1262,7 +1311,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1291,7 +1340,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1301,7 +1350,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -1313,7 +1362,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1325,7 +1374,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1338,7 +1387,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1348,7 +1397,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1358,7 +1407,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1368,7 +1417,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1378,7 +1427,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1392,7 +1441,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1405,7 +1454,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1420,7 +1469,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1430,7 +1479,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1440,7 +1489,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1450,7 +1499,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1467,7 +1516,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 4c598b20c..ac731cab9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:18:35 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:14:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2616878893500 because m5_exit instruction encountered +Exiting @ tick 2593146078000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 30d23f9d7..2681ab283 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603317 # Number of seconds simulated -sim_ticks 2603316759000 # Number of ticks simulated -final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.593146 # Number of seconds simulated +sim_ticks 2593146078000 # Number of ticks simulated +final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64170 # Simulator instruction rate (inst/s) -host_op_rate 82590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2648964509 # Simulator tick rate (ticks/s) -host_mem_usage 407980 # Number of bytes of host memory used -host_seconds 982.77 # Real time elapsed on the host -sim_insts 63063787 # Number of instructions simulated -sim_ops 81167171 # Number of ops (including micro ops) simulated +host_inst_rate 66425 # Simulator instruction rate (inst/s) +host_op_rate 85503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2731005239 # Simulator tick rate (ticks/s) +host_mem_usage 409388 # Number of bytes of host memory used +host_seconds 949.52 # Real time elapsed on the host +sim_insts 63072130 # Number of instructions simulated +sim_ops 81187111 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory -system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302357 # Total number of read requests seen -system.physmem.writeReqs 824226 # Total number of write requests seen -system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979350848 # Total number of bytes read from memory -system.physmem.bytesWritten 52750464 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302381 # Total number of read requests seen +system.physmem.writeReqs 824191 # Total number of write requests seen +system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979352384 # Total number of bytes read from memory +system.physmem.bytesWritten 52748224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603315545500 # Total gap between requests +system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry +system.physmem.totGap 2593144762500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163436 # Categorize read packet sizes +system.physmem.readPktSize::6 163460 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1909372 # categorize write packet sizes +system.physmem.writePktSize::2 1907771 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66942 # categorize write packet sizes +system.physmem.writePktSize::6 66907 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +138,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests -system.physmem.totBusLat 61207928000 # Total cycles spent in databus access -system.physmem.totBankLat 213142888000 # Total cycles spent in bank access -system.physmem.avgQLat 3140.88 # Average queueing delay per request -system.physmem.avgBankLat 13929.10 # Average bank access latency per request +system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests +system.physmem.totBusLat 61208184000 # Total cycles spent in databus access +system.physmem.totBankLat 213133396000 # Total cycles spent in bank access +system.physmem.avgQLat 3128.25 # Average queueing delay per request +system.physmem.avgBankLat 13928.42 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21069.98 # Average memory access latency -system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 21056.67 # Average memory access latency +system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.busUtil 2.49 # Data bus utilization in percentage system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 11.94 # Average write queue length over time -system.physmem.readRowHits 15253098 # Number of row buffer hits during reads -system.physmem.writeRowHits 789391 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.88 # Average write queue length over time +system.physmem.readRowHits 15253448 # Number of row buffer hits during reads +system.physmem.writeRowHits 789566 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes -system.physmem.avgGap 161430.08 # Average gap between requests +system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes +system.physmem.avgGap 160799.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -235,244 +239,258 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73153 # number of replacements -system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use -system.l2c.total_refs 1922203 # Total number of references to valid blocks. -system.l2c.sampled_refs 138333 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.895477 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73184 # number of replacements +system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use +system.l2c.total_refs 1906265 # Total number of references to valid blocks. +system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits -system.l2c.Writeback_hits::total 584379 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits +system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits +system.l2c.Writeback_hits::total 583960 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47923 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106824 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 35828 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5516 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398518 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6316 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 614017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260961 # number of demand (read+write) hits -system.l2c.demand_hits::total 1588466 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 35828 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5516 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398518 # number of overall hits -system.l2c.overall_hits::cpu0.data 213369 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53941 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6316 # number of overall hits -system.l2c.overall_hits::cpu1.inst 614017 # number of overall hits -system.l2c.overall_hits::cpu1.data 260961 # number of overall hits -system.l2c.overall_hits::total 1588466 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits +system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -665,27 +695,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9063545 # DTB read hits -system.cpu0.dtb.read_misses 36220 # DTB read misses -system.cpu0.dtb.write_hits 5280653 # DTB write hits -system.cpu0.dtb.write_misses 6480 # DTB write misses +system.cpu0.dtb.read_hits 9014303 # DTB read hits +system.cpu0.dtb.read_misses 34965 # DTB read misses +system.cpu0.dtb.write_hits 5253714 # DTB write hits +system.cpu0.dtb.write_misses 6399 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9099765 # DTB read accesses -system.cpu0.dtb.write_accesses 5287133 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9049268 # DTB read accesses +system.cpu0.dtb.write_accesses 5260113 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14344198 # DTB hits -system.cpu0.dtb.misses 42700 # DTB misses -system.cpu0.dtb.accesses 14386898 # DTB accesses -system.cpu0.itb.inst_hits 4425189 # ITB inst hits -system.cpu0.itb.inst_misses 5562 # ITB inst misses +system.cpu0.dtb.hits 14268017 # DTB hits +system.cpu0.dtb.misses 41364 # DTB misses +system.cpu0.dtb.accesses 14309381 # DTB accesses +system.cpu0.itb.inst_hits 4294311 # ITB inst hits +system.cpu0.itb.inst_misses 5261 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -694,542 +724,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses -system.cpu0.itb.hits 4425189 # DTB hits -system.cpu0.itb.misses 5562 # DTB misses -system.cpu0.itb.accesses 4430751 # DTB accesses -system.cpu0.numCycles 69436793 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses +system.cpu0.itb.hits 4294311 # DTB hits +system.cpu0.itb.misses 5261 # DTB misses +system.cpu0.itb.accesses 4299572 # DTB accesses +system.cpu0.numCycles 69013505 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued -system.cpu0.iq.rate 0.550303 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued +system.cpu0.iq.rate 0.549915 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119640 # number of nop insts executed -system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4997979 # Number of branches executed -system.cpu0.iew.exec_stores 5553630 # Number of stores executed -system.cpu0.iew.exec_rate 0.544294 # Inst execution rate -system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18742857 # num instructions producing a value -system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value +system.cpu0.iew.exec_nop 117654 # number of nop insts executed +system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4958494 # Number of branches executed +system.cpu0.iew.exec_stores 5526390 # Number of stores executed +system.cpu0.iew.exec_rate 0.544297 # Inst execution rate +system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18655901 # num instructions producing a value +system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24262669 # Number of instructions committed -system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24264310 # Number of instructions committed +system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692115 # Number of memory references committed -system.cpu0.commit.loads 6419212 # Number of loads committed -system.cpu0.commit.membars 234468 # Number of memory barriers committed -system.cpu0.commit.branches 4346825 # Number of branches committed +system.cpu0.commit.refs 11698867 # Number of memory references committed +system.cpu0.commit.loads 6423036 # Number of loads committed +system.cpu0.commit.membars 234373 # Number of memory barriers committed +system.cpu0.commit.branches 4346960 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500017 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499893 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 78638973 # The number of ROB reads -system.cpu0.rob.rob_writes 78294863 # The number of ROB writes -system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24181927 # Number of Instructions Simulated -system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated -system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads -system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes -system.cpu0.icache.replacements 404775 # number of replacements -system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use -system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits -system.cpu0.icache.overall_hits::total 3985323 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses -system.cpu0.icache.overall_misses::total 438012 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77875275 # The number of ROB reads +system.cpu0.rob.rob_writes 77410136 # The number of ROB writes +system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24183568 # Number of Instructions Simulated +system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated +system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads +system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads +system.cpu0.fp_regfile_writes 906 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes +system.cpu0.icache.replacements 399233 # number of replacements +system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use +system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits +system.cpu0.icache.overall_hits::total 3861943 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses +system.cpu0.icache.overall_misses::total 430668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses 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overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274922 # number of replacements -system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits -system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses -system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 274937 # number of replacements +system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits 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cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses) 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13760.831290 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks -system.cpu0.dcache.writebacks::total 255626 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks +system.cpu0.dcache.writebacks::total 255577 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1239,27 +1265,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43093620 # DTB read hits -system.cpu1.dtb.read_misses 44212 # DTB read misses -system.cpu1.dtb.write_hits 7019560 # DTB write hits -system.cpu1.dtb.write_misses 11765 # DTB write misses +system.cpu1.dtb.read_hits 43030291 # DTB read hits +system.cpu1.dtb.read_misses 42638 # DTB read misses +system.cpu1.dtb.write_hits 6991861 # DTB write hits +system.cpu1.dtb.write_misses 11867 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43137832 # DTB read accesses -system.cpu1.dtb.write_accesses 7031325 # DTB write accesses +system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43072929 # DTB read accesses +system.cpu1.dtb.write_accesses 7003728 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50113180 # DTB hits -system.cpu1.dtb.misses 55977 # DTB misses -system.cpu1.dtb.accesses 50169157 # DTB accesses -system.cpu1.itb.inst_hits 7945263 # ITB inst hits -system.cpu1.itb.inst_misses 6054 # ITB inst misses +system.cpu1.dtb.hits 50022152 # DTB hits +system.cpu1.dtb.misses 54505 # DTB misses +system.cpu1.dtb.accesses 50076657 # DTB accesses +system.cpu1.itb.inst_hits 7786412 # ITB inst hits +system.cpu1.itb.inst_misses 5635 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1268,538 +1294,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses -system.cpu1.itb.hits 7945263 # DTB hits -system.cpu1.itb.misses 6054 # DTB misses -system.cpu1.itb.accesses 7951317 # DTB accesses -system.cpu1.numCycles 409430571 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses +system.cpu1.itb.hits 7786412 # DTB hits +system.cpu1.itb.misses 5635 # DTB misses +system.cpu1.itb.accesses 7792047 # DTB accesses +system.cpu1.numCycles 409024249 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued -system.cpu1.iq.rate 0.218509 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued +system.cpu1.iq.rate 0.217987 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106113 # number of nop insts executed -system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7123929 # Number of branches executed -system.cpu1.iew.exec_stores 7325122 # Number of stores executed -system.cpu1.iew.exec_rate 0.214080 # Inst execution rate -system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30455976 # num instructions producing a value -system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value +system.cpu1.iew.exec_nop 104288 # number of nop insts executed +system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7088545 # Number of branches executed +system.cpu1.iew.exec_stores 7297390 # Number of stores executed +system.cpu1.iew.exec_rate 0.213684 # Inst execution rate +system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30364436 # num instructions producing a value +system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38951499 # Number of instructions committed -system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38958201 # Number of instructions committed +system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17023134 # Number of memory references committed -system.cpu1.commit.loads 9997743 # Number of loads committed -system.cpu1.commit.membars 202380 # Number of memory barriers committed -system.cpu1.commit.branches 6138522 # Number of branches committed +system.cpu1.commit.refs 17027012 # Number of memory references committed +system.cpu1.commit.loads 10000155 # Number of loads committed +system.cpu1.commit.membars 202531 # Number of memory barriers committed +system.cpu1.commit.branches 6139960 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556453 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556605 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172487010 # The number of ROB reads -system.cpu1.rob.rob_writes 129525616 # The number of ROB writes -system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38881860 # Number of Instructions Simulated -system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated -system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads -system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes -system.cpu1.icache.replacements 620724 # number of replacements -system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use -system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits -system.cpu1.icache.overall_hits::total 7273497 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses -system.cpu1.icache.overall_misses::total 669686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked +system.cpu1.rob.rob_reads 171645222 # The number of ROB reads +system.cpu1.rob.rob_writes 128401309 # The number of ROB writes +system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38888562 # Number of Instructions Simulated +system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated +system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads +system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads +system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes +system.cpu1.icache.replacements 614989 # number of replacements +system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use +system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits +system.cpu1.icache.overall_hits::total 7122851 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses +system.cpu1.icache.overall_misses::total 661583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses 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overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363973 # number of replacements -system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of 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LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses -system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles 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# miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency 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accesses +system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328753 # number of writebacks -system.cpu1.dcache.writebacks::total 328753 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394981 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394981 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks +system.cpu1.dcache.writebacks::total 328383 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1821,18 +1847,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e428e398a..fbd26bc50 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -188,7 +189,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -198,10 +199,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -491,11 +492,28 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -504,10 +522,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -531,18 +586,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -553,33 +608,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -590,11 +618,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -610,15 +638,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -633,7 +674,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -642,7 +683,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -689,7 +730,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -720,7 +761,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -729,7 +770,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -746,7 +787,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -760,7 +801,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -770,7 +811,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -780,7 +821,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -790,7 +831,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -804,7 +845,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -817,7 +858,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -846,7 +887,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -856,7 +897,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -868,7 +909,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -880,7 +921,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -893,7 +934,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -903,7 +944,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -913,7 +954,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -923,7 +964,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -933,7 +974,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -947,7 +988,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -960,7 +1001,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -975,7 +1016,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -985,7 +1026,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -995,7 +1036,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1005,7 +1046,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1019,16 +1060,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index affb69ad6..3ee89fc27 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 304caa505..e4320499c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:10:34 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:11:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 68a4a5e77..6a79df0e0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77702 # Simulator instruction rate (inst/s) -host_op_rate 99947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3235958193 # Simulator tick rate (ticks/s) -host_mem_usage 399788 # Number of bytes of host memory used -host_seconds 779.87 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 66325 # Simulator instruction rate (inst/s) +host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2762063576 # Simulator tick rate (ticks/s) +host_mem_usage 400896 # Number of bytes of host memory used +host_seconds 913.63 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4230 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,688 +256,526 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2603 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506175 # number of integer regfile reads -system.cpu.int_regfile_writes 88407137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353817 # number of integer regfile reads +system.cpu.int_regfile_writes 87979071 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq 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ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # 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uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 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overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the 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accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses 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WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles 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accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses 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+system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses 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rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency 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cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 97b29a376..f7ba63a28 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -8,15 +8,15 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 -clock=1 +clock=1000 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -52,7 +52,7 @@ oem_table_id= [system.apicbridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=11529215046068469760:11529215046068473855 req_size=16 @@ -62,7 +62,7 @@ slave=system.iobus.master[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 @@ -72,7 +72,7 @@ slave=system.membus.master[1] [system.cpu] type=DerivO3CPU -children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer +children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -120,6 +120,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -171,17 +172,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -190,7 +192,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -200,7 +202,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -209,17 +211,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -228,7 +231,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port -mem_side=system.toL2Bus.slave[3] +mem_side=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -498,17 +501,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -517,11 +521,11 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -530,6 +534,9 @@ int_master=system.membus.slave[4] int_slave=system.membus.master[3] pio=system.membus.master[2] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -538,7 +545,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -547,17 +554,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -566,7 +574,44 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port -mem_side=system.toL2Bus.slave[2] +mem_side=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[3] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side [system.cpu.tracer] type=ExeTracer @@ -950,17 +995,18 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -is_top_level=false -latency=50000 +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -971,32 +1017,6 @@ write_buffers=8 cpu_side=system.iobus.master[18] mem_side=system.membus.slave[2] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[3] - [system.membus] type=CoherentBus children=badaddr_responder @@ -1007,11 +1027,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1034,7 +1054,7 @@ system=system [system.pc.behind_pci] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1052,7 +1072,7 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal -clock=1 +clock=1000 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1076,7 +1096,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1093,7 +1113,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1110,7 +1130,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1127,7 +1147,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1144,7 +1164,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1162,7 +1182,7 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -clock=1 +clock=1000 pio_latency=30000 platform=system.pc size=16777216 @@ -1185,7 +1205,7 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1198,7 +1218,7 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 -clock=1 +clock=1000 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1245,7 +1265,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 @@ -1277,7 +1297,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/projects/pd/randd/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1297,7 +1317,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1380,7 +1400,7 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 -clock=1 +clock=1000 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1392,7 +1412,7 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin -clock=1 +clock=1000 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin @@ -1411,7 +1431,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1426,7 +1446,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1441,7 +1461,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1453,7 +1473,7 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker -clock=1 +clock=1000 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1461,15 +1481,28 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] @@ -1494,13 +1527,3 @@ starting_addr_segment=0 vendor= version= -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side - diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 54a312ff8..8ce3a2233 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -5,9 +5,6 @@ warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index a7e5df44c..334789158 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:31:43 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 18:26:17 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5167941639500 because m5_exit instruction encountered +Exiting @ tick 5132789913000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 46e54af4f..87b53a299 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132866 # Number of seconds simulated -sim_ticks 5132866386000 # Number of ticks simulated -final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132790 # Number of seconds simulated +sim_ticks 5132789913000 # Number of ticks simulated +final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195837 # Simulator instruction rate (inst/s) -host_op_rate 387119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2464119438 # Simulator tick rate (ticks/s) -host_mem_usage 403620 # Number of bytes of host memory used -host_seconds 2083.04 # Real time elapsed on the host -sim_insts 407937545 # Number of instructions simulated -sim_ops 806384911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1081536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10883712 # Number of bytes read from this memory -system.physmem.bytes_read::total 14443712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9597376 # Number of bytes written to this memory -system.physmem.bytes_written::total 9597376 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 170058 # Number of read requests responded to by this memory -system.physmem.num_reads::total 225683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149959 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149959 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 225683 # Total number of read requests seen -system.physmem.writeReqs 149959 # Total number of write requests seen -system.physmem.cpureqs 389568 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14443712 # Total number of bytes read from memory -system.physmem.bytesWritten 9597376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14443712 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14751 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14847 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14758 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 10102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9598 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 9903 # Track writes on a per bank basis +host_inst_rate 148899 # Simulator instruction rate (inst/s) +host_op_rate 294332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1873578722 # Simulator tick rate (ticks/s) +host_mem_usage 406892 # Number of bytes of host memory used +host_seconds 2739.56 # Real time elapsed on the host +sim_insts 407917143 # Number of instructions simulated +sim_ops 806342485 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory +system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory +system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225083 # Total number of read requests seen +system.physmem.writeReqs 149670 # Total number of write requests seen +system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14405312 # Total number of bytes read from memory +system.physmem.bytesWritten 9578880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132866305000 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132789860500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 225683 # Categorize read packet sizes +system.physmem.readPktSize::6 225083 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149959 # categorize write packet sizes +system.physmem.writePktSize::6 149719 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,31 +114,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3846 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 177236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -150,47 +150,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests -system.physmem.totBusLat 902376000 # Total cycles spent in databus access -system.physmem.totBankLat 3362716000 # Total cycles spent in bank access -system.physmem.avgQLat 14801.33 # Average queueing delay per request -system.physmem.avgBankLat 14906.05 # Average bank access latency per request +system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests +system.physmem.totBusLat 900032000 # Total cycles spent in databus access +system.physmem.totBankLat 3348464000 # Total cycles spent in bank access +system.physmem.avgQLat 14530.99 # Average queueing delay per request +system.physmem.avgBankLat 14881.53 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33707.38 # Average memory access latency +system.physmem.avgMemAccLat 33412.53 # Average memory access latency system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s @@ -198,45 +198,45 @@ system.physmem.avgConsumedWrBW 1.87 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 10.11 # Average write queue length over time -system.physmem.readRowHits 199074 # Number of row buffer hits during reads -system.physmem.writeRowHits 88511 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes -system.physmem.avgGap 13664250.28 # Average gap between requests -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.103977 # Cycle average of tags in use +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 198566 # Number of row buffer hits during reads +system.physmem.writeRowHits 87960 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes +system.physmem.avgGap 13696461.03 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.103964 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,409 +308,409 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448858777 # number of cpu cycles simulated +system.cpu.numCycles 447650408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits +system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued -system.cpu.iq.rate 1.836670 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued +system.cpu.iq.rate 1.839122 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed -system.cpu.iew.exec_branches 83279279 # Number of branches executed -system.cpu.iew.exec_stores 9223365 # Number of stores executed -system.cpu.iew.exec_rate 1.832152 # Inst execution rate -system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640562059 # num instructions producing a value -system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value +system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed +system.cpu.iew.exec_branches 83217289 # Number of branches executed +system.cpu.iew.exec_stores 9158024 # Number of stores executed +system.cpu.iew.exec_rate 1.834889 # Inst execution rate +system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639951171 # num instructions producing a value +system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back +system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255051171 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407937545 # Number of instructions committed -system.cpu.commit.committedOps 806384911 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407917143 # Number of instructions committed +system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22391676 # Number of memory references committed -system.cpu.commit.loads 13975668 # Number of loads committed -system.cpu.commit.membars 473465 # Number of memory barriers committed -system.cpu.commit.branches 82190309 # Number of branches committed +system.cpu.commit.refs 22389123 # Number of memory references committed +system.cpu.commit.loads 13975326 # Number of loads committed +system.cpu.commit.membars 473463 # Number of memory barriers committed +system.cpu.commit.branches 82187715 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735319938 # Number of committed integer instructions. +system.cpu.commit.int_insts 735283087 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5262891 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080825517 # The number of ROB reads -system.cpu.rob.rob_writes 1666103017 # The number of ROB writes -system.cpu.timesIdled 1222907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189972024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9816871415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407937545 # Number of Instructions Simulated -system.cpu.committedOps 806384911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407937545 # Number of Instructions Simulated -system.cpu.cpi 1.100312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508250980 # number of integer regfile reads -system.cpu.int_regfile_writes 977858997 # number of integer regfile writes -system.cpu.fp_regfile_reads 66 # number of floating regfile reads -system.cpu.misc_regfile_reads 265171411 # number of misc regfile reads -system.cpu.misc_regfile_writes 402390 # number of misc regfile writes -system.cpu.icache.replacements 1072344 # number of replacements -system.cpu.icache.tagsinuse 510.326715 # Cycle average of tags in use -system.cpu.icache.total_refs 8127499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.575580 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.326715 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996732 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996732 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8127499 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8127499 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8127499 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8127499 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8127499 # number of overall hits -system.cpu.icache.overall_hits::total 8127499 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1142014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1142014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1142014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1142014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1142014 # number of overall misses -system.cpu.icache.overall_misses::total 1142014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15424181989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15424181989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15424181989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15424181989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9269513 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9269513 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9269513 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9269513 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123201 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123201 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123201 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123201 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.123383 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.123383 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7378 # number of cycles access was blocked +system.cpu.rob.rob_reads 1078075497 # The number of ROB reads +system.cpu.rob.rob_writes 1662514782 # The number of ROB writes +system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407917143 # Number of Instructions Simulated +system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated +system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads +system.cpu.int_regfile_writes 976968921 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads +system.cpu.misc_regfile_writes 402218 # number of misc regfile writes +system.cpu.icache.replacements 1046081 # number of replacements +system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use +system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits +system.cpu.icache.overall_hits::total 7932749 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses +system.cpu.icache.overall_misses::total 1110744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.047244 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.656934 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66936 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66936 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66936 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66936 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66936 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66936 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075078 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075078 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075078 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12692625989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12692625989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12692625989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12692625989 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.237305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.237305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61679 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61679 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10190 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.008148 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 29715 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10203 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.912379 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103977180500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008148 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375509 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375509 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29719 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 29719 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9937 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.006130 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26086 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9951 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.621445 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5106893785000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29722 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 29722 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11072 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11072 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11072 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11072 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11072 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11072 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 125220500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 125220500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 125220500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 125220500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 125220500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 125220500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40791 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40791 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26222 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26222 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26222 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26222 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10817 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10817 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10817 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10817 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10817 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10817 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116537500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116537500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116537500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116537500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116537500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116537500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37036 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37036 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.271432 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.271432 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.271412 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.271412 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.271412 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.271412 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11309.654986 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11309.654986 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.292044 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.292044 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.292044 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.292044 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10773.550892 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10773.550892 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10773.550892 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1966 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 103076500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 103076500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.271432 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.271432 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.271412 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.271412 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9309.654986 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10817 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94903500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94903500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94903500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94903500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94903500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94903500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.292067 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 112521 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.957581 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.957581 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809849 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809849 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137452 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137452 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137452 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137452 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137452 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137452 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113500 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 113500 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113500 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113500 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 113500 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 113923 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37324 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37324 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671903 # number of replacements -system.cpu.dcache.tagsinuse 511.996701 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219910 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.492309 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11126974 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11126974 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8088054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8088054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19215028 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19215028 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19215028 # number of overall hits -system.cpu.dcache.overall_hits::total 19215028 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2267052 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2267052 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318719 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2585771 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2585771 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2585771 # number of overall misses -system.cpu.dcache.overall_misses::total 2585771 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41980097993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41980097993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21800799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21800799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21800799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21800799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118609 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118609 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118609 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118609 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14275.250413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14275.250413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30175.053866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30175.053866 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits +system.cpu.dcache.overall_hits::total 19097808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2233987 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317747 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42571 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.300439 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12630.749450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks +system.cpu.dcache.writebacks::total 1559612 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862458 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862458 # 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