diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/fs/10.linux-boot | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/fs/10.linux-boot')
5 files changed, 7369 insertions, 7388 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 9af3017c0..2bd7abaa8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887184 # Number of seconds simulated -sim_ticks 1887184463000 # Number of ticks simulated -final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887179 # Number of seconds simulated +sim_ticks 1887179292000 # Number of ticks simulated +final_tick 1887179292000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 272052 # Simulator instruction rate (inst/s) -host_op_rate 272052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9147074399 # Simulator tick rate (ticks/s) -host_mem_usage 373996 # Number of bytes of host memory used -host_seconds 206.32 # Real time elapsed on the host -sim_insts 56128524 # Number of instructions simulated -sim_ops 56128524 # Number of ops (including micro ops) simulated +host_inst_rate 271909 # Simulator instruction rate (inst/s) +host_op_rate 271909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9140545464 # Simulator tick rate (ticks/s) +host_mem_usage 373988 # Number of bytes of host memory used +host_seconds 206.46 # Real time elapsed on the host +sim_insts 56138893 # Number of instructions simulated +sim_ops 56138893 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1052544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25912448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7556224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7556224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388421 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118066 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118066 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 557734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13172540 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13730782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4003978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4003978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4003978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13172540 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404899 # Number of read requests accepted -system.physmem.writeReqs 159652 # Number of write requests accepted -system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25492 # Per bank write bursts -system.physmem.perBankRdBursts::1 25732 # Per bank write bursts -system.physmem.perBankRdBursts::2 25844 # Per bank write bursts -system.physmem.perBankRdBursts::3 25788 # Per bank write bursts -system.physmem.perBankRdBursts::4 25096 # Per bank write bursts -system.physmem.perBankRdBursts::5 25019 # Per bank write bursts -system.physmem.perBankRdBursts::6 24724 # Per bank write bursts -system.physmem.perBankRdBursts::7 24556 # Per bank write bursts -system.physmem.perBankRdBursts::8 25196 # Per bank write bursts -system.physmem.perBankRdBursts::9 25300 # Per bank write bursts -system.physmem.perBankRdBursts::10 25394 # Per bank write bursts -system.physmem.perBankRdBursts::11 24993 # Per bank write bursts +system.physmem.bw_total::total 17734760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404882 # Number of read requests accepted +system.physmem.writeReqs 159618 # Number of write requests accepted +system.physmem.readBursts 404882 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159618 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25905920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 8528320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25912448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10215552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26335 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25487 # Per bank write bursts +system.physmem.perBankRdBursts::1 25681 # Per bank write bursts +system.physmem.perBankRdBursts::2 25706 # Per bank write bursts +system.physmem.perBankRdBursts::3 25753 # Per bank write bursts +system.physmem.perBankRdBursts::4 25164 # Per bank write bursts +system.physmem.perBankRdBursts::5 25107 # Per bank write bursts +system.physmem.perBankRdBursts::6 24789 # Per bank write bursts +system.physmem.perBankRdBursts::7 24544 # Per bank write bursts +system.physmem.perBankRdBursts::8 25200 # Per bank write bursts +system.physmem.perBankRdBursts::9 25299 # Per bank write bursts +system.physmem.perBankRdBursts::10 25393 # Per bank write bursts +system.physmem.perBankRdBursts::11 24991 # Per bank write bursts system.physmem.perBankRdBursts::12 24525 # Per bank write bursts system.physmem.perBankRdBursts::13 25570 # Per bank write bursts system.physmem.perBankRdBursts::14 25834 # Per bank write bursts -system.physmem.perBankRdBursts::15 25739 # Per bank write bursts -system.physmem.perBankWrBursts::0 8904 # Per bank write bursts -system.physmem.perBankWrBursts::1 8550 # Per bank write bursts -system.physmem.perBankWrBursts::2 9134 # Per bank write bursts -system.physmem.perBankWrBursts::3 8817 # Per bank write bursts -system.physmem.perBankWrBursts::4 8179 # Per bank write bursts -system.physmem.perBankWrBursts::5 8016 # Per bank write bursts -system.physmem.perBankWrBursts::6 7555 # Per bank write bursts -system.physmem.perBankWrBursts::7 7380 # Per bank write bursts -system.physmem.perBankWrBursts::8 8271 # Per bank write bursts -system.physmem.perBankWrBursts::9 7751 # Per bank write bursts -system.physmem.perBankWrBursts::10 8147 # Per bank write bursts -system.physmem.perBankWrBursts::11 7871 # Per bank write bursts -system.physmem.perBankWrBursts::12 8181 # Per bank write bursts -system.physmem.perBankWrBursts::13 9046 # Per bank write bursts -system.physmem.perBankWrBursts::14 9003 # Per bank write bursts -system.physmem.perBankWrBursts::15 8880 # Per bank write bursts +system.physmem.perBankRdBursts::15 25737 # Per bank write bursts +system.physmem.perBankWrBursts::0 8901 # Per bank write bursts +system.physmem.perBankWrBursts::1 8465 # Per bank write bursts +system.physmem.perBankWrBursts::2 9022 # Per bank write bursts +system.physmem.perBankWrBursts::3 8725 # Per bank write bursts +system.physmem.perBankWrBursts::4 8062 # Per bank write bursts +system.physmem.perBankWrBursts::5 8096 # Per bank write bursts +system.physmem.perBankWrBursts::6 7614 # Per bank write bursts +system.physmem.perBankWrBursts::7 7482 # Per bank write bursts +system.physmem.perBankWrBursts::8 8269 # Per bank write bursts +system.physmem.perBankWrBursts::9 7671 # Per bank write bursts +system.physmem.perBankWrBursts::10 8104 # Per bank write bursts +system.physmem.perBankWrBursts::11 7830 # Per bank write bursts +system.physmem.perBankWrBursts::12 8200 # Per bank write bursts +system.physmem.perBankWrBursts::13 9100 # Per bank write bursts +system.physmem.perBankWrBursts::14 8920 # Per bank write bursts +system.physmem.perBankWrBursts::15 8794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 48 # Number of times write queue was full causing retry -system.physmem.totGap 1887175688500 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1887170570500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404899 # Read request sizes (log2) +system.physmem.readPktSize::6 404882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159652 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159618 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,110 +148,129 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64763 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.696185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.957517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.417041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14664 22.64% 22.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11016 17.01% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.39% 48.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3093 4.78% 52.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2464 3.80% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1908 2.95% 59.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1486 2.29% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1430 2.21% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23270 35.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64763 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4906 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 82.503669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3015.330482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4903 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads -system.physmem.totQLat 2145936500 # Total ticks spent queuing -system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4906 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4906 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.161639 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.352681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 61.394400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4666 95.11% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 49 1.00% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 4 0.08% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 5 0.10% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 7 0.14% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.02% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 2 0.04% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.14% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 21 0.43% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 22 0.45% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 9 0.18% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 10 0.20% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.04% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.06% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 19 0.39% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.18% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 5 0.10% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 13 0.26% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 3 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 5 0.10% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 8 0.16% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4906 # Writes before turning the bus around for reads +system.physmem.totQLat 2145475500 # Total ticks spent queuing +system.physmem.totMemAccLat 9735100500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5300.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24050.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -259,71 +278,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing -system.physmem.readRowHits 363622 # Number of row buffer hits during reads -system.physmem.writeRowHits 110075 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes -system.physmem.avgGap 3342790.44 # Average gap between requests +system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing +system.physmem.readRowHits 363650 # Number of row buffer hits during reads +system.physmem.writeRowHits 109622 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.25 # Row buffer hit rate for writes +system.physmem.avgGap 3343083.38 # Average gap between requests system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 239016960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130416000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577401800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 430058160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517324 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states +system.physmem_0.actBackEnergy 60604997490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079143932000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265387035290 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.518464 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795039940480 # Time in different power states system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29120110770 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579882200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433434240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.596923 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states +system.physmem_1.actBackEnergy 61665698520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078213500750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265541051285 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.600071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793490285480 # Time in different power states system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30669779520 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15007833 # Number of BP lookups -system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits +system.cpu.branchPred.lookups 15009390 # Number of BP lookups +system.cpu.branchPred.condPredicted 13017239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 373223 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9937559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5199343 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.320122 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808599 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32086 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242504 # DTB read hits -system.cpu.dtb.read_misses 17824 # DTB read misses +system.cpu.dtb.read_hits 9244571 # DTB read hits +system.cpu.dtb.read_misses 17796 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766347 # DTB read accesses -system.cpu.dtb.write_hits 6386002 # DTB write hits -system.cpu.dtb.write_misses 2322 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298454 # DTB write accesses -system.cpu.dtb.data_hits 15628506 # DTB hits -system.cpu.dtb.data_misses 20146 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064801 # DTB accesses -system.cpu.itb.fetch_hits 4019475 # ITB hits -system.cpu.itb.fetch_misses 6849 # ITB misses -system.cpu.itb.fetch_acv 693 # ITB acv -system.cpu.itb.fetch_accesses 4026324 # ITB accesses +system.cpu.dtb.read_accesses 766653 # DTB read accesses +system.cpu.dtb.write_hits 6387559 # DTB write hits +system.cpu.dtb.write_misses 2314 # DTB write misses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298430 # DTB write accesses +system.cpu.dtb.data_hits 15632130 # DTB hits +system.cpu.dtb.data_misses 20110 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1065083 # DTB accesses +system.cpu.itb.fetch_hits 4016391 # ITB hits +system.cpu.itb.fetch_misses 6902 # ITB misses +system.cpu.itb.fetch_acv 656 # ITB acv +system.cpu.itb.fetch_accesses 4023293 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -336,39 +355,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180833533 # number of cpu cycles simulated +system.cpu.numCycles 180739367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56128524 # Number of instructions committed -system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.221776 # CPI: cycles per instruction -system.cpu.ipc 0.310388 # IPC: instructions per cycle +system.cpu.committedInsts 56138893 # Number of instructions committed +system.cpu.committedOps 56138893 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2514465 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5513 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593619217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.219504 # CPI: cycles per instruction +system.cpu.ipc 0.310607 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211474 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182688 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834553179500 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80704500 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 676355500 0.04% 97.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51868058000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887178297500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693547 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814930 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -404,40 +423,40 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175529 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192427 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.callpal::total 192412 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5872 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 167 -system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 168 +system.cpu.kern.mode_switch_good::kernel 0.324762 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4171 # number of times the context was actually changed -system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked -system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395323 # number of replacements +system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393074 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36563872500 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4128201000 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846486214000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4173 # number of times the context was actually changed +system.cpu.tickCycles 84425844 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96313523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395605 # number of replacements system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13777018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1396117 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868097 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy @@ -447,72 +466,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits -system.cpu.dcache.overall_hits::total 13392427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses -system.cpu.dcache.overall_misses::total 1774786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63673578 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63673578 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816852 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816852 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578390 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578390 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182745 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182745 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198996 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198996 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13395242 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13395242 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13395242 # number of overall hits +system.cpu.dcache.overall_hits::total 13395242 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573228 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17271 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17271 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1775111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1775111 # number of overall misses +system.cpu.dcache.overall_misses::total 1775111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33009196500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33009196500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22459728804 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22459728804 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231661750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231661750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55468925304 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55468925304 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55468925304 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55468925304 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9018735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9018735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151618 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151618 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200016 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200016 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198996 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198996 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15170353 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15170353 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15170353 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15170353 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133265 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093183 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093183 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117012 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117012 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117012 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117012 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31248.144653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31248.144653 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,129 +540,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838171 # number of writebacks -system.cpu.dcache.writebacks::total 838171 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838424 # number of writebacks +system.cpu.dcache.writebacks::total 838424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127263 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268960 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 268960 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 396223 # 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number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378888 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1115769250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16346505000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17462274250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 421016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 421016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7497021141 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7497021141 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1115769250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843526141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24959295391 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1115769250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843526141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24959295391 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336297500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336297500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892281000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892281000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3228578500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3228578500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113145 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558177 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558144 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304274 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304274 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2918365 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93385664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143064988 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236450652 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41986 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3752110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104918 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3710343 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41767 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3752110 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698405000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2192449154 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2195119407 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -970,23 +989,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242104189 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024001 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302269 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729988196000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302269 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081392 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081392 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1002,8 +1021,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8768796805 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8768796805 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles @@ -1026,17 +1045,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 73108 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9982 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.323983 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1052,8 +1071,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6608090807 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6608090807 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles @@ -1068,59 +1087,59 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295757 # Transaction distribution -system.membus.trans_dist::ReadResp 295741 # Transaction distribution +system.membus.trans_dist::ReadReq 295738 # Transaction distribution +system.membus.trans_dist::ReadResp 295722 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118100 # Transaction distribution +system.membus.trans_dist::Writeback 118066 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 161 # Transaction distribution -system.membus.trans_dist::UpgradeResp 161 # Transaction distribution -system.membus.trans_dist::ReadExReq 116519 # Transaction distribution -system.membus.trans_dist::ReadExResp 116519 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116521 # Transaction distribution +system.membus.trans_dist::ReadExResp 116521 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886877 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920007 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044811 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855260 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36172316 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 581756 # Request fanout histogram +system.membus.snoop_fanout::samples 581705 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581705 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581756 # Request fanout histogram -system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581705 # Request fanout histogram +system.membus.reqLayer0.occupancy 29342000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1229889311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160670093 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 42495999 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 6bbef9107..c18c16475 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846107 # Number of seconds simulated -sim_ticks 2846106511000 # Number of ticks simulated -final_tick 2846106511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846034 # Number of seconds simulated +sim_ticks 2846033690500 # Number of ticks simulated +final_tick 2846033690500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154405 # Simulator instruction rate (inst/s) -host_op_rate 186958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3504377822 # Simulator tick rate (ticks/s) -host_mem_usage 600496 # Number of bytes of host memory used -host_seconds 812.16 # Real time elapsed on the host -sim_insts 125401163 # Number of instructions simulated -sim_ops 151839522 # Number of ops (including micro ops) simulated +host_inst_rate 166502 # Simulator instruction rate (inst/s) +host_op_rate 201645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3701777010 # Simulator tick rate (ticks/s) +host_mem_usage 652712 # Number of bytes of host memory used +host_seconds 768.83 # Real time elapsed on the host +sim_insts 128011279 # Number of instructions simulated +sim_ops 155030352 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1669760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1336112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8514432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 219648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 604112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 400768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1665600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1328952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8468032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 219456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 635604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 399104 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12756096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1669760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 219648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1889408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8854144 # Number of bytes written to this memory +system.physmem.bytes_read::total 12726924 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1665600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1885056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8843968 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8871708 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 138 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8861532 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 131 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26025 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9952 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6236 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138346 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199403 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138187 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142737 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3103 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142578 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 586682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 469453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2991607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 212259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 140813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 585236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 466949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2975380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 223330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 140232 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4481946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 586682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 663857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3110967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4471811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 585236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 662345 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3107471 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3117138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3110967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3113643 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3107471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 586682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 475610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2991607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 212273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 140813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 585236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 473106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2975380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 223344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 140232 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7599085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199856 # Number of read requests accepted -system.physmem.writeReqs 178961 # Number of write requests accepted -system.physmem.readBursts 199856 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178961 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12785664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5120 # Total number of bytes read from write queue -system.physmem.bytesWritten 9927488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12756096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11190044 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23813 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14250 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12367 # Per bank write bursts -system.physmem.perBankRdBursts::1 12533 # Per bank write bursts -system.physmem.perBankRdBursts::2 12905 # Per bank write bursts -system.physmem.perBankRdBursts::3 12918 # Per bank write bursts -system.physmem.perBankRdBursts::4 15006 # Per bank write bursts -system.physmem.perBankRdBursts::5 12397 # Per bank write bursts -system.physmem.perBankRdBursts::6 13141 # Per bank write bursts -system.physmem.perBankRdBursts::7 13266 # Per bank write bursts -system.physmem.perBankRdBursts::8 12256 # Per bank write bursts -system.physmem.perBankRdBursts::9 12318 # Per bank write bursts -system.physmem.perBankRdBursts::10 12174 # Per bank write bursts -system.physmem.perBankRdBursts::11 11385 # Per bank write bursts -system.physmem.perBankRdBursts::12 11522 # Per bank write bursts -system.physmem.perBankRdBursts::13 12342 # Per bank write bursts -system.physmem.perBankRdBursts::14 11687 # Per bank write bursts -system.physmem.perBankRdBursts::15 11559 # Per bank write bursts -system.physmem.perBankWrBursts::0 9829 # Per bank write bursts -system.physmem.perBankWrBursts::1 10209 # Per bank write bursts -system.physmem.perBankWrBursts::2 10296 # Per bank write bursts -system.physmem.perBankWrBursts::3 10100 # Per bank write bursts -system.physmem.perBankWrBursts::4 9093 # Per bank write bursts -system.physmem.perBankWrBursts::5 9584 # Per bank write bursts -system.physmem.perBankWrBursts::6 10130 # Per bank write bursts -system.physmem.perBankWrBursts::7 10398 # Per bank write bursts -system.physmem.perBankWrBursts::8 9607 # Per bank write bursts -system.physmem.perBankWrBursts::9 9596 # Per bank write bursts -system.physmem.perBankWrBursts::10 9832 # Per bank write bursts -system.physmem.perBankWrBursts::11 9707 # Per bank write bursts -system.physmem.perBankWrBursts::12 9196 # Per bank write bursts -system.physmem.perBankWrBursts::13 9428 # Per bank write bursts -system.physmem.perBankWrBursts::14 9291 # Per bank write bursts -system.physmem.perBankWrBursts::15 8821 # Per bank write bursts +system.physmem.bw_total::total 7585453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199403 # Number of read requests accepted +system.physmem.writeReqs 178802 # Number of write requests accepted +system.physmem.readBursts 199403 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178802 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12754816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 9923392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12726924 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11179868 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23728 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14293 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12446 # Per bank write bursts +system.physmem.perBankRdBursts::1 12462 # Per bank write bursts +system.physmem.perBankRdBursts::2 12648 # Per bank write bursts +system.physmem.perBankRdBursts::3 12635 # Per bank write bursts +system.physmem.perBankRdBursts::4 15144 # Per bank write bursts +system.physmem.perBankRdBursts::5 12384 # Per bank write bursts +system.physmem.perBankRdBursts::6 13114 # Per bank write bursts +system.physmem.perBankRdBursts::7 13234 # Per bank write bursts +system.physmem.perBankRdBursts::8 12297 # Per bank write bursts +system.physmem.perBankRdBursts::9 12473 # Per bank write bursts +system.physmem.perBankRdBursts::10 12152 # Per bank write bursts +system.physmem.perBankRdBursts::11 11219 # Per bank write bursts +system.physmem.perBankRdBursts::12 11569 # Per bank write bursts +system.physmem.perBankRdBursts::13 12199 # Per bank write bursts +system.physmem.perBankRdBursts::14 11629 # Per bank write bursts +system.physmem.perBankRdBursts::15 11689 # Per bank write bursts +system.physmem.perBankWrBursts::0 9980 # Per bank write bursts +system.physmem.perBankWrBursts::1 10101 # Per bank write bursts +system.physmem.perBankWrBursts::2 10187 # Per bank write bursts +system.physmem.perBankWrBursts::3 9953 # Per bank write bursts +system.physmem.perBankWrBursts::4 9212 # Per bank write bursts +system.physmem.perBankWrBursts::5 9585 # Per bank write bursts +system.physmem.perBankWrBursts::6 10195 # Per bank write bursts +system.physmem.perBankWrBursts::7 10328 # Per bank write bursts +system.physmem.perBankWrBursts::8 9559 # Per bank write bursts +system.physmem.perBankWrBursts::9 9737 # Per bank write bursts +system.physmem.perBankWrBursts::10 9778 # Per bank write bursts +system.physmem.perBankWrBursts::11 9524 # Per bank write bursts +system.physmem.perBankWrBursts::12 9387 # Per bank write bursts +system.physmem.perBankWrBursts::13 9312 # Per bank write bursts +system.physmem.perBankWrBursts::14 9249 # Per bank write bursts +system.physmem.perBankWrBursts::15 8966 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 44 # Number of times write queue was full causing retry -system.physmem.totGap 2846106004500 # Total gap between requests +system.physmem.totGap 2846033184500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 555 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199276 # Read request sizes (log2) +system.physmem.readPktSize::6 198820 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174570 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 48017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174411 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 48367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -184,160 +184,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 49 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.965201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.421700 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.995255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47261 52.01% 52.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18080 19.90% 71.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6274 6.90% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3625 3.99% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2837 3.12% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1606 1.77% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 998 1.10% 88.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1046 1.15% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9138 10.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90865 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6548 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.509316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.919891 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6546 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 62 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.526648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 138.939609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.892335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48258 52.67% 52.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17913 19.55% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6311 6.89% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3675 4.01% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2817 3.07% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1472 1.61% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1018 1.11% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1004 1.10% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9151 9.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91619 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.547670 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.789065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6548 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.689218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.640113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 40.676171 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6193 94.58% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 92 1.41% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 24 0.37% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 16 0.24% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 27 0.41% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 36 0.55% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 25 0.38% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 12 0.18% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.26% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 3 0.05% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 21 0.32% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.27% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.17% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.05% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.08% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 1 0.02% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 8 0.12% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.14% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::912-927 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6548 # Writes before turning the bus around for reads -system.physmem.totQLat 5702655246 # Total ticks spent queuing -system.physmem.totMemAccLat 9448455246 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 998880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28545.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.766554 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.625948 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.024429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6179 94.71% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 85 1.30% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 25 0.38% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 31 0.48% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 34 0.52% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 24 0.37% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 11 0.17% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 15 0.23% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 12 0.18% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 17 0.26% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 13 0.20% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.08% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 3 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.25% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::880-895 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads +system.physmem.totQLat 5653495532 # Total ticks spent queuing +system.physmem.totMemAccLat 9390258032 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 996470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28367.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47295.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47117.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 166460 # Number of row buffer hits during reads -system.physmem.writeRowHits 97567 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.89 # Row buffer hit rate for writes -system.physmem.avgGap 7513142.24 # Average gap between requests -system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359425080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 196114875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 815357400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 516060720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83232319410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634649447000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905662152725 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.569541 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719260667390 # Time in different power states -system.physmem_0.memoryStateTime::REF 95037540000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.06 # Average write queue length when enqueuing +system.physmem.readRowHits 165654 # Number of row buffer hits during reads +system.physmem.writeRowHits 97073 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes +system.physmem.avgGap 7525107.24 # Average gap between requests +system.physmem.pageHitRate 74.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 361662840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197335875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 811722600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 515425680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83071861560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634748153750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905595013505 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.562437 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719423686494 # Time in different power states +system.physmem_0.memoryStateTime::REF 95035200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31802228860 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31571473506 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 327514320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178703250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742887600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 489097440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82208245725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635547757250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905387633825 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.473086 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720763679724 # Time in different power states -system.physmem_1.memoryStateTime::REF 95037540000 # Time in different power states +system.physmem_1.actEnergy 330976800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180592500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 742762800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489317760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82401250860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635336408750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905370160670 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.483431 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720410023695 # Time in different power states +system.physmem_1.memoryStateTime::REF 95035200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30305178276 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30588353805 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -363,15 +364,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20636360 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13610949 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1051916 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13187821 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9315921 # Number of BTB hits +system.cpu0.branchPred.lookups 20699653 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13612367 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1051860 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13249801 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9339959 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.640336 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3367590 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 213586 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.491315 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3411685 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 215338 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,58 +403,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 69356 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 69356 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46232 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23124 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 69356 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 69356 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 69356 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6817 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9525.708083 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8414.892081 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6090.769517 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6639 97.39% 97.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 162 2.38% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6817 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 70748 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 70748 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47364 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23384 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 70748 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 70748 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 70748 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6854 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9215.640648 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8072.361115 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6078.265155 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6652 97.05% 97.05% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 190 2.77% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6854 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5248 76.98% 76.98% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1569 23.02% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6817 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69356 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5278 77.01% 77.01% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1576 22.99% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6854 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 70748 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69356 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6817 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 70748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6854 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6817 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 76173 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6854 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 77602 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17307432 # DTB read hits -system.cpu0.dtb.read_misses 63365 # DTB read misses -system.cpu0.dtb.write_hits 14534577 # DTB write hits -system.cpu0.dtb.write_misses 5991 # DTB write misses +system.cpu0.dtb.read_hits 17365788 # DTB read hits +system.cpu0.dtb.read_misses 64419 # DTB read misses +system.cpu0.dtb.write_hits 14563883 # DTB write hits +system.cpu0.dtb.write_misses 6329 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1432 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1922 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3519 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1310 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17370797 # DTB read accesses -system.cpu0.dtb.write_accesses 14540568 # DTB write accesses +system.cpu0.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17430207 # DTB read accesses +system.cpu0.dtb.write_accesses 14570212 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31842009 # DTB hits -system.cpu0.dtb.misses 69356 # DTB misses -system.cpu0.dtb.accesses 31911365 # DTB accesses +system.cpu0.dtb.hits 31929671 # DTB hits +system.cpu0.dtb.misses 70748 # DTB misses +system.cpu0.dtb.accesses 32000419 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,39 +484,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3833 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 3844 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3844 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9827.457901 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8615.260983 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5288.530479 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 893 37.04% 37.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1467 60.85% 97.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 9 0.37% 98.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.62% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3537 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2412 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9287.312604 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8105.691907 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5199.777734 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 996 41.29% 41.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1373 56.92% 98.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.42% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.88% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2412 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2111 87.56% 87.56% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2112 87.56% 87.56% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2412 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3844 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38721907 # ITB inst hits -system.cpu0.itb.inst_misses 3833 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2412 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2412 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6256 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38673096 # ITB inst hits +system.cpu0.itb.inst_misses 3844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -524,131 +525,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2217 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7269 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7305 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38725740 # ITB inst accesses -system.cpu0.itb.hits 38721907 # DTB hits -system.cpu0.itb.misses 3833 # DTB misses -system.cpu0.itb.accesses 38725740 # DTB accesses -system.cpu0.numCycles 164661578 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38676940 # ITB inst accesses +system.cpu0.itb.hits 38673096 # DTB hits +system.cpu0.itb.misses 3844 # DTB misses +system.cpu0.itb.accesses 38676940 # DTB accesses +system.cpu0.numCycles 164345884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79519346 # Number of instructions committed -system.cpu0.committedOps 95696233 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5042389 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1874 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527576937 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.070711 # CPI: cycles per instruction -system.cpu0.ipc 0.482926 # IPC: instructions per cycle +system.cpu0.committedInsts 79729346 # Number of instructions committed +system.cpu0.committedOps 95953153 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5189304 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527748141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.061297 # CPI: cycles per instruction +system.cpu0.ipc 0.485131 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed -system.cpu0.tickCycles 128007340 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36654238 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 714687 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.798460 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30351139 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715199 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.437334 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed +system.cpu0.tickCycles 127709647 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36636237 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 716917 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.984031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30425669 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 717429 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.409310 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.798460 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978122 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978122 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.984031 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978484 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978484 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63691793 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63691793 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15776398 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15776398 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13416114 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13416114 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321622 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 321622 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365571 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365571 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361457 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361457 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29192512 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29192512 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29514134 # number of overall hits -system.cpu0.dcache.overall_hits::total 29514134 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 464236 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 464236 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 577383 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 577383 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136671 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136671 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21082 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21082 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20299 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20299 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1041619 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1041619 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1178290 # number of overall misses -system.cpu0.dcache.overall_misses::total 1178290 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6143546304 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6143546304 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9155597212 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9155597212 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 318010226 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 318010226 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454779772 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454779772 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15299143516 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15299143516 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15299143516 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15299143516 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16240634 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16240634 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13993497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13993497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458293 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 458293 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386653 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386653 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381756 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381756 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30234131 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30234131 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30692424 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30692424 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028585 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028585 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041261 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041261 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298218 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298218 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053173 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053173 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034452 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034452 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038390 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038390 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.670599 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.670599 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15857.060585 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15857.060585 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15084.442937 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63847334 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63847334 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15827695 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15827695 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13439418 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13439418 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321505 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321505 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365521 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365521 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361496 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361496 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29267113 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29267113 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29588618 # number of overall hits +system.cpu0.dcache.overall_hits::total 29588618 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 465920 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 465920 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 577900 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 577900 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136723 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136723 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21141 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21141 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20265 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20265 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1043820 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1043820 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1180543 # number of overall misses +system.cpu0.dcache.overall_misses::total 1180543 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6144584831 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6144584831 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9172351028 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9172351028 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319190979 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 319190979 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453656289 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 453656289 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 133500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 133500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15316935859 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15316935859 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15316935859 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15316935859 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16293615 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16293615 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017318 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14017318 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458228 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 458228 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386662 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386662 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381761 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381761 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30310933 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30310933 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30769161 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30769161 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028595 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041228 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041228 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298373 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298373 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054676 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054676 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053083 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053083 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034437 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034437 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038368 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038368 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13188.068404 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13188.068404 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15871.865423 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15871.865423 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15098.196821 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15098.196821 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22386.197335 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22386.197335 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14687.849891 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14673.924488 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14673.924488 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12974.483656 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12974.483656 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,149 +658,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 514395 # number of writebacks -system.cpu0.dcache.writebacks::total 514395 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72393 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 72393 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253509 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 253509 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14653 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14653 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 325902 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 325902 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 325902 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 325902 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391843 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 391843 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323874 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323874 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103461 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 103461 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6429 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6429 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20299 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20299 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 715717 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 715717 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 819178 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 819178 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39471 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4433666662 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4433666662 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4919386398 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4919386398 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621821456 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621821456 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96313514 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96313514 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423613728 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423613728 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 205000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 205000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9353053060 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9353053060 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974874516 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10974874516 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276413999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276413999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259254500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259254500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535668499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535668499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024127 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023145 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023145 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225753 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225753 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016627 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053173 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053173 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023672 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023672 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026690 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026690 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11314.905873 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11314.905873 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15189.198262 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15189.198262 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15675.679299 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15675.679299 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14981.103438 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14981.103438 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20868.699345 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20868.699345 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 515635 # number of writebacks +system.cpu0.dcache.writebacks::total 515635 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72452 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 72452 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253659 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 253659 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14673 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14673 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 326111 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 326111 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 326111 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 326111 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393468 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 393468 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324241 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324241 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103543 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103543 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6468 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6468 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 717709 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 717709 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 821252 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 821252 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20388 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19084 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4430984378 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4430984378 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4926577100 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4926577100 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621170703 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621170703 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96485758 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96485758 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422555211 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422555211 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 127500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 127500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9357561478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9357561478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10978732181 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10978732181 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4278812500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4278812500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259105000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259105000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7537917500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7537917500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024149 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024149 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023131 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023131 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225964 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225964 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016728 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016728 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053083 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053083 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023678 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023678 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026691 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026691 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11261.358936 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11261.358936 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15194.183031 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15194.183031 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15656.980221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15656.980221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14917.402288 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14917.402288 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20851.478460 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20851.478460 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13068.088448 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13068.088448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13397.423412 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13397.423412 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209772.098450 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209772.098450 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170775.713911 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170775.713911 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190916.584302 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190916.584302 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13038.099673 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13038.099673 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13368.286690 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13368.286690 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209869.163233 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209869.163233 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170776.828757 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170776.828757 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190968.724666 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190968.724666 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1966290 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.784569 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36747505 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1966802 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.683886 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784569 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1965366 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.785087 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36699580 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1965878 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.668290 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6403533250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785087 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999580 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79395451 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79395451 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36747505 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36747505 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36747505 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36747505 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36747505 # number of overall hits -system.cpu0.icache.overall_hits::total 36747505 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1966814 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1966814 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1966814 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1966814 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1966814 # number of overall misses -system.cpu0.icache.overall_misses::total 1966814 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18563219293 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18563219293 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18563219293 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18563219293 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18563219293 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18563219293 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38714319 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38714319 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38714319 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38714319 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38714319 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38714319 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050803 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050803 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050803 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050803 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050803 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050803 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9438.217998 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9438.217998 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9438.217998 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9438.217998 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79296841 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79296841 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36699580 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36699580 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36699580 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36699580 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36699580 # number of overall hits +system.cpu0.icache.overall_hits::total 36699580 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1965894 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1965894 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1965894 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1965894 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1965894 # number of overall misses +system.cpu0.icache.overall_misses::total 1965894 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18549717200 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18549717200 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18549717200 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18549717200 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18549717200 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18549717200 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38665474 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38665474 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38665474 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38665474 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38665474 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38665474 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9435.766730 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9435.766730 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9435.766730 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9435.766730 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,425 +809,426 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1966814 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1966814 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1966814 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1966814 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1966814 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1966814 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1965894 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1965894 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1965894 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1965894 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1965894 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1965894 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16587142707 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16587142707 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16587142707 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16587142707 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16587142707 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16587142707 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16574456804 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16574456804 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16574456804 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16574456804 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16574456804 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16574456804 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050803 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050803 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050803 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8433.508561 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8431.002284 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838523 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1838641 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838784 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1838936 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 132 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 232831 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 300437 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16148.129146 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2913009 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 316676 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.198705 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2826267479000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6686.637120 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.827012 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.093258 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5824.484196 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1950.328123 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1638.759437 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.408120 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.pfSpanPage 233824 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 299625 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16147.057230 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2915503 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 315876 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.229897 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6737.365934 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.298987 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.096459 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5766.699762 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1949.490017 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1636.106070 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.411216 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003497 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355498 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119039 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.100022 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985604 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4157 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7950 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2796 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928589 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55309423 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55309423 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81547 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1895666 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 400950 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2794111276 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3958365842 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6777505118 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23091000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1937000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2794111276 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3958365842 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14425244211 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21202749329 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113041750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395186250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115835500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115835500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4115441500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4397586000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115690500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115690500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7228877250 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7511021750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.200003 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067462 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7231132000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7513276500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198775 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067265 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482455 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482455 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908863 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.908863 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155802 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155802 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075859 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.485025 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.485025 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909697 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909697 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157966 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157966 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075893 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163321 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23409.502965 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30021.261718 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58911.725424 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20151.626074 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20151.626074 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14704.905686 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14704.905686 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162956 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23314.226034 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29970.336612 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58660.903875 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20181.948232 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20181.948232 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14672.081530 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14672.081530 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38572.902454 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38572.902454 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38288.679884 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.679884 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31617.396520 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46065.994731 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201856.067294 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185122.542623 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163261.920981 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163261.920981 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183196.493717 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175384.030906 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2715743 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2641226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 514393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 305303 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89358 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43016 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112820 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297586 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284185 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3940361 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2387083 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11736 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174847 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6514027 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126091520 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86470884 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17508 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329468 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 212909380 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 677925 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4032687 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.164340 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.370584 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2719039 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2643816 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 515632 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 304029 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89544 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42988 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112734 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297842 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284446 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3938521 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2392407 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11394 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176554 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6518876 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126032640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86683880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16052 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 213062260 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 679431 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4036359 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.164506 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.370735 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3369954 83.57% 83.57% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 662733 16.43% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3372352 83.55% 83.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 664007 16.45% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4032687 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2258839735 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4036359 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2262112239 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115861999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115872000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2960687293 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2959359198 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1231161241 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1234268849 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7364989 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7386992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 92493743 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 94142746 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 18540788 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6039472 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 931744 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9588411 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 6940637 # Number of BTB hits +system.cpu1.branchPred.lookups 19410315 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6222605 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 754773 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10046576 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7244167 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.385685 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8266914 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 716215 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.105830 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8699318 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 540404 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1256,61 +1258,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26399 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26399 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19296 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7103 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26399 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26399 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26399 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2728 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9779.693548 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8843.591627 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5628.626467 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 924 33.87% 33.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 61.25% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 66 2.42% 97.54% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.13% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 1 0.04% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 26225 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26225 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19144 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26225 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26225 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26225 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9368.766324 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8408.351420 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5475.622761 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1046 38.37% 38.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1544 56.64% 95.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.49% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 59 2.16% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2728 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1622643264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1622643264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1622643264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2007 73.57% 73.57% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 721 26.43% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2728 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26399 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1584726764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1584726764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1584726764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2009 73.70% 73.70% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 717 26.30% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2726 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26225 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26399 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2728 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26225 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2726 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2728 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 29127 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28951 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10801915 # DTB read hits -system.cpu1.dtb.read_misses 24746 # DTB read misses -system.cpu1.dtb.write_hits 6805241 # DTB write hits -system.cpu1.dtb.write_misses 1653 # DTB write misses +system.cpu1.dtb.read_hits 11340769 # DTB read hits +system.cpu1.dtb.read_misses 24844 # DTB read misses +system.cpu1.dtb.write_hits 7074140 # DTB write hits +system.cpu1.dtb.write_misses 1381 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 413 # Number of TLB faults due to prefetch +system.cpu1.dtb.align_faults 202 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 452 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 271 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10826661 # DTB read accesses -system.cpu1.dtb.write_accesses 6806894 # DTB write accesses +system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11365613 # DTB read accesses +system.cpu1.dtb.write_accesses 7075521 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17607156 # DTB hits -system.cpu1.dtb.misses 26399 # DTB misses -system.cpu1.dtb.accesses 17633555 # DTB accesses +system.cpu1.dtb.hits 18414909 # DTB hits +system.cpu1.dtb.misses 26225 # DTB misses +system.cpu1.dtb.accesses 18441134 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1347,35 +1348,34 @@ system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9888.739946 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9049.592552 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4688.260195 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 127 11.35% 11.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 167 14.92% 26.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 537 47.99% 74.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 96.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 16 1.43% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 11 0.98% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1622052264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1622052264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1622052264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::samples 1118 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9560.375671 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8643.967571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4716.413998 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 181 16.19% 16.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 171 15.30% 31.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 489 43.74% 75.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 245 21.91% 97.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 97.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 14 1.25% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1118 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1584152264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1584152264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1584152264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 950 84.97% 84.97% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.03% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1118 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3378 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39782626 # ITB inst hits +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1118 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1118 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3377 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39752348 # ITB inst hits system.cpu1.itb.inst_misses 2259 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1385,130 +1385,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1864 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1892 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39784885 # ITB inst accesses -system.cpu1.itb.hits 39782626 # DTB hits +system.cpu1.itb.inst_accesses 39754607 # ITB inst accesses +system.cpu1.itb.hits 39752348 # DTB hits system.cpu1.itb.misses 2259 # DTB misses -system.cpu1.itb.accesses 39784885 # DTB accesses -system.cpu1.numCycles 114626006 # number of cpu cycles simulated +system.cpu1.itb.accesses 39754607 # DTB accesses +system.cpu1.numCycles 114648497 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 45881817 # Number of instructions committed -system.cpu1.committedOps 56143289 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 4843481 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2780 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576973220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.498288 # CPI: cycles per instruction -system.cpu1.ipc 0.400274 # IPC: instructions per cycle +system.cpu1.committedInsts 48281933 # Number of instructions committed +system.cpu1.committedOps 59077199 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5147990 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2790 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576811814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.374563 # CPI: cycles per instruction +system.cpu1.ipc 0.421130 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed -system.cpu1.tickCycles 97881179 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16744827 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 194211 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.569028 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17169326 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 194582 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 88.236970 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90524286500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.569028 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922986 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922986 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 371 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.724609 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 35245180 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 35245180 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10415746 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10415746 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6512410 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6512410 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50058 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50058 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80074 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80074 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71526 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71526 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 16928156 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 16928156 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 16978214 # number of overall hits -system.cpu1.dcache.overall_hits::total 16978214 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 157191 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 157191 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144867 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144867 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30819 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30819 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16921 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16921 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23675 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23675 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 302058 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 302058 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 332877 # number of overall misses -system.cpu1.dcache.overall_misses::total 332877 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2309301217 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2309301217 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3857781581 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3857781581 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316145498 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 316145498 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557553671 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557553671 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 527500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 527500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6167082798 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6167082798 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6167082798 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6167082798 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10572937 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10572937 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6657277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6657277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80877 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80877 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96995 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96995 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95201 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95201 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17230214 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17230214 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17311091 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17311091 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014867 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014867 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021761 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021761 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381060 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381060 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174452 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174452 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248684 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248684 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017531 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.017531 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019229 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.019229 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14691.052395 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14691.052395 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26629.816183 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26629.816183 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18683.617871 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18683.617871 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23550.313453 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23550.313453 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2790 # number of quiesce instructions executed +system.cpu1.tickCycles 97744251 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 16904246 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 195096 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.102569 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17976294 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195460 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 91.969170 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90457158500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.102569 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925982 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925982 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36856215 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36856215 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10952474 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10952474 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6779584 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6779584 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50047 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50047 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80034 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80034 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71497 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71497 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17732058 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17732058 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17782105 # number of overall hits +system.cpu1.dcache.overall_hits::total 17782105 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 158503 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 158503 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 144597 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 144597 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30804 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30804 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16970 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16970 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23713 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23713 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 303100 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 303100 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 333904 # number of overall misses +system.cpu1.dcache.overall_misses::total 333904 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2370328398 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2370328398 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3872727461 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3872727461 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316464239 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 316464239 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 558424163 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 558424163 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 271500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 271500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6243055859 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6243055859 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6243055859 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6243055859 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11110977 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11110977 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6924181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6924181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80851 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80851 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97004 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97004 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95210 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95210 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18035158 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18035158 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18116009 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18116009 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014265 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.014265 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020883 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.020883 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380997 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380997 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174941 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174941 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249060 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249060 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016806 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016806 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018431 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018431 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14954.470250 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14954.470250 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26782.903248 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26782.903248 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18648.452504 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18648.452504 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23549.283642 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23549.283642 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20416.882844 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20416.882844 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18526.611325 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18526.611325 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20597.346945 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20597.346945 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18697.158042 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18697.158042 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1517,148 +1517,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 117850 # number of writebacks -system.cpu1.dcache.writebacks::total 117850 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15942 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15942 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52278 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52278 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 68220 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 68220 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 68220 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 68220 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141249 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 141249 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92589 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92589 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4886 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4886 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23675 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23675 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 233838 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 233838 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263747 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263747 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14605 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1867063577 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1867063577 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2294961861 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2294961861 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 485499507 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 485499507 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80204246 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80204246 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520729829 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520729829 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 512500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 512500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4162025438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4162025438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4647524945 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4647524945 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322107500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322107500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843997501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843997501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166105001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166105001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013359 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013359 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013908 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013908 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369808 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369808 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050374 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050374 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248684 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248684 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013571 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013571 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015236 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13218.242798 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24786.549817 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16232.555652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16415.113795 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.924139 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.924139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119832 # number of writebacks +system.cpu1.dcache.writebacks::total 119832 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16048 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16048 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52216 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52216 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12045 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12045 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 68264 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 68264 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 68264 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 68264 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 142455 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 142455 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92381 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92381 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 234836 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 234836 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 264785 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 264785 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14604 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14604 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11935 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26539 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26539 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1925101376 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1925101376 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2304194019 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2304194019 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 483540014 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 483540014 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80690501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80690501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521529337 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521529337 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 262500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 262500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4229295395 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4229295395 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4712835409 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4712835409 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2321932001 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2321932001 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843920001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843920001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4165852002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4165852002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012821 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012821 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013342 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013342 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370422 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370422 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050771 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050771 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013021 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013021 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014616 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014616 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13513.750841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13513.750841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24942.293534 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24942.293534 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16145.447728 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16145.447728 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.858071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.858071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21993.393371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21993.393371 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17798.755711 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17798.755711 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17621.148089 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17621.148089 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158994.008901 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158994.008901 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154490.407255 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154490.407255 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156968.652312 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156968.652312 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18009.570062 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18009.570062 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17798.725037 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17798.725037 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158992.878732 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158992.878732 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154496.858065 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154496.858065 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156970.948491 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156970.948491 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 947892 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.324313 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38832195 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 948404 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.944782 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72125006000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324313 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 948604 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.330921 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38801180 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 949116 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.881389 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72079277000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.330921 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975256 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975256 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80509602 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80509602 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38832195 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38832195 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38832195 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38832195 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38832195 # number of overall hits -system.cpu1.icache.overall_hits::total 38832195 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 948404 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 948404 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 948404 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 948404 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 948404 # number of overall misses -system.cpu1.icache.overall_misses::total 948404 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8190397665 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8190397665 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8190397665 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8190397665 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8190397665 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8190397665 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39780599 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39780599 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39780599 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39780599 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39780599 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39780599 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023841 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023841 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023841 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023841 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023841 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023841 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8635.979672 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8635.979672 # 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number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 949116 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 949116 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7240674335 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7240674335 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7240674335 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7240674335 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10378250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10378250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10378250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023877 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023877 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023877 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7636.413085 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92662.946429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92662.946429 # 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number of replacements -system.cpu1.l2cache.tags.tagsinuse 15316.530997 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1176536 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69755 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.866691 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58593 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54928 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15357.291554 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1177888 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69820 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.870352 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7883.130354 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 45.774786 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.102173 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4372.978904 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2161.890501 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 852.654278 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.481148 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002794 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 7821.827388 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.231580 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.097899 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4362.380441 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2262.649841 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 872.104404 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.477406 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002333 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266905 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131951 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052042 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934847 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1060 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13867 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 654 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 402 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266259 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138101 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.053229 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.937335 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13777 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 657 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 409 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6188 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7370 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064697 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.846375 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22471002 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 22471002 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28799 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2667 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927404 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 105047 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1063917 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 117850 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 117850 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1629 # 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mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104485 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949080 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949080 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958504 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958504 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.556029 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.556029 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104976 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123653 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124005 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16091.003046 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18882.626836 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39809.965816 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15942.372819 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942.372819 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15108.505390 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.505390 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530 # average overall mshr uncacheable latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32388.339027 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32388.339027 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22541.587713 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25191.495009 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150992.382156 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150484.404662 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146986.216925 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146986.216925 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149190.747504 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148917.826648 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1570481 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1215284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 117850 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42118 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85085 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67041 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1897032 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 831140 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7228 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62942 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2798342 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60705024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25653404 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86487752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 646083 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1988037 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.303225 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.459652 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1571398 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1216942 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11935 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 119832 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 28997 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76686 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42144 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86299 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66899 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1898456 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835008 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7108 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62262 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2802834 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60750592 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25843924 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11084 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115824 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86721424 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 645948 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1991449 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.302505 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459343 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1385215 69.68% 69.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 602822 30.32% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1389026 69.75% 69.75% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 602423 30.25% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1988037 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 835355978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1991449 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 839147473 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80571000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80233998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1423456915 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1424533908 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 410007475 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 411735495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4338499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4337999 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33513487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33317735 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31003 # Transaction distribution system.iobus.trans_dist::ReadResp 31003 # Transaction distribution @@ -2169,23 +2168,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198954212 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198974708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36786767 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36789763 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 14.479130 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.479314 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270363169000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904946 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904946 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270323444000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479314 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904957 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904957 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2199,14 +2198,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31382127 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31382127 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655722318 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6655722318 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31382127 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31382127 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31382127 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31382127 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31377127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31377127 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657460818 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657460818 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31377127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31377127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31377127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31377127 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2223,19 +2222,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129144.555556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129144.555556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183737.917348 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183737.917348 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129144.555556 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129144.555556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22459 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129123.979424 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129123.979424 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.910391 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.910391 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129123.979424 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129123.979424 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22685 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.547813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.627228 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2249,14 +2248,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18687627 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18687627 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772040352 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772040352 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18687627 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18687627 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18687627 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18687627 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18676627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18676627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773786844 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773786844 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18676627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18676627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18676627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18676627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2265,304 +2264,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76903.814815 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76903.814815 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131736.979682 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131736.979682 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76858.547325 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76858.547325 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.193352 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.193352 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 136145 # number of replacements -system.l2c.tags.tagsinuse 64036.316369 # Cycle average of tags in use -system.l2c.tags.total_refs 380367 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200629 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.895872 # Average number of references to valid blocks. +system.l2c.tags.replacements 135621 # number of replacements +system.l2c.tags.tagsinuse 64040.319526 # Cycle average of tags in use +system.l2c.tags.total_refs 379947 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200130 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.898501 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12112.427093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.878570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.028766 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8551.494132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2840.139732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35681.498153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.446887 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2203.793190 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 582.329943 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1973.279904 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184821 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12350.088291 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.394364 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8481.237345 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2821.026897 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35473.229907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.484833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2216.311582 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 599.378307 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2022.137051 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.188447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.130485 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043337 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544456 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.033627 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977117 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30113 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5558 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24416 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.129413 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043045 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.541279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033818 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009146 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977178 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29987 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34466 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 143 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5502 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24342 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3300 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30690 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.459488 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.523788 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5288124 # Number of tag accesses -system.l2c.tags.data_accesses 5288124 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 404 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 85 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 48346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 49709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47536 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 123 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17643 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5444 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178619 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232833 # number of Writeback hits -system.l2c.Writeback_hits::total 232833 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2833 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 761 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3594 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 161 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 327 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4206 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1689 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5895 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 404 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 48346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 53915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47536 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 123 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17643 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10986 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5444 # number of demand (read+write) hits -system.l2c.demand_hits::total 184514 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 404 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits -system.l2c.overall_hits::cpu0.inst 48346 # number of overall hits -system.l2c.overall_hits::cpu0.data 53915 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47536 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 123 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17643 # number of overall hits -system.l2c.overall_hits::cpu1.data 10986 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5444 # number of overall hits -system.l2c.overall_hits::total 184514 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 138 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3362 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30784 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.457565 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.525909 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5285534 # Number of tag accesses +system.l2c.tags.data_accesses 5285534 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 409 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 48212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 49449 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47699 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 23 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17668 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9341 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5522 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178518 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232415 # number of Writeback hits +system.l2c.Writeback_hits::total 232415 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3312 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.515428 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.281325 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.462761 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.515428 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6479122500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6862750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453026252 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10143719502 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.164896 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.146629 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.496772 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.736767 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788823 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.748651 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.806413 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.888581 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858330 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722693 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.834399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.766375 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.514910 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.514910 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75982.212960 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76676.438163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87876.258454 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17838.894532 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.648054 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17821.381132 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17884.067432 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17761.044917 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.659715 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79473.301316 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68960.332013 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74999.046028 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75668.182917 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75993.925234 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87614.772950 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.601510 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.664169 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17826.614124 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17914.104566 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.679907 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.057565 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79530.822396 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69677.179063 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75335.612392 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182315.479694 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131494.572358 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152037.303759 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144732.472228 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128451.948136 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138468.309778 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164144.773510 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130126.102352 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145980.104221 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215398 # Transaction distribution -system.membus.trans_dist::ReadResp 215398 # Transaction distribution -system.membus.trans_dist::WriteReq 31021 # Transaction distribution -system.membus.trans_dist::WriteResp 31021 # Transaction distribution -system.membus.trans_dist::Writeback 138346 # Transaction distribution +system.membus.trans_dist::ReadReq 214941 # Transaction distribution +system.membus.trans_dist::ReadResp 214941 # Transaction distribution +system.membus.trans_dist::WriteReq 31019 # Transaction distribution +system.membus.trans_dist::WriteResp 31019 # Transaction distribution +system.membus.trans_dist::Writeback 138187 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76455 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40833 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14266 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 39995 # Transaction distribution -system.membus.trans_dist::ReadExResp 19465 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76766 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40830 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14310 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 39945 # Transaction distribution +system.membus.trans_dist::ReadExResp 19469 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663047 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 785159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662279 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 784385 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 894055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 893281 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19310684 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19503012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19271336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19463652 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24138468 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 124155 # Total snoops (count) -system.membus.snoop_fanout::samples 578323 # Request fanout histogram +system.membus.pkt_size::total 24099108 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124366 # Total snoops (count) +system.membus.snoop_fanout::samples 577962 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 578323 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 577962 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 578323 # Request fanout histogram -system.membus.reqLayer0.occupancy 88747000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 577962 # Request fanout histogram +system.membus.reqLayer0.occupancy 91190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12490999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12300498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1169123868 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1168075116 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1173969642 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1171902830 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37485233 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37484237 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2859,44 +2858,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516846 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516831 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31021 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232833 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79939 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41160 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 121099 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51726 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51726 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083746 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338123 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1421869 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34155096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5564428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39719524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 288847 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 989795 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036873 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.188451 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 516760 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516745 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31019 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232415 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80723 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41154 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 121877 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51826 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51826 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082609 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339699 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1422308 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34055964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5608584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39664548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289563 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 990166 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036865 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.188429 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 953298 96.31% 96.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36497 3.69% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 953664 96.31% 96.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36502 3.69% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 989795 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 786931704 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 990166 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 786658690 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 682239026 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 681591350 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 258695257 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 259907159 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 60c7bcf62..99269b180 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852796 # Number of seconds simulated -sim_ticks 2852795541500 # Number of ticks simulated -final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852793 # Number of seconds simulated +sim_ticks 2852793222500 # Number of ticks simulated +final_tick 2852793222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152327 # Simulator instruction rate (inst/s) -host_op_rate 184181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3876544573 # Simulator tick rate (ticks/s) -host_mem_usage 573860 # Number of bytes of host memory used -host_seconds 735.91 # Real time elapsed on the host -sim_insts 112099513 # Number of instructions simulated -sim_ops 135541235 # Number of ops (including micro ops) simulated +host_inst_rate 170913 # Simulator instruction rate (inst/s) +host_op_rate 206647 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4363431399 # Simulator tick rate (ticks/s) +host_mem_usage 626396 # Number of bytes of host memory used +host_seconds 653.80 # Real time elapsed on the host +sim_insts 111742418 # Number of instructions simulated +sim_ops 135104867 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1671744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9171756 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory +system.physmem.bytes_read::total 10852140 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1671744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1671744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7973376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7990900 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143830 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170086 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124584 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128965 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3215009 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3804040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794937 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2801079 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3221152 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169771 # Number of read requests accepted -system.physmem.writeReqs 164823 # Number of write requests accepted -system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10712 # Per bank write bursts -system.physmem.perBankRdBursts::1 10437 # Per bank write bursts -system.physmem.perBankRdBursts::2 10571 # Per bank write bursts -system.physmem.perBankRdBursts::3 10533 # Per bank write bursts -system.physmem.perBankRdBursts::4 13317 # Per bank write bursts -system.physmem.perBankRdBursts::5 10551 # Per bank write bursts -system.physmem.perBankRdBursts::6 11242 # Per bank write bursts -system.physmem.perBankRdBursts::7 11054 # Per bank write bursts -system.physmem.perBankRdBursts::8 10299 # Per bank write bursts -system.physmem.perBankRdBursts::9 10415 # Per bank write bursts -system.physmem.perBankRdBursts::10 10045 # Per bank write bursts -system.physmem.perBankRdBursts::11 9308 # Per bank write bursts -system.physmem.perBankRdBursts::12 10198 # Per bank write bursts -system.physmem.perBankRdBursts::13 10751 # Per bank write bursts -system.physmem.perBankRdBursts::14 10066 # Per bank write bursts -system.physmem.perBankRdBursts::15 10147 # Per bank write bursts -system.physmem.perBankWrBursts::0 8889 # Per bank write bursts -system.physmem.perBankWrBursts::1 8834 # Per bank write bursts -system.physmem.perBankWrBursts::2 9167 # Per bank write bursts -system.physmem.perBankWrBursts::3 9119 # Per bank write bursts -system.physmem.perBankWrBursts::4 8534 # Per bank write bursts -system.physmem.perBankWrBursts::5 8844 # Per bank write bursts -system.physmem.perBankWrBursts::6 9286 # Per bank write bursts -system.physmem.perBankWrBursts::7 9148 # Per bank write bursts -system.physmem.perBankWrBursts::8 9054 # Per bank write bursts -system.physmem.perBankWrBursts::9 9024 # Per bank write bursts -system.physmem.perBankWrBursts::10 8594 # Per bank write bursts -system.physmem.perBankWrBursts::11 8355 # Per bank write bursts -system.physmem.perBankWrBursts::12 8781 # Per bank write bursts -system.physmem.perBankWrBursts::13 8812 # Per bank write bursts -system.physmem.perBankWrBursts::14 8169 # Per bank write bursts -system.physmem.perBankWrBursts::15 8428 # Per bank write bursts +system.physmem.bw_total::total 6605119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170086 # Number of read requests accepted +system.physmem.writeReqs 165189 # Number of write requests accepted +system.physmem.readBursts 170086 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165189 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10878016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 9060544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10852140 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10309236 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23589 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10719 # Per bank write bursts +system.physmem.perBankRdBursts::1 10428 # Per bank write bursts +system.physmem.perBankRdBursts::2 10712 # Per bank write bursts +system.physmem.perBankRdBursts::3 10613 # Per bank write bursts +system.physmem.perBankRdBursts::4 13554 # Per bank write bursts +system.physmem.perBankRdBursts::5 10863 # Per bank write bursts +system.physmem.perBankRdBursts::6 10988 # Per bank write bursts +system.physmem.perBankRdBursts::7 10936 # Per bank write bursts +system.physmem.perBankRdBursts::8 10331 # Per bank write bursts +system.physmem.perBankRdBursts::9 10532 # Per bank write bursts +system.physmem.perBankRdBursts::10 10066 # Per bank write bursts +system.physmem.perBankRdBursts::11 9201 # Per bank write bursts +system.physmem.perBankRdBursts::12 10334 # Per bank write bursts +system.physmem.perBankRdBursts::13 10898 # Per bank write bursts +system.physmem.perBankRdBursts::14 9868 # Per bank write bursts +system.physmem.perBankRdBursts::15 9926 # Per bank write bursts +system.physmem.perBankWrBursts::0 8834 # Per bank write bursts +system.physmem.perBankWrBursts::1 8868 # Per bank write bursts +system.physmem.perBankWrBursts::2 9254 # Per bank write bursts +system.physmem.perBankWrBursts::3 9172 # Per bank write bursts +system.physmem.perBankWrBursts::4 8841 # Per bank write bursts +system.physmem.perBankWrBursts::5 9153 # Per bank write bursts +system.physmem.perBankWrBursts::6 9171 # Per bank write bursts +system.physmem.perBankWrBursts::7 9059 # Per bank write bursts +system.physmem.perBankWrBursts::8 9082 # Per bank write bursts +system.physmem.perBankWrBursts::9 9087 # Per bank write bursts +system.physmem.perBankWrBursts::10 8650 # Per bank write bursts +system.physmem.perBankWrBursts::11 8253 # Per bank write bursts +system.physmem.perBankWrBursts::12 8834 # Per bank write bursts +system.physmem.perBankWrBursts::13 9086 # Per bank write bursts +system.physmem.perBankWrBursts::14 8043 # Per bank write bursts +system.physmem.perBankWrBursts::15 8184 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51 # Number of times write queue was full causing retry -system.physmem.totGap 2852795136500 # Total gap between requests +system.physmem.numWrRetry 57 # Number of times write queue was full causing retry +system.physmem.totGap 2852792816500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169214 # Read request sizes (log2) +system.physmem.readPktSize::6 169529 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160442 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160808 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,162 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1399 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::37 2324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 161 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.665933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.077551 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.586947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22269 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14610 23.64% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6509 10.53% 70.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3452 5.59% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2793 4.52% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1471 2.38% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1217 1.97% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1102 1.78% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8370 13.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5884 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.884772 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 583.981749 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5883 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5884 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5884 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.060333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.369950 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.410965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5554 94.39% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.50% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 18 0.31% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 15 0.25% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 30 0.51% 96.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 27 0.46% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 26 0.44% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 9 0.15% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 10 0.17% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 1 0.02% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 18 0.31% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.20% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.14% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.08% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.10% 99.15% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads -system.physmem.totQLat 1681739444 # Total ticks spent queuing -system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 3 0.05% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.27% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5884 # Writes before turning the bus around for reads +system.physmem.totQLat 1705654500 # Total ticks spent queuing +system.physmem.totMemAccLat 4892573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849845000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10035.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28785.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing -system.physmem.readRowHits 140075 # Number of row buffer hits during reads -system.physmem.writeRowHits 109026 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes -system.physmem.avgGap 8526139.55 # Average gap between requests -system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ) +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.27 # Average write queue length when enqueuing +system.physmem.readRowHits 140294 # Number of row buffer hits during reads +system.physmem.writeRowHits 109452 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.30 # Row buffer hit rate for writes +system.physmem.avgGap 8508814.60 # Average gap between requests +system.physmem.pageHitRate 80.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242736480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132445500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692741400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468840960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.449413 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states +system.physmem_0.actBackEnergy 83545935120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638387378750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909800359490 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.450312 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725465336224 # Time in different power states system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32062608776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 224418600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122450625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 633009000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 448539120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.351340 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states +system.physmem_1.actBackEnergy 82219424850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639550984250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909529107725 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.355229 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727414398224 # Time in different power states system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30117847276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -334,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31028841 # Number of BP lookups -system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits +system.cpu.branchPred.lookups 31001883 # Number of BP lookups +system.cpu.branchPred.condPredicted 16796453 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2502337 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18460820 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13284720 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.961701 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7904518 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1496209 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,58 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66007 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66819 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66819 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43911 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22908 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66819 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66819 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66819 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7827 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11026.574677 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8748.919938 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7443.454079 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6102 77.96% 77.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 21.96% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7827 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6438 82.25% 82.25% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1389 17.75% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7827 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66819 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66819 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7827 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7827 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74646 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24765986 # DTB read hits -system.cpu.dtb.read_misses 59321 # DTB read misses -system.cpu.dtb.write_hits 19441821 # DTB write hits -system.cpu.dtb.write_misses 6686 # DTB write misses +system.cpu.dtb.read_hits 24698795 # DTB read hits +system.cpu.dtb.read_misses 59886 # DTB read misses +system.cpu.dtb.write_hits 19408206 # DTB write hits +system.cpu.dtb.write_misses 6933 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4360 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1246 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1786 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24825307 # DTB read accesses -system.cpu.dtb.write_accesses 19448507 # DTB write accesses +system.cpu.dtb.perms_faults 745 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24758681 # DTB read accesses +system.cpu.dtb.write_accesses 19415139 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44207807 # DTB hits -system.cpu.dtb.misses 66007 # DTB misses -system.cpu.dtb.accesses 44273814 # DTB accesses +system.cpu.dtb.hits 44107001 # DTB hits +system.cpu.dtb.misses 66819 # DTB misses +system.cpu.dtb.accesses 44173820 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -454,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5444 # Table walker walks requested -system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5459 # Table walker walks requested +system.cpu.itb.walker.walksShort 5459 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5138 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5459 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5459 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5459 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3190 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11236.050157 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8968.317634 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7059.322929 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1291 40.47% 40.47% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1179 36.96% 77.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 719 22.54% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3190 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2880 90.28% 90.28% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3190 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5459 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5459 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57608448 # ITB inst hits -system.cpu.itb.inst_misses 5444 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3190 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3190 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8649 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57544146 # ITB inst hits +system.cpu.itb.inst_misses 5459 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -497,270 +497,270 @@ system.cpu.itb.flush_entries 2978 # Nu system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8374 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57613892 # ITB inst accesses -system.cpu.itb.hits 57608448 # DTB hits -system.cpu.itb.misses 5444 # DTB misses -system.cpu.itb.accesses 57613892 # DTB accesses -system.cpu.numCycles 315454477 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57549605 # ITB inst accesses +system.cpu.itb.hits 57544146 # DTB hits +system.cpu.itb.misses 5459 # DTB misses +system.cpu.itb.accesses 57549605 # DTB accesses +system.cpu.numCycles 315425036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112099513 # Number of instructions committed -system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111742418 # Number of instructions committed +system.cpu.committedOps 135104867 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7746377 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.814058 # CPI: cycles per instruction -system.cpu.ipc 0.355359 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390221882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.822787 # CPI: cycles per instruction +system.cpu.ipc 0.354260 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842088 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks. +system.cpu.tickCycles 227203186 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88221850 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843958 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947848 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42509637 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844470 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.338836 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947848 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460198 # 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Number of tag accesses +system.cpu.dcache.tags.data_accesses 175807461 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23001062 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23001062 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18245677 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18245677 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356392 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356392 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443406 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443406 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460170 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460170 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41246739 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41246739 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466021 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460200 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460200 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42400072 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42400072 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42926578 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42926578 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020868 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020868 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029087 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029087 # 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number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285183750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 285183750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30700950373 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30700950373 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30700950373 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30700950373 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23494581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23494581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18793465 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18793465 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526532 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526532 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465991 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465991 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460172 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460172 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42288046 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42288046 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42814578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42814578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029148 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029148 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323133 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.323133 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048467 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024519 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024519 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028175 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028175 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14771.398719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14771.398719 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42599.937549 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42599.937549 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12688.693490 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12688.693490 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29435.693461 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29435.693461 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25301.667843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25301.667843 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 252 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024624 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024624 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028295 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028295 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14798.865071 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14798.865071 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42712.562674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42712.562674 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12627.130839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12627.130839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29483.092280 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29483.092280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25342.380123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25342.380123 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.900000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697883 # number of writebacks -system.cpu.dcache.writebacks::total 697883 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74969 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74969 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105928000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18030704801 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18030704801 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19593733551 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19593733551 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833996750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833996750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510200000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510200000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10344196750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10344196750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231528 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231528 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017734 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017734 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25108.027762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23323.994988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23323.994988 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187518.721087 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187518.721087 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163508.429105 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163508.429105 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176238.451909 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016959 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016959 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2897206 # number of replacements +system.cpu.icache.tags.tagsinuse 511.401811 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54637656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897718 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.855408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15497791250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.401811 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998832 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54702268 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400789000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592518750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151344500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151344500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5397684500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5589414250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151492500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151492500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9552133500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743863250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025818 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982004 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982004 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9549177000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9740906750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025883 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.980898 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.980898 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044072 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044072 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67689.004746 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71214.411931 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69055.756834 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17774.445922 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17774.445922 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65003.775370 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65003.775370 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67690.753082 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71585.540217 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69190.197709 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17770.383339 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17770.383339 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65128.397654 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65128.397654 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173502.602159 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163047.193878 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150503.734184 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150503.734184 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173402.868800 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162956.683673 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150509.099808 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150509.099808 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162647.153004 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157408.444161 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3581126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3581032 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 699616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2827 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60910 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295959 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2511831 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15055 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160898 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8489559 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185655872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99015325 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284973713 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61355 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4643370 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.029465 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.169105 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4506555 97.05% 97.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 136815 2.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4643370 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3016847250 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4356806979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1344182949 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10597250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89732000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1231,23 +1231,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198883474 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031423 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270485733000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031423 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064464 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064464 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1261,14 +1261,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6650280092 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6650280092 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1285,19 +1285,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183587.679218 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183587.679218 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22674 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3485 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.506169 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1311,14 +1311,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766620104 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766620104 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1327,66 +1327,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131587.348277 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131587.348277 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71735 # Transaction distribution -system.membus.trans_dist::ReadResp 71735 # Transaction distribution +system.membus.trans_dist::ReadReq 71811 # Transaction distribution +system.membus.trans_dist::ReadResp 71811 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124218 # Transaction distribution +system.membus.trans_dist::Writeback 124584 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution -system.membus.trans_dist::ReadExReq 129118 # Transaction distribution -system.membus.trans_dist::ReadExResp 129118 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution +system.membus.trans_dist::ReadExReq 129358 # Transaction distribution +system.membus.trans_dist::ReadExResp 129358 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554330 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 663217 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16689629 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 393527 # Request fanout histogram +system.membus.pkt_size::total 21325085 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 507 # Total snoops (count) +system.membus.snoop_fanout::samples 394211 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 394211 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 393527 # Request fanout histogram -system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 394211 # Request fanout histogram +system.membus.reqLayer0.occupancy 87591000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1723500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1025789403 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 997949408 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 5aa558433..99e4aebe7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.365947 # Number of seconds simulated -sim_ticks 47365946685500 # Number of ticks simulated -final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.477179 # Number of seconds simulated +sim_ticks 47477179149500 # Number of ticks simulated +final_tick 47477179149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174192 # Simulator instruction rate (inst/s) -host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9672451523 # Simulator tick rate (ticks/s) -host_mem_usage 763596 # Number of bytes of host memory used -host_seconds 4897.00 # Real time elapsed on the host -sim_insts 853019792 # Number of instructions simulated -sim_ops 1003201701 # Number of ops (including micro ops) simulated +host_inst_rate 181000 # Simulator instruction rate (inst/s) +host_op_rate 212908 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9614368962 # Simulator tick rate (ticks/s) +host_mem_usage 772236 # Number of bytes of host memory used +host_seconds 4938.15 # Real time elapsed on the host +sim_insts 893806699 # Number of instructions simulated +sim_ops 1051369194 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory -system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 125376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 108736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7965248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14333320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15086080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 149568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3627008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11510096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14847104 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436288 # Number of bytes read from this memory +system.physmem.bytes_read::total 68325080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7965248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3627008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11592256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 80335616 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory -system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 80356200 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 124457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 223971 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 235720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 179858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 231986 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6817 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1067605 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1255244 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1257818 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 167770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 301899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 317754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 242434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 312721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1439114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 167770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1692089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 778555 # Number of read requests accepted -system.physmem.writeReqs 1622091 # Number of write requests accepted -system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 42060 # Per bank write bursts -system.physmem.perBankRdBursts::1 53156 # Per bank write bursts -system.physmem.perBankRdBursts::2 42442 # Per bank write bursts -system.physmem.perBankRdBursts::3 47567 # Per bank write bursts -system.physmem.perBankRdBursts::4 45723 # Per bank write bursts -system.physmem.perBankRdBursts::5 54413 # Per bank write bursts -system.physmem.perBankRdBursts::6 50594 # Per bank write bursts -system.physmem.perBankRdBursts::7 44772 # Per bank write bursts -system.physmem.perBankRdBursts::8 41306 # Per bank write bursts -system.physmem.perBankRdBursts::9 93457 # Per bank write bursts -system.physmem.perBankRdBursts::10 34541 # Per bank write bursts -system.physmem.perBankRdBursts::11 47870 # Per bank write bursts -system.physmem.perBankRdBursts::12 47765 # Per bank write bursts -system.physmem.perBankRdBursts::13 46143 # Per bank write bursts -system.physmem.perBankRdBursts::14 39677 # Per bank write bursts -system.physmem.perBankRdBursts::15 46694 # Per bank write bursts -system.physmem.perBankWrBursts::0 94318 # Per bank write bursts -system.physmem.perBankWrBursts::1 104450 # Per bank write bursts -system.physmem.perBankWrBursts::2 99318 # Per bank write bursts -system.physmem.perBankWrBursts::3 101345 # Per bank write bursts -system.physmem.perBankWrBursts::4 99792 # Per bank write bursts -system.physmem.perBankWrBursts::5 104837 # Per bank write bursts -system.physmem.perBankWrBursts::6 100210 # Per bank write bursts -system.physmem.perBankWrBursts::7 98464 # Per bank write bursts -system.physmem.perBankWrBursts::8 93421 # Per bank write bursts -system.physmem.perBankWrBursts::9 95649 # Per bank write bursts -system.physmem.perBankWrBursts::10 88541 # Per bank write bursts -system.physmem.perBankWrBursts::11 99820 # Per bank write bursts -system.physmem.perBankWrBursts::12 96824 # Per bank write bursts -system.physmem.perBankWrBursts::13 96750 # Per bank write bursts -system.physmem.perBankWrBursts::14 94484 # Per bank write bursts -system.physmem.perBankWrBursts::15 104479 # Per bank write bursts +system.physmem.bw_write::total 1692523 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1692089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 167770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 302333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 317754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 242434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 312721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3131637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1067605 # Number of read requests accepted +system.physmem.writeReqs 1929186 # Number of write requests accepted +system.physmem.readBursts 1067605 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1929186 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68309056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 120257344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68325080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123323752 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50133 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 117648 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 62386 # Per bank write bursts +system.physmem.perBankRdBursts::1 65796 # Per bank write bursts +system.physmem.perBankRdBursts::2 60427 # Per bank write bursts +system.physmem.perBankRdBursts::3 63507 # Per bank write bursts +system.physmem.perBankRdBursts::4 66319 # Per bank write bursts +system.physmem.perBankRdBursts::5 73621 # Per bank write bursts +system.physmem.perBankRdBursts::6 69221 # Per bank write bursts +system.physmem.perBankRdBursts::7 63591 # Per bank write bursts +system.physmem.perBankRdBursts::8 61143 # Per bank write bursts +system.physmem.perBankRdBursts::9 115825 # Per bank write bursts +system.physmem.perBankRdBursts::10 59973 # Per bank write bursts +system.physmem.perBankRdBursts::11 66407 # Per bank write bursts +system.physmem.perBankRdBursts::12 58867 # Per bank write bursts +system.physmem.perBankRdBursts::13 61123 # Per bank write bursts +system.physmem.perBankRdBursts::14 58743 # Per bank write bursts +system.physmem.perBankRdBursts::15 60380 # Per bank write bursts +system.physmem.perBankWrBursts::0 115877 # Per bank write bursts +system.physmem.perBankWrBursts::1 122877 # Per bank write bursts +system.physmem.perBankWrBursts::2 115996 # Per bank write bursts +system.physmem.perBankWrBursts::3 119851 # Per bank write bursts +system.physmem.perBankWrBursts::4 119313 # Per bank write bursts +system.physmem.perBankWrBursts::5 126432 # Per bank write bursts +system.physmem.perBankWrBursts::6 119028 # Per bank write bursts +system.physmem.perBankWrBursts::7 120185 # Per bank write bursts +system.physmem.perBankWrBursts::8 118113 # Per bank write bursts +system.physmem.perBankWrBursts::9 119452 # Per bank write bursts +system.physmem.perBankWrBursts::10 113141 # Per bank write bursts +system.physmem.perBankWrBursts::11 117109 # Per bank write bursts +system.physmem.perBankWrBursts::12 112676 # Per bank write bursts +system.physmem.perBankWrBursts::13 113553 # Per bank write bursts +system.physmem.perBankWrBursts::14 112771 # Per bank write bursts +system.physmem.perBankWrBursts::15 112647 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 276 # Number of times write queue was full causing retry -system.physmem.totGap 47365944763000 # Total gap between requests +system.physmem.numWrRetry 226 # Number of times write queue was full causing retry +system.physmem.totGap 47477177227000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 778525 # Read request sizes (log2) +system.physmem.readPktSize::6 1067575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1619517 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1926612 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 704225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 21025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,167 +188,153 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 78613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 78193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 94725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 83224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 77979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 75147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 72304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 45205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 65288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 93465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 105702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 113971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 112162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 108444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 104050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 97727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 116214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 104741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 100206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 102548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 704 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1080190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 174.567156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.861850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.135229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 694007 64.25% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 206792 19.14% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51978 4.81% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24974 2.31% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18580 1.72% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11712 1.08% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8387 0.78% 94.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7821 0.72% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55939 5.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1080190 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 83578 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.770071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 136.461901 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 83575 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads -system.physmem.totQLat 24526926504 # Total ticks spent queuing -system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 83578 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 83578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.482244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.955849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.755182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 75860 90.77% 90.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 5202 6.22% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1276 1.53% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 755 0.90% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 241 0.29% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 100 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 48 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 8 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 17 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 25 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 83578 # Writes before turning the bus around for reads +system.physmem.totQLat 40962619238 # Total ticks spent queuing +system.physmem.totMemAccLat 60975037988 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5336645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38378.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 57128.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing -system.physmem.readRowHits 582169 # Number of row buffer hits during reads -system.physmem.writeRowHits 931750 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes -system.physmem.avgGap 19730499.53 # Average gap between requests -system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.643023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states +system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.74 # Average write queue length when enqueuing +system.physmem.readRowHits 799066 # Number of row buffer hits during reads +system.physmem.writeRowHits 1067089 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 56.79 # Row buffer hit rate for writes +system.physmem.avgGap 15842672.12 # Average gap between requests +system.physmem.pageHitRate 63.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4225820760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2305755375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4093954800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6217942320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1196990920755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27436312080750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31751124639720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.766110 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45642284556030 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585367160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states +system.physmem_0.memoryStateTime::ACT 249523460470 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.612186 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states +system.physmem_1.actEnergy 3940415640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2150028375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4231125600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5958113760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1192295919105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27440430503250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31749984270690 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.742090 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45649112064952 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585367160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242698243548 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -379,18 +365,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 133649210 # Number of BP lookups -system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 146228375 # Number of BP lookups +system.cpu0.branchPred.condPredicted 102974776 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6711039 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 109409110 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78811291 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.033573 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17518133 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1190785 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,67 +407,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 281840 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 302414 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 302414 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9161 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80364 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 302414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 302414 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 302414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 89525 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 88579 98.94% 98.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 783 0.87% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 49 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 89525 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 80364 89.77% 89.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9161 10.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 89525 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302414 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302414 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89525 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 391939 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86621651 # DTB read hits -system.cpu0.dtb.read_misses 235326 # DTB read misses -system.cpu0.dtb.write_hits 77269391 # DTB write hits -system.cpu0.dtb.write_misses 46514 # DTB write misses +system.cpu0.dtb.read_hits 94852147 # DTB read hits +system.cpu0.dtb.read_misses 252189 # DTB read misses +system.cpu0.dtb.write_hits 83443537 # DTB write hits +system.cpu0.dtb.write_misses 50225 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36113 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2068 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9574 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86856977 # DTB read accesses -system.cpu0.dtb.write_accesses 77315905 # DTB write accesses +system.cpu0.dtb.perms_faults 10663 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 95104336 # DTB read accesses +system.cpu0.dtb.write_accesses 83493762 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 163891042 # DTB hits -system.cpu0.dtb.misses 281840 # DTB misses -system.cpu0.dtb.accesses 164172882 # DTB accesses +system.cpu0.dtb.hits 178295684 # DTB hits +system.cpu0.dtb.misses 302414 # DTB misses +system.cpu0.dtb.accesses 178598098 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,191 +492,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66347 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66598 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66598 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 516 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54284 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66598 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66598 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66598 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 54800 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 53728 98.04% 98.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 946 1.73% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 48 0.09% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 54800 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54284 99.06% 99.06% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 516 0.94% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54800 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66598 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66598 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 239632917 # ITB inst hits -system.cpu0.itb.inst_misses 66347 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54800 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54800 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 261387859 # ITB inst hits +system.cpu0.itb.inst_misses 66598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25865 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 223375 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses -system.cpu0.itb.hits 239632917 # DTB hits -system.cpu0.itb.misses 66347 # DTB misses -system.cpu0.itb.accesses 239699264 # DTB accesses -system.cpu0.numCycles 955623985 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 261454457 # ITB inst accesses +system.cpu0.itb.hits 261387859 # DTB hits +system.cpu0.itb.misses 66598 # DTB misses +system.cpu0.itb.accesses 261454457 # DTB accesses +system.cpu0.numCycles 1029830596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 445844997 # Number of instructions committed -system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.143400 # CPI: cycles per instruction -system.cpu0.ipc 0.466549 # IPC: instructions per cycle +system.cpu0.committedInsts 487755400 # Number of instructions committed +system.cpu0.committedOps 573075495 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47715438 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4391 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93925247519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.111367 # CPI: cycles per instruction +system.cpu0.ipc 0.473627 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed -system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5506052 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13314 # number of quiesce instructions executed +system.cpu0.tickCycles 777849504 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 251981092 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5902107 # number of replacements +system.cpu0.dcache.tags.tagsinuse 475.000126 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169363182 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5902609 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.692936 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits -system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses -system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.000126 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.927735 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.927735 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 502 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.980469 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 359562725 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 359562725 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86974547 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86974547 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 77401946 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 77401946 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 298185 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 298185 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 275916 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 275916 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1961524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1961524 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1923644 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1923644 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164376493 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164376493 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164674678 # number of overall hits +system.cpu0.dcache.overall_hits::total 164674678 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3650210 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3650210 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2435892 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2435892 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670224 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 670224 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 817849 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 817849 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 165967 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 165967 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202383 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202383 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6086102 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6086102 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6756326 # number of overall misses +system.cpu0.dcache.overall_misses::total 6756326 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55969500387 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 55969500387 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47032436273 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 47032436273 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 33507618312 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 33507618312 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2441854002 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2441854002 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4283229947 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4283229947 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1855000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1855000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 103001936660 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 103001936660 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90624757 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90624757 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79837838 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79837838 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 968409 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 968409 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093765 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093765 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2127491 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2127491 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2126027 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2126027 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170462595 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 170462595 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171431004 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 171431004 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040278 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040278 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030510 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030510 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.692088 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.692088 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.747737 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.747737 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078011 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078011 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095193 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095193 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035703 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.035703 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039411 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039411 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -704,161 +681,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks -system.cpu0.dcache.writebacks::total 3760610 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1379824 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1379824 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2926726 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2926726 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1345143 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 614981 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 614981 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 822584 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 822584 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115009 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 183586 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 183586 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4271869 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4271869 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4886850 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4886850 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33259 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66422 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37662767131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37662767131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23537156289 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13208319439 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31592370271 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31592370271 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3966592 # number of writebacks +system.cpu0.dcache.writebacks::total 3966592 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 443574 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 443574 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1010368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1010368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 102 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 102 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 27 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 27 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1453942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1453942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1453942 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1453942 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3206636 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3206636 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1425524 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1425524 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664815 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 664815 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 817747 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 817747 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202356 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202356 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4632160 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4632160 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5296975 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5296975 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31604 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62581 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42580313466 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42580313466 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25667045166 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25667045166 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14837829930 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14837829930 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32271814438 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 32271814438 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1568491891 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1568491891 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3969414040 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3969414040 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1696000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1696000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68247358632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 68247358632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83085188562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 83085188562 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5612600750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5612600750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5285393252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5285393252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10897994002 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10897994002 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017855 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017855 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.686502 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.686502 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747644 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.747644 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095180 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095180 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027174 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027174 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030899 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030899 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9994306 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 10289736 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930282 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 250868144 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10290248 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.379213 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24018555250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930282 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits -system.cpu0.icache.overall_hits::total 229434949 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses -system.cpu0.icache.overall_misses::total 9994827 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 532607059 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 532607059 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 250868144 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 250868144 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 250868144 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 250868144 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 250868144 # number of overall hits +system.cpu0.icache.overall_hits::total 250868144 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10290257 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10290257 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10290257 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10290257 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10290257 # number of overall misses +system.cpu0.icache.overall_misses::total 10290257 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101454150461 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 101454150461 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 101454150461 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 101454150461 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 101454150461 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 261158401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 261158401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 261158401 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 261158401 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 261158401 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 261158401 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039402 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039402 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039402 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039402 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039402 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039402 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.243599 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.243599 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9859.243599 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9859.243599 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -867,467 +844,462 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10290257 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 91134485035 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 91134485035 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 91134485035 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 91134485035 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 91134485035 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 91134485035 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039402 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039402 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8856.385709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230073 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7233896 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 3309 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8031555 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8035489 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 3395 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 950560 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2661651 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16101.576152 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15630806 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2677359 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.838143 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5822133500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5793.980406 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 73.792044 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 73.619480 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5777.684117 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3504.905506 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 877.594600 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.353636 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004504 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004493 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.352642 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.213922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053564 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982762 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1351 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14265 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 263 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 705 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7781 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 446 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082458 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.870667 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 331999507 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 331999507 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494334 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160804 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9208783 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2710357 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12574278 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3760607 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3760607 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 232072 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 232072 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 101378 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 101378 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33994 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33994 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 863447 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 863447 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494334 # 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average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 17664917 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15307376 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3966591 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1103078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166462 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 816287 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 481802 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 516230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1338230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1206066 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20685127 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17177406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364539 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170846 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39397918 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 661924032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645723507 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1324200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4272848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1313244587 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4794163 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 26128529 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.203121 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.402322 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 20821287 79.69% 79.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5307242 20.31% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 26128529 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 15626998682 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 207003480 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15540735463 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8534595583 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 199309237 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 637104704 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123549187 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits +system.cpu1.branchPred.lookups 125576312 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90437850 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5588126 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 96414800 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 70448335 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.067968 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14240452 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 921306 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1357,65 +1329,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 259362 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 267188 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 267188 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10577 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85745 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 267188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 267188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 267188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 96322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 91721 95.22% 95.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3398 3.53% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 602 0.62% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 416 0.43% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 24 0.02% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 36 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 19 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 31 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 34 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 96322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1244507444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1244507444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1244507444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85745 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10577 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 96322 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 267188 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 267188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 96322 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 96322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 363510 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80542266 # DTB read hits -system.cpu1.dtb.read_misses 214982 # DTB read misses -system.cpu1.dtb.write_hits 69249357 # DTB write hits -system.cpu1.dtb.write_misses 44380 # DTB write misses +system.cpu1.dtb.read_hits 79480191 # DTB read hits +system.cpu1.dtb.read_misses 220503 # DTB read misses +system.cpu1.dtb.write_hits 69950509 # DTB write hits +system.cpu1.dtb.write_misses 46685 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40279 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1007 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7671 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80757248 # DTB read accesses -system.cpu1.dtb.write_accesses 69293737 # DTB write accesses +system.cpu1.dtb.perms_faults 12807 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79700694 # DTB read accesses +system.cpu1.dtb.write_accesses 69997194 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149791623 # DTB hits -system.cpu1.dtb.misses 259362 # DTB misses -system.cpu1.dtb.accesses 150050985 # DTB accesses +system.cpu1.dtb.hits 149430700 # DTB hits +system.cpu1.dtb.misses 267188 # DTB misses +system.cpu1.dtb.accesses 149697888 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1445,191 +1419,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60478 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated +system.cpu1.itb.walker.walks 64917 # Table walker walks requested +system.cpu1.itb.walker.walksLong 64917 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 645 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55496 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 64917 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 64917 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 64917 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 56141 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 54677 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1297 2.31% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 81 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 56141 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1243919944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1243919944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1243919944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55496 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 645 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56141 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64917 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64917 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 220701471 # ITB inst hits -system.cpu1.itb.inst_misses 60478 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56141 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56141 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 121058 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 225481249 # ITB inst hits +system.cpu1.itb.inst_misses 64917 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28543 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses -system.cpu1.itb.hits 220701471 # DTB hits -system.cpu1.itb.misses 60478 # DTB misses -system.cpu1.itb.accesses 220761949 # DTB accesses -system.cpu1.numCycles 819495419 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 225546166 # ITB inst accesses +system.cpu1.itb.hits 225481249 # DTB hits +system.cpu1.itb.misses 64917 # DTB misses +system.cpu1.itb.accesses 225546166 # DTB accesses +system.cpu1.numCycles 849119079 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 407174795 # Number of instructions committed -system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.012638 # CPI: cycles per instruction -system.cpu1.ipc 0.496860 # IPC: instructions per cycle +system.cpu1.committedInsts 406051299 # Number of instructions committed +system.cpu1.committedOps 478293699 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 46606937 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5644 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94106060514 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.091162 # CPI: cycles per instruction +system.cpu1.ipc 0.478203 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed -system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4776829 # number of replacements -system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5757 # number of quiesce instructions executed +system.cpu1.tickCycles 666946808 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 182172271 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5052284 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.990994 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 141727438 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5052796 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.049309 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380007678500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.990994 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894514 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.894514 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 302037341 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 302037341 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73896099 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73896099 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64629380 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64629380 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 204586 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 204586 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 67650 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 67650 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684264 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1684264 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1653940 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1653940 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138525479 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138525479 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138730065 # number of overall hits -system.cpu1.dcache.overall_hits::total 138730065 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3123049 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3123049 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2001792 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2001792 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 560125 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 560125 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 418714 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 418714 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158898 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 158898 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187849 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187849 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5124841 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5124841 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5684966 # number of overall misses -system.cpu1.dcache.overall_misses::total 5684966 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43997999443 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43997999443 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 34323796172 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 34323796172 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11321642584 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11321642584 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2327905715 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2327905715 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3931505754 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3931505754 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3098000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3098000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78321795615 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78321795615 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78321795615 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78321795615 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77019148 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77019148 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 66631172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 66631172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 764711 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 764711 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 486364 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 486364 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843162 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1843162 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1841789 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1841789 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 143650320 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 143650320 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 144415031 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 144415031 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040549 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040549 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030043 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030043 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732466 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732466 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.860907 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.860907 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086209 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086209 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101993 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101993 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035676 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035676 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039365 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039365 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14088.155339 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14088.155339 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17146.534791 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17146.534791 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27039.082964 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27039.082964 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14650.314762 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14650.314762 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20929.074704 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20929.074704 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 301466109 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 301466109 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72704936 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72704936 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65165576 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65165576 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 206723 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 206723 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 46881 # 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number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2249159 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 660232 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 660232 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 426407 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 426407 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160976 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 160976 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201965 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 201965 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5456345 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5456345 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6116577 # number of overall misses +system.cpu1.dcache.overall_misses::total 6116577 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 49733165026 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 49733165026 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39916128019 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 39916128019 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12105984043 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12105984043 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2535632453 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2535632453 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4276755567 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4276755567 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1256500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1256500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89649293045 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89649293045 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89649293045 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89649293045 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75912122 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75912122 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67414735 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67414735 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 866955 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 866955 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 473288 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 473288 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1747321 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1747321 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1746082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1746082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 143326857 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 143326857 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 144193812 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 144193812 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.042249 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.042249 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033363 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.033363 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.761553 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.761553 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.900946 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.900946 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092127 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092127 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.115668 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.115668 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038069 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038069 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042419 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.042419 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15282.775722 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15282.775722 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13777.003348 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1638,161 +1608,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks -system.cpu1.dcache.writebacks::total 3038485 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3294639 # number of writebacks +system.cpu1.dcache.writebacks::total 3294639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 376716 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 376716 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 934861 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 934861 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 50 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 50 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39920 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39920 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 26 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 26 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1311577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1311577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1311577 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1311577 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2830470 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2830470 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1314298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1314298 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659943 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 659943 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 426357 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 426357 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121056 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121056 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201939 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 201939 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4144768 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4144768 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4804711 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4804711 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7026 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38398702439 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38398702439 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21764603493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21764603493 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13372610673 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13372610673 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11459992206 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11459992206 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1620200910 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1620200910 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3963729421 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3963729421 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1148000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1148000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60163305932 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60163305932 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73535916605 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 73535916605 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 828088750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 828088750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 987688750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 987688750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1815777500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1815777500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037286 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037286 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019496 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019496 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761219 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.761219 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.900841 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.900841 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069281 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069281 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.115653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.115653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033321 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8549825 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8512500 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.044267 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216759728 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8513012 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.462166 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8369990866500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.044267 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990321 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990321 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 449535393 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 449535393 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 211942190 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 211942190 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 211942190 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 211942190 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 211942190 # number of overall hits -system.cpu1.icache.overall_hits::total 211942190 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8550338 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8550338 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8550338 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8550338 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8550338 # number of overall misses -system.cpu1.icache.overall_misses::total 8550338 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84064963562 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 84064963562 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 84064963562 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 84064963562 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 84064963562 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 84064963562 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 220492528 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 220492528 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 220492528 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 220492528 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 220492528 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 220492528 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038778 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038778 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038778 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038778 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038778 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038778 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9831.770810 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9831.770810 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9831.770810 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9831.770810 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 459058494 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 459058494 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 216759728 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 216759728 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 216759728 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 216759728 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 216759728 # number of overall hits +system.cpu1.icache.overall_hits::total 216759728 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8513013 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8513013 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8513013 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8513013 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8513013 # number of overall misses +system.cpu1.icache.overall_misses::total 8513013 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85304905568 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 85304905568 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 85304905568 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 85304905568 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 85304905568 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 85304905568 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 225272741 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 225272741 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 225272741 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 225272741 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 225272741 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 225272741 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037790 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037790 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037790 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10020.530401 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10020.530401 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1801,241 +1771,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8550338 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8550338 # 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number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 76768195856 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 76768195856 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 76768195856 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 76768195856 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 76768195856 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 76768195856 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8107000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8107000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8107000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8107000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037790 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037790 # 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average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7158191 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7159863 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1351 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3832.023077 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3147.321084 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 943.891423 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.332220 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005062 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005425 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233888 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192097 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057611 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.826304 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1444 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14725 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 436 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 846 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5482 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7066 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 978 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.088135 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898743 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 283341479 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 283341479 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 455761 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138301 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7823529 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17115860957 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34168842500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 51972895494 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 315988754 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17115860957 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34168842500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35590505004 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 87563400498 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7349000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 771832750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 779181750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 931317500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 931317500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7349000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1703150250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1710499250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.276281 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.138973 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.577695 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.577695 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.698971 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.698971 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.816038 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816038 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.592436 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.592436 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.657861 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.657861 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825006 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825006 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.230225 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.230225 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138649 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.214518 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.214518 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.145000 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183983 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22381.061927 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21997.300501 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32251.883341 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30868.772240 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30868.772240 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19324.564083 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19324.564083 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14558.396990 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14558.396990 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 714333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 714333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30079.764078 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30079.764078 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22970.037902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25257.109948 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93929.077317 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93801.179200 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107178.494397 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107178.494397 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 100556.391445 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 100433.772027 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.197716 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 937500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 937500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15573132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13012901 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3294638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1065592 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1119456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 424954 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 473527 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1269149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1115295 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17026205 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14595450 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 357835 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1096931 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33076421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544838528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 546511254 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1311792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4013488 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1096675062 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5302361 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 23181233 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.250406 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.433247 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 17376502 74.96% 74.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5804731 25.04% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 23181233 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12806281931 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 180531485 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12781520856 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7568960857 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 194234943 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 595690418 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40383 # Transaction distribution -system.iobus.trans_dist::ReadResp 40383 # Transaction distribution -system.iobus.trans_dist::WriteReq 136956 # Transaction distribution -system.iobus.trans_dist::WriteResp 29972 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40349 # Transaction distribution +system.iobus.trans_dist::ReadResp 40349 # Transaction distribution +system.iobus.trans_dist::WriteReq 136610 # Transaction distribution +system.iobus.trans_dist::WriteResp 29882 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47640 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2263,18 +2231,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122574 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2284,18 +2252,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155681 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496839 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36172000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2315,7 +2283,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2323,71 +2291,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607512131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92695000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148588668 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115850 # number of replacements -system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use +system.iocache.tags.replacements 115637 # number of replacements +system.iocache.tags.tagsinuse 11.310069 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115653 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129457632000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.399895 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.910174 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462493 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244386 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706879 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043187 # Number of tag accesses -system.iocache.tags.data_accesses 1043187 # Number of data accesses +system.iocache.tags.tag_accesses 1041045 # Number of tag accesses +system.iocache.tags.data_accesses 1041045 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106984 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106984 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8886 # number of demand (read+write) misses -system.iocache.demand_misses::total 8926 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses +system.iocache.demand_misses::total 8944 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8886 # number of overall misses -system.iocache.overall_misses::total 8926 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8904 # number of overall misses +system.iocache.overall_misses::total 8944 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1622865167 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1628060667 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19842621296 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19842621296 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1622865167 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1628429667 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1622865167 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1628429667 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106984 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106984 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8886 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8926 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8886 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8926 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2401,55 +2369,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182089.326362 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182069.506597 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182069.506597 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110288 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.796574 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1147719 # number of replacements -system.l2c.tags.tagsinuse 64326.028489 # Cycle average of tags in use -system.l2c.tags.total_refs 4694874 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1208975 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.883351 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8775850000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21201.345204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 99.174306 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 102.969089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6287.304380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9789.287555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7119.681672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 173.781032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 211.002205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4753.478760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6062.523137 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8525.481150 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.323507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.095937 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.149373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.108638 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.072532 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.092507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.130089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.981537 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9955 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 51081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 63 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 299 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 192 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1433 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 215 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11769 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 36932 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.151901 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.779434 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 59123537 # Number of tag accesses -system.l2c.tags.data_accesses 59123537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6743 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4986 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 715760 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 559628 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 328609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6048 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 682361 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 522413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 303271 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3133948 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2214381 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1425966751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13841121752 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.192710 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181320 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212132 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770238 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.472421 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.683033 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.635002 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.589189 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.612759 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601971 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596503 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618691 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.515549 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.571866 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.232022 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.232022 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33548.050591 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32025.022175 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33239.596409 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17799.416115 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.188394 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17801.177159 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17787.396188 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17809.571812 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17798.269170 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77295.267829 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72023.520979 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75137.639645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150061.012846 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 90265.980923 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94148.330129 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144601.849792 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105381.038057 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136944.559961 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147358.779038 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 98078.736571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 106867.220149 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 709274 # Transaction distribution -system.membus.trans_dist::ReadResp 709274 # Transaction distribution -system.membus.trans_dist::WriteReq 38250 # Transaction distribution -system.membus.trans_dist::WriteResp 38250 # Transaction distribution -system.membus.trans_dist::Writeback 981258 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution -system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution -system.membus.trans_dist::ReadExReq 127489 # Transaction distribution -system.membus.trans_dist::ReadExResp 110378 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 975380 # Transaction distribution +system.membus.trans_dist::ReadResp 975380 # Transaction distribution +system.membus.trans_dist::WriteReq 38492 # Transaction distribution +system.membus.trans_dist::WriteResp 38492 # Transaction distribution +system.membus.trans_dist::Writeback 1255244 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 671368 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 671368 # Transaction distribution +system.membus.trans_dist::UpgradeReq 435292 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 320448 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117663 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 151367 # Transaction distribution +system.membus.trans_dist::ReadExResp 133687 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5296349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5445421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5781341 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 640714 # Total snoops (count) -system.membus.snoop_fanout::samples 3227461 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177552960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177762857 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14095872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14095872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191858729 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 658635 # Total snoops (count) +system.membus.snoop_fanout::samples 3847839 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3847839 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3227461 # Request fanout histogram -system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3847839 # Request fanout histogram +system.membus.reqLayer0.occupancy 109654500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21898998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11397821385 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6506682845 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152058832 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3143,45 +3106,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1657293 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5105910 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5098639 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38492 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2490573 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 937823 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 830969 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 486096 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 332772 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 818868 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302211 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302211 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8322623 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6766752 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15089375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 277489443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218349254 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 495838697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1695482 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9694113 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.011945 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108639 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9578315 98.81% 98.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115798 1.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9694113 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8435746901 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2506500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4797228870 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4287100444 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 828dae038..505d3c407 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.609999 # Number of seconds simulated -sim_ticks 51609998980000 # Number of ticks simulated -final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.610037 # Number of seconds simulated +sim_ticks 51610036853000 # Number of ticks simulated +final_tick 51610036853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182485 # Simulator instruction rate (inst/s) -host_op_rate 214421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9938249935 # Simulator tick rate (ticks/s) -host_mem_usage 720032 # Number of bytes of host memory used -host_seconds 5193.07 # Real time elapsed on the host -sim_insts 947659008 # Number of instructions simulated -sim_ops 1113505098 # Number of ops (including micro ops) simulated +host_inst_rate 188716 # Simulator instruction rate (inst/s) +host_op_rate 221745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10246213919 # Simulator tick rate (ticks/s) +host_mem_usage 724572 # Number of bytes of host memory used +host_seconds 5036.99 # Real time elapsed on the host +sim_insts 950561948 # Number of instructions simulated +sim_ops 1116924449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory -system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 410048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 340288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10352448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67122824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 411200 # Number of bytes read from this memory +system.physmem.bytes_read::total 78636808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10352448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10352448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 95202624 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 95223204 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 161757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1048807 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6425 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1228713 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1487541 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1490114 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1300577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1523673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1844653 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1202070 # Number of read requests accepted -system.physmem.writeReqs 2120779 # Number of write requests accepted -system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue -system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72977 # Per bank write bursts -system.physmem.perBankRdBursts::1 77412 # Per bank write bursts -system.physmem.perBankRdBursts::2 73227 # Per bank write bursts -system.physmem.perBankRdBursts::3 70716 # Per bank write bursts -system.physmem.perBankRdBursts::4 69716 # Per bank write bursts -system.physmem.perBankRdBursts::5 78531 # Per bank write bursts -system.physmem.perBankRdBursts::6 70002 # Per bank write bursts -system.physmem.perBankRdBursts::7 72888 # Per bank write bursts -system.physmem.perBankRdBursts::8 66687 # Per bank write bursts -system.physmem.perBankRdBursts::9 126636 # Per bank write bursts -system.physmem.perBankRdBursts::10 72169 # Per bank write bursts -system.physmem.perBankRdBursts::11 76842 # Per bank write bursts -system.physmem.perBankRdBursts::12 69750 # Per bank write bursts -system.physmem.perBankRdBursts::13 69617 # Per bank write bursts -system.physmem.perBankRdBursts::14 66498 # Per bank write bursts -system.physmem.perBankRdBursts::15 67847 # Per bank write bursts -system.physmem.perBankWrBursts::0 128572 # Per bank write bursts -system.physmem.perBankWrBursts::1 129591 # Per bank write bursts -system.physmem.perBankWrBursts::2 133621 # Per bank write bursts -system.physmem.perBankWrBursts::3 133794 # Per bank write bursts -system.physmem.perBankWrBursts::4 127990 # Per bank write bursts -system.physmem.perBankWrBursts::5 135547 # Per bank write bursts -system.physmem.perBankWrBursts::6 129190 # Per bank write bursts -system.physmem.perBankWrBursts::7 132517 # Per bank write bursts -system.physmem.perBankWrBursts::8 125103 # Per bank write bursts -system.physmem.perBankWrBursts::9 133352 # Per bank write bursts -system.physmem.perBankWrBursts::10 128272 # Per bank write bursts -system.physmem.perBankWrBursts::11 129497 # Per bank write bursts -system.physmem.perBankWrBursts::12 125797 # Per bank write bursts -system.physmem.perBankWrBursts::13 127747 # Per bank write bursts -system.physmem.perBankWrBursts::14 124476 # Per bank write bursts -system.physmem.perBankWrBursts::15 125194 # Per bank write bursts +system.physmem.bw_write::total 1845052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1844653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 200590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1300976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3368725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1228713 # Number of read requests accepted +system.physmem.writeReqs 2143008 # Number of write requests accepted +system.physmem.readBursts 1228713 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2143008 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78600192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37440 # Total number of bytes read from write queue +system.physmem.bytesWritten 133928256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78636808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 137008420 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 585 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50360 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39728 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 75722 # Per bank write bursts +system.physmem.perBankRdBursts::1 79954 # Per bank write bursts +system.physmem.perBankRdBursts::2 72878 # Per bank write bursts +system.physmem.perBankRdBursts::3 71278 # Per bank write bursts +system.physmem.perBankRdBursts::4 72651 # Per bank write bursts +system.physmem.perBankRdBursts::5 79829 # Per bank write bursts +system.physmem.perBankRdBursts::6 73600 # Per bank write bursts +system.physmem.perBankRdBursts::7 73320 # Per bank write bursts +system.physmem.perBankRdBursts::8 65239 # Per bank write bursts +system.physmem.perBankRdBursts::9 127420 # Per bank write bursts +system.physmem.perBankRdBursts::10 73665 # Per bank write bursts +system.physmem.perBankRdBursts::11 77478 # Per bank write bursts +system.physmem.perBankRdBursts::12 72459 # Per bank write bursts +system.physmem.perBankRdBursts::13 72712 # Per bank write bursts +system.physmem.perBankRdBursts::14 69098 # Per bank write bursts +system.physmem.perBankRdBursts::15 70825 # Per bank write bursts +system.physmem.perBankWrBursts::0 130775 # Per bank write bursts +system.physmem.perBankWrBursts::1 132563 # Per bank write bursts +system.physmem.perBankWrBursts::2 131683 # Per bank write bursts +system.physmem.perBankWrBursts::3 133448 # Per bank write bursts +system.physmem.perBankWrBursts::4 132375 # Per bank write bursts +system.physmem.perBankWrBursts::5 136941 # Per bank write bursts +system.physmem.perBankWrBursts::6 129100 # Per bank write bursts +system.physmem.perBankWrBursts::7 132855 # Per bank write bursts +system.physmem.perBankWrBursts::8 124239 # Per bank write bursts +system.physmem.perBankWrBursts::9 131924 # Per bank write bursts +system.physmem.perBankWrBursts::10 130753 # Per bank write bursts +system.physmem.perBankWrBursts::11 132768 # Per bank write bursts +system.physmem.perBankWrBursts::12 128150 # Per bank write bursts +system.physmem.perBankWrBursts::13 130180 # Per bank write bursts +system.physmem.perBankWrBursts::14 126529 # Per bank write bursts +system.physmem.perBankWrBursts::15 128346 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 166 # Number of times write queue was full causing retry -system.physmem.totGap 51609997338500 # Total gap between requests +system.physmem.numWrRetry 140 # Number of times write queue was full causing retry +system.physmem.totGap 51610035211500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1202055 # Read request sizes (log2) +system.physmem.readPktSize::6 1228698 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2118206 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2140435 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1157126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 175 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,169 +159,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 51481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 101890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 106045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 113976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 152332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 126167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 115190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 114656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 140408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 121792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 105744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 103641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 344 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 720627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.570872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.798815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.942314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 295355 40.99% 40.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175877 24.41% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63976 8.88% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35683 4.95% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24604 3.41% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16955 2.35% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13020 1.81% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11401 1.58% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 83756 11.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 720627 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.077512 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 124.901364 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 99480 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 52200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 103140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 107216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 115340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 154284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 127380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 115742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 109222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 142144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 115995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 122630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 110947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 107019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 104847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 312 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 733749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.646732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.469062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.982397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301017 41.02% 41.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179214 24.42% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 65174 8.88% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36623 4.99% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25257 3.44% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17346 2.36% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13099 1.79% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11628 1.58% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 84391 11.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 733749 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 100720 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.193388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 124.138953 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 100718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99482 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99482 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.810398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.292150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.172998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 95801 96.30% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1933 1.94% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 403 0.41% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 315 0.32% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 148 0.15% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 160 0.16% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 333 0.33% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 129 0.13% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 31 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 15 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 63 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 32 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 100720 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 100720 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.776698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.274786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.101890 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 96977 96.28% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 2012 2.00% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 404 0.40% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 303 0.30% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 157 0.16% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 153 0.15% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 320 0.32% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 134 0.13% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 20 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 11 0.01% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 66 0.07% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 35 0.03% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 7 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 9 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 20 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 8 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 12 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 21 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 5 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 5 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads -system.physmem.totQLat 16741886044 # Total ticks spent queuing -system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 100720 # Writes before turning the bus around for reads +system.physmem.totQLat 16983547454 # Total ticks spent queuing +system.physmem.totMemAccLat 40010947454 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6140640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13828.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32578.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing -system.physmem.readRowHits 927538 # Number of row buffer hits during reads -system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes -system.physmem.avgGap 15531851.53 # Average gap between requests -system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.733317 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states -system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 948457 # Number of row buffer hits during reads +system.physmem.writeRowHits 1638549 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.30 # Row buffer hit rate for writes +system.physmem.avgGap 15306733.63 # Average gap between requests +system.physmem.pageHitRate 77.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2845387440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1552542750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4674001800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6867115200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1311782988195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29815330787250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34513969041435 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.745387 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49599639397461 # Time in different power states +system.physmem_0.memoryStateTime::REF 1723372300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states +system.physmem_0.memoryStateTime::ACT 287019858539 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.710038 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states -system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states +system.physmem_1.actEnergy 2701755000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1474171875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4905342000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6693120720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1303897064130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29822248264500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34512835937025 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723432 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49611170347429 # Time in different power states +system.physmem_1.memoryStateTime::REF 1723372300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states +system.physmem_1.memoryStateTime::ACT 275493728071 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -345,15 +344,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 260066829 # Number of BP lookups -system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits +system.cpu.branchPred.lookups 260902420 # Number of BP lookups +system.cpu.branchPred.condPredicted 182959992 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12222887 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 194114900 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136429435 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.282825 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31730781 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2172348 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -384,61 +383,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 583127 # Table walker walks requested -system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 588227 # Table walker walks requested +system.cpu.dtb.walker.walksLong 588227 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22315 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191623 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 588227 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 588227 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 588227 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213938 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 211313 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2233 1.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 146 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213938 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 191624 89.57% 89.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22315 10.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213939 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 588227 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 588227 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213939 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213939 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 802166 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 182952995 # DTB read hits -system.cpu.dtb.read_misses 481784 # DTB read misses -system.cpu.dtb.write_hits 162354187 # DTB write hits -system.cpu.dtb.write_misses 101343 # DTB write misses +system.cpu.dtb.read_hits 183548892 # DTB read hits +system.cpu.dtb.read_misses 485969 # DTB read misses +system.cpu.dtb.write_hits 162881584 # DTB write hits +system.cpu.dtb.write_misses 102258 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 79791 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15585 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183434779 # DTB read accesses -system.cpu.dtb.write_accesses 162455530 # DTB write accesses +system.cpu.dtb.perms_faults 23526 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184034861 # DTB read accesses +system.cpu.dtb.write_accesses 162983842 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 345307182 # DTB hits -system.cpu.dtb.misses 583127 # DTB misses -system.cpu.dtb.accesses 345890309 # DTB accesses +system.cpu.dtb.hits 346430476 # DTB hits +system.cpu.dtb.misses 588227 # DTB misses +system.cpu.dtb.accesses 347018703 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,340 +467,341 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136411 # Table walker walks requested -system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136538 # Table walker walks requested +system.cpu.itb.walker.walksLong 136538 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1085 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118818 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136538 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136538 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136538 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119903 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27208.529278 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116996 97.58% 97.58% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2625 2.19% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 168 0.14% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 53 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 37 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119903 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118818 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1085 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119903 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136538 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136538 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 452746266 # ITB inst hits -system.cpu.itb.inst_misses 136411 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119903 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119903 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256441 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 454119408 # ITB inst hits +system.cpu.itb.inst_misses 136538 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57592 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57195 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 369764 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369083 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 452882677 # ITB inst accesses -system.cpu.itb.hits 452746266 # DTB hits -system.cpu.itb.misses 136411 # DTB misses -system.cpu.itb.accesses 452882677 # DTB accesses -system.cpu.numCycles 2486475408 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 454255946 # ITB inst accesses +system.cpu.itb.hits 454119408 # DTB hits +system.cpu.itb.misses 136538 # DTB misses +system.cpu.itb.accesses 454255946 # DTB accesses +system.cpu.numCycles 2495798541 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 947659008 # Number of instructions committed -system.cpu.committedOps 1113505098 # Number of ops (including micro ops) committed -system.cpu.discardedOps 96546934 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7735 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100734690731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.623808 # CPI: cycles per instruction -system.cpu.ipc 0.381125 # IPC: instructions per cycle +system.cpu.committedInsts 950561948 # Number of instructions committed +system.cpu.committedOps 1116924449 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97483728 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7747 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100725440428 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.625603 # CPI: cycles per instruction +system.cpu.ipc 0.380865 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16595 # number of quiesce instructions executed -system.cpu.tickCycles 1791502894 # Number of cycles that the object actually ticked -system.cpu.idleCycles 694972514 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11092406 # number of replacements +system.cpu.kern.inst.quiesce 16607 # number of quiesce instructions executed +system.cpu.tickCycles 1794634441 # Number of cycles that the object actually ticked +system.cpu.idleCycles 701164100 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11128908 # number of replacements system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 328965151 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11092918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.655421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 330012577 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11129420 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.652271 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1382417296 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1382417296 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 168207875 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168207875 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151549113 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151549113 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 490930 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 490930 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335942 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 335942 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4008865 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4008865 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4323127 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4323127 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 319756988 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 319756988 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320247918 # number of overall hits -system.cpu.dcache.overall_hits::total 320247918 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6578537 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6578537 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4302299 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4302299 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1473808 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1473808 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244599 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1244599 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 315993 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 315993 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1386837426 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1386837426 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 168701491 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168701491 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152033429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152033429 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 523995 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 523995 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4025252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4025252 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4342024 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4342024 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 320734920 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320734920 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321258915 # number of overall hits +system.cpu.dcache.overall_hits::total 321258915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6599201 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6599201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4320372 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4320372 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1481368 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1481368 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244671 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1244671 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 318506 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 318506 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10880836 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10880836 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12354644 # number of overall misses -system.cpu.dcache.overall_misses::total 12354644 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 106697920457 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 153242376598 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35461255171 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35461255171 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4805977234 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4805977234 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 10919573 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10919573 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12400941 # number of overall misses +system.cpu.dcache.overall_misses::total 12400941 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107641538217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 155110738831 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35571203201 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35571203201 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4850646421 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4850646421 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 259940297055 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 259940297055 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 259940297055 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 259940297055 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 174786412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 174786412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 155851412 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 155851412 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1964738 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1964738 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1580541 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1580541 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4324858 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4324858 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4323128 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4323128 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 330637824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 330637824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 332602562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 332602562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037638 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037638 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027605 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027605 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750130 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.750130 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787451 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787451 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073064 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073064 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 262752277048 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 262752277048 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 262752277048 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 262752277048 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 175300692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 175300692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156353801 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156353801 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005363 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2005363 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581358 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581358 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4343758 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4343758 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4342025 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4342025 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 331654493 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 331654493 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 333659856 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333659856 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037645 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037645 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027632 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027632 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738703 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.738703 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787090 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787090 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073325 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032909 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032909 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037145 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037145 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032925 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032925 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037166 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037166 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23889.735775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21039.885654 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24062.504738 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21188.091859 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8509656 # number of writebacks -system.cpu.dcache.writebacks::total 8509656 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799615 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 799615 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1895946 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1895946 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 144 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 144 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69791 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69791 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2695561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2695561 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2695561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2695561 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5778922 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5778922 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2406353 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2406353 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466300 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1466300 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244455 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244455 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8539693 # number of writebacks +system.cpu.dcache.writebacks::total 8539693 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803144 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 803144 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904565 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1904565 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 147 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 147 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69655 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69655 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2707709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2707709 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2707709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2707709 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5796057 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5796057 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2415807 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2415807 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473891 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1473891 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244524 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244524 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248851 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 248851 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8211864 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8211864 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9685755 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9685755 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85294782786 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 85294782786 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79878018296 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79878018296 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23078167080 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23078167080 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33700697799 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33700697799 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3279664007 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3279664007 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165172801082 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 188250968162 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5750649000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5750649000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5615353750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5615353750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11366002750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11366002750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734975 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734975 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786997 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786997 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057289 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057289 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024760 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024760 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029029 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029029 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24538707 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24596775 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926998 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 429140951 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24597287 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.446678 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 22329177250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926998 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 476903830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 476903830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 427825373 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 427825373 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 427825373 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 427825373 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 427825373 # number of overall hits -system.cpu.icache.overall_hits::total 427825373 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24539229 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24539229 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24539229 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24539229 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24539229 # number of overall misses -system.cpu.icache.overall_misses::total 24539229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 326974610838 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 326974610838 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 326974610838 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 326974610838 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 326974610838 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 326974610838 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 452364602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 452364602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 452364602 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 452364602 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 452364602 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 452364602 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403 # 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average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 33924038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33915953 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8539693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49695 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 565529 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 49696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2366369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2366369 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49299178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31033537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 698041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2292039 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83322795 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577573568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1259064522 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2320736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7893144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2846851970 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 553019 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46264787 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.039533 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.194859 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44435816 96.05% 96.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1828971 3.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 46264787 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32875768488 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1167000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37011580552 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15738706286 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408640707 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1306185489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40311 # Transaction distribution -system.iobus.trans_dist::ReadResp 40311 # Transaction distribution +system.iobus.trans_dist::ReadReq 40309 # Transaction distribution +system.iobus.trans_dist::ReadResp 40309 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1219,11 +1219,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1240,11 +1240,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1273,71 +1273,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606954435 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148397760 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115472 # number of replacements -system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use +system.iocache.tags.replacements 115470 # number of replacements +system.iocache.tags.tagsinuse 10.439534 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13142420796000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.524742 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.914791 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039767 # Number of tag accesses -system.iocache.tags.data_accesses 1039767 # Number of data accesses +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses -system.iocache.demand_misses::total 8866 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8824 # number of demand (read+write) misses +system.iocache.demand_misses::total 8864 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8826 # number of overall misses -system.iocache.overall_misses::total 8866 # number of overall misses +system.iocache.overall_misses::realview.ide 8824 # number of overall misses +system.iocache.overall_misses::total 8864 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1602204582 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1607276582 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19806517093 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19806517093 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1602204582 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1607629082 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1602204582 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1607629082 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8824 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8864 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8824 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8864 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1352,54 +1352,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181387.719445 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181366.096796 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181366.096796 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109809 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.797635 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8824 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8864 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8824 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8864 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1142260060 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1145402060 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14259947135 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14259947135 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1142260060 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1145595560 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1142260060 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1145595560 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1414,70 +1414,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 537267 # Transaction distribution -system.membus.trans_dist::ReadResp 537267 # Transaction distribution +system.membus.trans_dist::ReadReq 551255 # Transaction distribution +system.membus.trans_dist::ReadResp 551255 # Transaction distribution system.membus.trans_dist::WriteReq 33705 # Transaction distribution system.membus.trans_dist::WriteResp 33705 # Transaction distribution -system.membus.trans_dist::Writeback 1468636 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution +system.membus.trans_dist::Writeback 1487541 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 652894 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 652894 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39734 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution -system.membus.trans_dist::ReadExReq 701468 # Transaction distribution -system.membus.trans_dist::ReadExResp 701468 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39735 # Transaction distribution +system.membus.trans_dist::ReadExReq 714242 # Transaction distribution +system.membus.trans_dist::ReadExResp 714242 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5003208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5132856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5468104 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2980 # Total snoops (count) -system.membus.snoop_fanout::samples 3430156 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201583148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201753546 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14062080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14062080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 215815626 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3099 # Total snoops (count) +system.membus.snoop_fanout::samples 3479513 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3479513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3430156 # Request fanout histogram -system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3479513 # Request fanout histogram +system.membus.reqLayer0.occupancy 102597500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5574500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12409067173 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7071367467 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7217145927 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151550030 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151545740 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted |