diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-04 19:00:48 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-04 19:00:48 -0600 |
| commit | 5ebe3210d80d7f0226c33877d7200be8cb38d423 (patch) | |
| tree | 27a31051c662fdc72623351a6806ba695eab28e0 /tests/long/fs/10.linux-boot | |
| parent | e17c375ddd32fbbef55a96c446a4b98b20df2ad5 (diff) | |
| download | gem5-5ebe3210d80d7f0226c33877d7200be8cb38d423.tar.xz | |
regressions: stats update due to decoder changes
Diffstat (limited to 'tests/long/fs/10.linux-boot')
7 files changed, 193 insertions, 206 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 219ef17ea..e4ef93067 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index a24f5a985..1c087a72b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.523500 # Nu sim_ticks 2523500318000 # Number of ticks simulated final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54734 # Simulator instruction rate (inst/s) -host_op_rate 70403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2279341302 # Simulator tick rate (ticks/s) -host_mem_usage 401036 # Number of bytes of host memory used -host_seconds 1107.12 # Real time elapsed on the host +host_inst_rate 64209 # Simulator instruction rate (inst/s) +host_op_rate 82591 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2673913922 # Simulator tick rate (ticks/s) +host_mem_usage 441476 # Number of bytes of host memory used +host_seconds 943.75 # Real time elapsed on the host sim_insts 60596849 # Number of instructions simulated sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory @@ -584,7 +584,7 @@ system.cpu.int_regfile_reads 549353820 # nu system.cpu.int_regfile_writes 87979072 # number of integer regfile writes system.cpu.fp_regfile_reads 8318 # number of floating regfile reads system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads system.cpu.misc_regfile_writes 912865 # number of misc regfile writes system.cpu.icache.replacements 980837 # number of replacements system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index e8e271d58..523f8a126 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 2681ab283..3f5cdc3ab 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.593146 # Nu sim_ticks 2593146078000 # Number of ticks simulated final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66425 # Simulator instruction rate (inst/s) -host_op_rate 85503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2731005239 # Simulator tick rate (ticks/s) -host_mem_usage 409388 # Number of bytes of host memory used -host_seconds 949.52 # Real time elapsed on the host +host_inst_rate 77303 # Simulator instruction rate (inst/s) +host_op_rate 99505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3178225665 # Simulator tick rate (ticks/s) +host_mem_usage 449664 # Number of bytes of host memory used +host_seconds 815.91 # Real time elapsed on the host sim_insts 63072130 # Number of instructions simulated sim_ops 81187111 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory @@ -1007,7 +1007,7 @@ system.cpu0.int_regfile_reads 175323075 # nu system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads system.cpu0.fp_regfile_writes 906 # number of floating regfile writes -system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads +system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes system.cpu0.icache.replacements 399233 # number of replacements system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use @@ -1577,7 +1577,7 @@ system.cpu1.int_regfile_reads 391481129 # nu system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads +system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes system.cpu1.icache.replacements 614989 # number of replacements system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index fbd26bc50..842d69c20 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,11 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem +midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -64,12 +65,12 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,7 +118,6 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts -isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -497,23 +497,6 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts -[system.cpu.isa] -type=ArmISA -fpsid=1090793632 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=3 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=4027589137 -id_pfr0=49 -id_pfr1=1 -midr=890224640 - [system.cpu.itb] type=ArmTLB children=walker diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 3ee89fc27..affb69ad6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,6 +11,8 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6a79df0e0..0468c1634 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.523500 # Nu sim_ticks 2523500318000 # Number of ticks simulated final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66325 # Simulator instruction rate (inst/s) -host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2762063576 # Simulator tick rate (ticks/s) -host_mem_usage 400896 # Number of bytes of host memory used -host_seconds 913.63 # Real time elapsed on the host +host_inst_rate 76318 # Simulator instruction rate (inst/s) +host_op_rate 98167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3178196363 # Simulator tick rate (ticks/s) +host_mem_usage 441472 # Number of bytes of host memory used +host_seconds 794.00 # Real time elapsed on the host sim_insts 60596849 # Number of instructions simulated sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory @@ -539,7 +539,7 @@ system.cpu.int_regfile_reads 549353817 # nu system.cpu.int_regfile_writes 87979071 # number of integer regfile writes system.cpu.fp_regfile_reads 8318 # number of floating regfile reads system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads system.cpu.misc_regfile_writes 912865 # number of misc regfile writes system.cpu.icache.replacements 980837 # number of replacements system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use @@ -633,6 +633,168 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 64388 # number of replacements system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. @@ -896,168 +1058,6 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643459 # number of replacements -system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use -system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits -system.cpu.dcache.overall_hits::total 21094791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses -system.cpu.dcache.overall_misses::total 3692032 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks -system.cpu.dcache.writebacks::total 607749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. |