diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
| commit | 470051345af2a78425730bd790000530b1b8a1f5 (patch) | |
| tree | d2bdfb09a2cfc4c96a5fcd9c4399610fbf4206a3 /tests/long/fs/10.linux-boot | |
| parent | 9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (diff) | |
| download | gem5-470051345af2a78425730bd790000530b1b8a1f5.tar.xz | |
ARM: Update stats for CBNZ fix.
Diffstat (limited to 'tests/long/fs/10.linux-boot')
8 files changed, 2657 insertions, 2663 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index b50c47979..51386a35a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:34:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:47:04 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503289265500 because m5_exit instruction encountered +Exiting @ tick 2503099557500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3749ebea8..d91423395 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503289 # Number of seconds simulated -sim_ticks 2503289265500 # Number of ticks simulated -final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503100 # Number of seconds simulated +sim_ticks 2503099557500 # Number of ticks simulated +final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55466 # Simulator instruction rate (inst/s) -host_op_rate 71644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335415954 # Simulator tick rate (ticks/s) -host_mem_usage 389340 # Number of bytes of host memory used -host_seconds 1071.88 # Real time elapsed on the host -sim_insts 59452703 # Number of instructions simulated -sim_ops 76793713 # Number of ops (including micro ops) simulated +host_inst_rate 68083 # Simulator instruction rate (inst/s) +host_op_rate 87941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2866621111 # Simulator tick rate (ticks/s) +host_mem_usage 384248 # Number of bytes of host memory used +host_seconds 873.19 # Real time elapsed on the host +sim_insts 59449445 # Number of instructions simulated +sim_ops 76789092 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130753040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9587720 # Number of bytes written to this memory -system.physmem.num_reads 15117482 # Number of read requests responded to by this memory -system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.bytes_read 130740776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9586312 # Number of bytes written to this memory +system.physmem.num_reads 15115704 # Number of read requests responded to by this memory +system.physmem.num_writes 856678 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119784 # number of replacements -system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use -system.l2c.total_refs 1841990 # Total number of references to valid blocks. -system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119794 # number of replacements +system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use +system.l2c.total_refs 1840774 # Total number of references to valid blocks. +system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.483052 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218343 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084068 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397859 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017089 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048289 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985507 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569735 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001039 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,9 +278,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15017434 # DTB read hits -system.cpu.checker.dtb.read_misses 7313 # DTB read misses -system.cpu.checker.dtb.write_hits 11274974 # DTB write hits +system.cpu.checker.dtb.read_hits 15016256 # DTB read hits +system.cpu.checker.dtb.read_misses 7312 # DTB read misses +system.cpu.checker.dtb.write_hits 11274185 # DTB write hits system.cpu.checker.dtb.write_misses 2190 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -291,13 +291,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15024747 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11277164 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15023568 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11276375 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26292408 # DTB hits -system.cpu.checker.dtb.misses 9503 # DTB misses -system.cpu.checker.dtb.accesses 26301911 # DTB accesses -system.cpu.checker.itb.inst_hits 60619265 # ITB inst hits +system.cpu.checker.dtb.hits 26290441 # DTB hits +system.cpu.checker.dtb.misses 9502 # DTB misses +system.cpu.checker.dtb.accesses 26299943 # DTB accesses +system.cpu.checker.itb.inst_hits 60615999 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -314,36 +314,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60623736 # ITB inst accesses -system.cpu.checker.itb.hits 60619265 # DTB hits +system.cpu.checker.itb.inst_accesses 60620470 # ITB inst accesses +system.cpu.checker.itb.hits 60615999 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60623736 # DTB accesses -system.cpu.checker.numCycles 77072082 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60620470 # DTB accesses +system.cpu.checker.numCycles 77067453 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51991464 # DTB read hits -system.cpu.dtb.read_misses 102104 # DTB read misses -system.cpu.dtb.write_hits 11910179 # DTB write hits -system.cpu.dtb.write_misses 24558 # DTB write misses +system.cpu.dtb.read_hits 51948606 # DTB read hits +system.cpu.dtb.read_misses 101816 # DTB read misses +system.cpu.dtb.write_hits 11910706 # DTB write hits +system.cpu.dtb.write_misses 24423 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8002 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7999 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52093568 # DTB read accesses -system.cpu.dtb.write_accesses 11934737 # DTB write accesses +system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52050422 # DTB read accesses +system.cpu.dtb.write_accesses 11935129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63901643 # DTB hits -system.cpu.dtb.misses 126662 # DTB misses -system.cpu.dtb.accesses 64028305 # DTB accesses -system.cpu.itb.inst_hits 13706914 # ITB inst hits -system.cpu.itb.inst_misses 11634 # ITB inst misses +system.cpu.dtb.hits 63859312 # DTB hits +system.cpu.dtb.misses 126239 # DTB misses +system.cpu.dtb.accesses 63985551 # DTB accesses +system.cpu.itb.inst_hits 13611127 # ITB inst hits +system.cpu.itb.inst_misses 11794 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -352,504 +352,504 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5188 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5224 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13718548 # ITB inst accesses -system.cpu.itb.hits 13706914 # DTB hits -system.cpu.itb.misses 11634 # DTB misses -system.cpu.itb.accesses 13718548 # DTB accesses -system.cpu.numCycles 414369636 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13622921 # ITB inst accesses +system.cpu.itb.hits 13611127 # DTB hits +system.cpu.itb.misses 11794 # DTB misses +system.cpu.itb.accesses 13622921 # DTB accesses +system.cpu.numCycles 414035717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits +system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued -system.cpu.iq.rate 0.304001 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued +system.cpu.iq.rate 0.303772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 597024 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 929867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216034 # number of nop insts executed -system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed -system.cpu.iew.exec_branches 11571925 # Number of branches executed -system.cpu.iew.exec_stores 12419635 # Number of stores executed -system.cpu.iew.exec_rate 0.296062 # Inst execution rate -system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46911516 # num instructions producing a value -system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value +system.cpu.iew.exec_nop 216875 # number of nop insts executed +system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed +system.cpu.iew.exec_branches 11533456 # Number of branches executed +system.cpu.iew.exec_stores 12420416 # Number of stores executed +system.cpu.iew.exec_rate 0.295954 # Inst execution rate +system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46901063 # num instructions producing a value +system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59603084 # Number of instructions committed -system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59599826 # Number of instructions committed +system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27461448 # Number of memory references committed -system.cpu.commit.loads 15681836 # Number of loads committed -system.cpu.commit.membars 413071 # Number of memory barriers committed -system.cpu.commit.branches 9891470 # Number of branches committed +system.cpu.commit.refs 27459254 # Number of memory references committed +system.cpu.commit.loads 15680449 # Number of loads committed +system.cpu.commit.membars 413031 # Number of memory barriers committed +system.cpu.commit.branches 9890920 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. -system.cpu.commit.function_calls 995631 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. +system.cpu.commit.function_calls 995546 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 248361579 # The number of ROB reads -system.cpu.rob.rob_writes 211126300 # The number of ROB writes -system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59452703 # Number of Instructions Simulated -system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated -system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556236615 # number of integer regfile reads -system.cpu.int_regfile_writes 88987616 # number of integer regfile writes -system.cpu.fp_regfile_reads 8813 # number of floating regfile reads -system.cpu.fp_regfile_writes 2942 # number of floating regfile writes -system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads -system.cpu.misc_regfile_writes 912350 # number of misc regfile writes -system.cpu.icache.replacements 1015901 # number of replacements -system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use -system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 247831805 # The number of ROB reads +system.cpu.rob.rob_writes 210661614 # The number of ROB writes +system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59449445 # Number of Instructions Simulated +system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated +system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555570057 # number of integer regfile reads +system.cpu.int_regfile_writes 88783659 # number of integer regfile writes +system.cpu.fp_regfile_reads 8868 # number of floating regfile reads +system.cpu.fp_regfile_writes 2963 # number of floating regfile writes +system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads +system.cpu.misc_regfile_writes 912266 # number of misc regfile writes +system.cpu.icache.replacements 1016880 # number of replacements +system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use +system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits -system.cpu.icache.overall_hits::total 12592690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses -system.cpu.icache.overall_misses::total 1106667 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits +system.cpu.icache.overall_hits::total 12495254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses +system.cpu.icache.overall_misses::total 1108036 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 58562 # number of writebacks -system.cpu.icache.writebacks::total 58562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 58719 # number of writebacks +system.cpu.icache.writebacks::total 58719 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645034 # number of replacements -system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use -system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644925 # number of replacements +system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use +system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # 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mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -868,14 +868,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index fcc2fd3aa..231285393 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:35:13 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:49:08 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2572328372500 because m5_exit instruction encountered +Exiting @ tick 2572151538500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index da2515fe9..3baa592c1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.572328 # Number of seconds simulated -sim_ticks 2572328372500 # Number of ticks simulated -final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.572152 # Number of seconds simulated +sim_ticks 2572151538500 # Number of ticks simulated +final_tick 2572151538500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66069 # Simulator instruction rate (inst/s) -host_op_rate 85341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2748514196 # Simulator tick rate (ticks/s) -host_mem_usage 389880 # Number of bytes of host memory used -host_seconds 935.90 # Real time elapsed on the host -sim_insts 61834256 # Number of instructions simulated -sim_ops 79870174 # Number of ops (including micro ops) simulated +host_inst_rate 81031 # Simulator instruction rate (inst/s) +host_op_rate 104662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3370719075 # Simulator tick rate (ticks/s) +host_mem_usage 387768 # Number of bytes of host memory used +host_seconds 763.09 # Real time elapsed on the host +sim_insts 61833482 # Number of instructions simulated +sim_ops 79866272 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,249 +20,249 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131402148 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10205776 # Number of bytes written to this memory -system.physmem.num_reads 15127689 # Number of read requests responded to by this memory -system.physmem.num_writes 869419 # Number of write requests responded to by this memory +system.physmem.bytes_read 131401380 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1182400 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10205328 # Number of bytes written to this memory +system.physmem.num_reads 15127677 # Number of read requests responded to by this memory +system.physmem.num_writes 869412 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130931 # number of replacements -system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use -system.l2c.total_refs 1850900 # Total number of references to valid blocks. -system.l2c.sampled_refs 160584 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.526055 # Average number of references to valid blocks. +system.physmem.bw_read 51086174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 459693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3967623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55053797 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 130950 # number of replacements +system.l2c.tagsinuse 27519.569663 # Cycle average of tags in use +system.l2c.total_refs 1851108 # Total number of references to valid blocks. +system.l2c.sampled_refs 160575 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.527996 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.048154 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2916.118065 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468888000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493861000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131970428500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744865480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777562693 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32522428173 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213753480 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271423693 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164492856673 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061805 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051237 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853021 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.854551 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781633 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.600912 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643655 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.557358 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40056.762362 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.871708 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.350620 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.770641 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.775457 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40047.438330 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.215702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40098.701698 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -455,27 +452,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7800657 # DTB read hits -system.cpu0.dtb.read_misses 37871 # DTB read misses -system.cpu0.dtb.write_hits 4594363 # DTB write hits -system.cpu0.dtb.write_misses 6405 # DTB write misses +system.cpu0.dtb.read_hits 7779192 # DTB read hits +system.cpu0.dtb.read_misses 37115 # DTB read misses +system.cpu0.dtb.write_hits 4594295 # DTB write hits +system.cpu0.dtb.write_misses 6419 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2014 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 4597 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7838528 # DTB read accesses -system.cpu0.dtb.write_accesses 4600768 # DTB write accesses +system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7816307 # DTB read accesses +system.cpu0.dtb.write_accesses 4600714 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12395020 # DTB hits -system.cpu0.dtb.misses 44276 # DTB misses -system.cpu0.dtb.accesses 12439296 # DTB accesses -system.cpu0.itb.inst_hits 4047811 # ITB inst hits -system.cpu0.itb.inst_misses 4513 # ITB inst misses +system.cpu0.dtb.hits 12373487 # DTB hits +system.cpu0.dtb.misses 43534 # DTB misses +system.cpu0.dtb.accesses 12417021 # DTB accesses +system.cpu0.itb.inst_hits 4018220 # ITB inst hits +system.cpu0.itb.inst_misses 4575 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -484,122 +481,122 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1835 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses -system.cpu0.itb.hits 4047811 # DTB hits -system.cpu0.itb.misses 4513 # DTB misses -system.cpu0.itb.accesses 4052324 # DTB accesses -system.cpu0.numCycles 58217040 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4022795 # ITB inst accesses +system.cpu0.itb.hits 4018220 # DTB hits +system.cpu0.itb.misses 4575 # DTB misses +system.cpu0.itb.accesses 4022795 # DTB accesses +system.cpu0.numCycles 58073431 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5437293 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4256353 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3600228 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2674120 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 485080 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 65250 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11048158 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 28487074 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5437293 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3159200 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6739880 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1438397 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 59633 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 18694595 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6724 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 30266 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 80153 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4016097 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175657 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3180 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 37672027 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.986348 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.372863 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30938102 82.12% 82.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 539295 1.43% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 754456 2.00% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 605374 1.61% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 572205 1.52% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 499727 1.33% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 619840 1.65% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 357335 0.95% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2785693 7.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 37672027 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.093628 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.490535 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11376766 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18792478 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6048489 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 500890 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 953404 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 867804 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 60437 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 35787038 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 193524 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 953404 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11914000 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 4629145 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12457249 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6001220 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1717009 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 34527596 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 354930 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 888723 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 49 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 34587688 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 157020073 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 156979210 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 40863 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26885692 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7701996 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 453005 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414730 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4495926 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6704710 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5162827 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 858153 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 869893 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32576471 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 727676 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32778157 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81649 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5740307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13396786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 126207 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 37672027 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.870093 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506550 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 24340985 64.61% 64.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5232872 13.89% 78.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2696429 7.16% 85.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2005933 5.32% 90.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1857666 4.93% 95.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 789251 2.10% 98.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 535159 1.42% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 163101 0.43% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 50631 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 37672027 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17215 1.80% 1.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 476 0.05% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available @@ -627,391 +624,388 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 744103 77.93% 79.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 193089 20.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 19588840 59.76% 59.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 43482 0.13% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8219170 25.08% 85.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4911355 14.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued -system.cpu0.iq.rate 0.564768 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 32778157 # Type of FU issued +system.cpu0.iq.rate 0.564426 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 954883 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029132 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 104296789 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 39048181 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 30070598 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10781 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5570 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4438 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 33712886 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5873 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 258573 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1274599 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3983 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9698 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 554608 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1948828 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5242 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 205793 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 324259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 953404 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 3530697 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 77233 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33359153 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 131395 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6704710 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5162827 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 457179 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 36756 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4503 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9698 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 188494 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 122646 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 311140 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32365577 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8053232 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 412580 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 54681 # number of nop insts executed -system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4282280 # Number of branches executed -system.cpu0.iew.exec_stores 4857867 # Number of stores executed -system.cpu0.iew.exec_rate 0.557341 # Inst execution rate -system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 16076835 # num instructions producing a value -system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value +system.cpu0.iew.exec_nop 55006 # number of nop insts executed +system.cpu0.iew.exec_refs 12911062 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4264405 # Number of branches executed +system.cpu0.iew.exec_stores 4857830 # Number of stores executed +system.cpu0.iew.exec_rate 0.557322 # Inst execution rate +system.cpu0.iew.wb_sent 32156724 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 30075036 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 16051487 # num instructions producing a value +system.cpu0.iew.wb_consumers 31416706 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.517879 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.510922 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 20629701 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 27347563 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 5860569 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601469 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 274713 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 36749403 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.744163 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.705264 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 26406070 71.85% 71.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5210331 14.18% 86.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1671532 4.55% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 813872 2.21% 92.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 646917 1.76% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 387096 1.05% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 442946 1.21% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 193384 0.53% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 977255 2.66% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 20629504 # Number of instructions committed -system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 36749403 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 20629701 # Number of instructions committed +system.cpu0.commit.committedOps 27347563 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10038315 # Number of memory references committed -system.cpu0.commit.loads 5430093 # Number of loads committed +system.cpu0.commit.refs 10038330 # Number of memory references committed +system.cpu0.commit.loads 5430111 # Number of loads committed system.cpu0.commit.membars 201113 # Number of memory barriers committed -system.cpu0.commit.branches 3777887 # Number of branches committed +system.cpu0.commit.branches 3777893 # Number of branches committed system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions. -system.cpu0.commit.function_calls 441072 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 24270810 # Number of committed integer instructions. +system.cpu0.commit.function_calls 441070 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 977255 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 68594693 # The number of ROB reads -system.cpu0.rob.rob_writes 67665332 # The number of ROB writes -system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 20604950 # Number of Instructions Simulated -system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated -system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads -system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads -system.cpu0.fp_regfile_writes 420 # number of floating regfile writes -system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes -system.cpu0.icache.replacements 364224 # number of replacements -system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use -system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 68333926 # The number of ROB reads +system.cpu0.rob.rob_writes 67371686 # The number of ROB writes +system.cpu0.timesIdled 379272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 20401404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5085475083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 20605147 # Number of Instructions Simulated +system.cpu0.committedOps 27323009 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 20605147 # Number of Instructions Simulated +system.cpu0.cpi 2.818394 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.818394 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.354812 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.354812 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 150871425 # number of integer regfile reads +system.cpu0.int_regfile_writes 29495246 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4612 # number of floating regfile reads +system.cpu0.fp_regfile_writes 442 # number of floating regfile writes +system.cpu0.misc_regfile_reads 40364553 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457015 # number of misc regfile writes +system.cpu0.icache.replacements 364779 # number of replacements +system.cpu0.icache.tagsinuse 511.052726 # Cycle average of tags in use +system.cpu0.icache.total_refs 3619396 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 365291 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.908254 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.052726 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits -system.cpu0.icache.overall_hits::total 3649617 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses -system.cpu0.icache.overall_misses::total 395923 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3619396 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3619396 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3619396 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3619396 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3619396 # number of overall hits +system.cpu0.icache.overall_hits::total 3619396 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 396554 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 396554 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 396554 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 396554 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 396554 # number of overall misses +system.cpu0.icache.overall_misses::total 396554 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6048062987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6048062987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6048062987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6048062987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6048062987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6048062987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4015950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4015950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4015950 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4015950 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4015950 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4015950 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked +system.cpu0.dcache.demand_misses::cpu0.data 1804300 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1804300 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1804300 # number of overall misses +system.cpu0.dcache.overall_misses::total 1804300 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4785519500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4785519500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60142300903 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60142300903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99268000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99268000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83415000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 83415000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64927820403 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64927820403 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64927820403 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64927820403 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5324661 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5324661 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4177156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167434 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167434 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164045 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 164045 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9501817 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9501817 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9501817 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9501817 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351046 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051734 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189890 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189890 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14161.442150 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41014.298469 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11460.170861 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10782.704240 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4268990 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2272500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 373 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 104 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11445.013405 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21850.961538 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks -system.cpu0.dcache.writebacks::total 213312 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 213485 # number of writebacks +system.cpu0.dcache.writebacks::total 213485 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174573 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 174573 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346571 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1346571 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1521144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1521144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1521144 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1521144 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 163353 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119803 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 119803 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8048 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8048 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 283156 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283156 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 283156 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283156 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2116822500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2116822500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4307053989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4307053989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66689500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66689500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60159000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60159000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6423876489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6423876489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6423876489 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6423876489 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482121000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482121000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884869891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884869891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366990891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366990891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048067 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047152 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12958.577437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35951.136357 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8286.468688 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7777.504848 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 44928224 # DTB read hits -system.cpu1.dtb.read_misses 73602 # DTB read misses -system.cpu1.dtb.write_hits 7780505 # DTB write hits -system.cpu1.dtb.write_misses 20150 # DTB write misses +system.cpu1.dtb.read_hits 44907962 # DTB read hits +system.cpu1.dtb.read_misses 73330 # DTB read misses +system.cpu1.dtb.write_hits 7780018 # DTB write hits +system.cpu1.dtb.write_misses 20100 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2652 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 7203 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 561 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45001826 # DTB read accesses -system.cpu1.dtb.write_accesses 7800655 # DTB write accesses +system.cpu1.dtb.perms_faults 1824 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 44981292 # DTB read accesses +system.cpu1.dtb.write_accesses 7800118 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 52708729 # DTB hits -system.cpu1.dtb.misses 93752 # DTB misses -system.cpu1.dtb.accesses 52802481 # DTB accesses -system.cpu1.itb.inst_hits 10224529 # ITB inst hits -system.cpu1.itb.inst_misses 7346 # ITB inst misses +system.cpu1.dtb.hits 52687980 # DTB hits +system.cpu1.dtb.misses 93430 # DTB misses +system.cpu1.dtb.accesses 52781410 # DTB accesses +system.cpu1.itb.inst_hits 10156376 # ITB inst hits +system.cpu1.itb.inst_misses 7457 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1024,503 +1018,503 @@ system.cpu1.itb.flush_entries 1545 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 5007 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses -system.cpu1.itb.hits 10224529 # DTB hits -system.cpu1.itb.misses 7346 # DTB misses -system.cpu1.itb.accesses 10231875 # DTB accesses -system.cpu1.numCycles 361675233 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10163833 # ITB inst accesses +system.cpu1.itb.hits 10156376 # DTB hits +system.cpu1.itb.misses 7457 # DTB misses +system.cpu1.itb.accesses 10163833 # DTB accesses +system.cpu1.numCycles 361463197 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits +system.cpu1.BPredUnit.lookups 10782508 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8772381 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 635923 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7402063 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5909244 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 873700 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 139717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 23605299 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 77286787 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 10782508 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6782944 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16557542 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5336622 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 96051 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 76350866 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 106359 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 159348 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 263 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10151102 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 836280 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4015 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 120517405 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782275 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.157111 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 103969658 86.27% 86.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 987113 0.82% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1198247 0.99% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2181121 1.81% 89.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1404675 1.17% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 731318 0.61% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2384511 1.98% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 517678 0.43% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7143084 5.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 120517405 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029830 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.213816 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 25233877 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76283550 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 14821072 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 657863 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3521043 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1494975 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 117774 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 87693964 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 382895 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3521043 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 26831414 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32478721 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 39236731 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 13889721 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4559775 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 81167341 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2581 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 635823 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3200516 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 46226 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 85740662 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 375398775 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 375349065 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 49710 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 53651640 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 32089021 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 776045 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 700116 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8935980 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15610664 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9406979 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1201620 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1579608 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 72666150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1193677 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 96590201 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 142158 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20735703 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 58926609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 234264 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 120517405 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.801463 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.526860 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86833748 72.05% 72.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9975019 8.28% 80.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4940804 4.10% 84.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4069487 3.38% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11024826 9.15% 96.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2090694 1.73% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1200483 1.00% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 289311 0.24% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 93033 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 120517405 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 40307 0.50% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7705811 95.37% 95.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 333073 4.12% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 92768 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 42073039 43.56% 43.65% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 68661 0.07% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 25 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 44 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1453 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46174618 47.80% 91.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8179589 8.47% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued -system.cpu1.iq.rate 0.267369 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 96590201 # Type of FU issued +system.cpu1.iq.rate 0.267220 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8080188 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083654 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 322001182 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94611209 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 59943384 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12160 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6852 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5542 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 104571300 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6321 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377653 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4689619 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6336 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 23311 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1773508 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32175805 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149678 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3521043 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25065136 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359091 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 74029865 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 214492 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15610664 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9406979 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 810165 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 59786 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8576 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 23311 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 385716 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 238696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 624412 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 93721321 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45339640 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2868880 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 169844 # number of nop insts executed -system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7814764 # Number of branches executed -system.cpu1.iew.exec_stores 8083565 # Number of stores executed -system.cpu1.iew.exec_rate 0.259338 # Inst execution rate -system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 32803499 # num instructions producing a value -system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value +system.cpu1.iew.exec_nop 170038 # number of nop insts executed +system.cpu1.iew.exec_refs 53422835 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7793526 # Number of branches executed +system.cpu1.iew.exec_stores 8083195 # Number of stores executed +system.cpu1.iew.exec_rate 0.259283 # Inst execution rate +system.cpu1.iew.wb_sent 92395030 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 59948926 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 32815937 # num instructions producing a value +system.cpu1.iew.wb_consumers 59243985 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.165851 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.553912 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 41354162 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 52669090 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 21302262 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 959413 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 549125 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 117050265 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.449970 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.406060 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97973751 83.70% 83.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9696174 8.28% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2557084 2.18% 94.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1440070 1.23% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1185226 1.01% 96.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 698819 0.60% 97.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1094067 0.93% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 501455 0.43% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1903619 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41355133 # Number of instructions committed -system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 117050265 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41354162 # Number of instructions committed +system.cpu1.commit.committedOps 52669090 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18556919 # Number of memory references committed -system.cpu1.commit.loads 10922280 # Number of loads committed -system.cpu1.commit.membars 235767 # Number of memory barriers committed -system.cpu1.commit.branches 6572492 # Number of branches committed +system.cpu1.commit.refs 18554516 # Number of memory references committed +system.cpu1.commit.loads 10921045 # Number of loads committed +system.cpu1.commit.membars 235754 # Number of memory barriers committed +system.cpu1.commit.branches 6572629 # Number of branches committed system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions. -system.cpu1.commit.function_calls 612387 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 46931412 # Number of committed integer instructions. +system.cpu1.commit.function_calls 612362 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1903619 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 188242511 # The number of ROB reads -system.cpu1.rob.rob_writes 151809339 # The number of ROB writes -system.cpu1.timesIdled 1543775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 240936392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4782922080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41229306 # Number of Instructions Simulated -system.cpu1.committedOps 52547337 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated -system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads -system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes -system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads -system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes -system.cpu1.icache.replacements 696666 # number of replacements -system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use -system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 697178 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.575185 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 187930171 # The number of ROB reads +system.cpu1.rob.rob_writes 151588010 # The number of ROB writes +system.cpu1.timesIdled 1544590 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 240945792 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4782780444 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41228335 # Number of Instructions Simulated +system.cpu1.committedOps 52543263 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 41228335 # Number of Instructions Simulated +system.cpu1.cpi 8.767349 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.767349 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.114060 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.114060 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 421568276 # number of integer regfile reads +system.cpu1.int_regfile_writes 62748878 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4369 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2038 # number of floating regfile writes +system.cpu1.misc_regfile_reads 99504542 # number of misc regfile reads +system.cpu1.misc_regfile_writes 498546 # number of misc regfile writes +system.cpu1.icache.replacements 696735 # number of replacements +system.cpu1.icache.tagsinuse 498.773379 # Cycle average of tags in use +system.cpu1.icache.total_refs 9395224 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 697247 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.474743 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.774287 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974169 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974169 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9464320 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9464320 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9464320 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9464320 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9464320 # number of overall hits -system.cpu1.icache.overall_hits::total 9464320 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 754908 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 754908 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 754908 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 754908 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 754908 # number of overall misses -system.cpu1.icache.overall_misses::total 754908 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11029274493 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11029274493 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11029274493 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11029274493 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11029274493 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11029274493 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10219228 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10219228 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10219228 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10219228 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10219228 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10219228 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073871 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073871 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073871 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14610.090889 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 498.773379 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974167 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974167 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9395224 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9395224 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9395224 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9395224 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9395224 # number of overall hits +system.cpu1.icache.overall_hits::total 9395224 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 755826 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 755826 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 755826 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 755826 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 755826 # number of overall misses +system.cpu1.icache.overall_misses::total 755826 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11037584991 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11037584991 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11037584991 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11037584991 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11037584991 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11037584991 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10151050 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10151050 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10151050 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10151050 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 33229 # number of writebacks +system.cpu1.icache.writebacks::total 33229 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 58554 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 58554 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 58554 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 58554 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 58554 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8249763494 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8249763494 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # 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number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16653546 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16653546 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16653546 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16653546 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044559 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263430 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102854 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079826 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15033.206785 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33391.295681 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12045.425645 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8474.183976 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 14003056 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5014500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3116 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 133 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4493.920411 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37703.007519 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks -system.cpu1.dcache.writebacks::total 337861 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 337879 # number of writebacks +system.cpu1.dcache.writebacks::total 337879 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 192117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 192117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1524857 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1524857 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1136 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1136 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1716974 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1716974 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1716974 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1716974 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262519 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 262519 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174391 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 174391 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13019 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13019 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10105 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10105 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 436910 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 436910 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 436910 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 436910 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3282878000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3282878000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5492297055 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5492297055 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 117597000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 117597000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55303500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55303500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8775175055 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8775175055 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8775175055 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8775175055 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933377000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933377000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618372048 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618372048 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551749048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551749048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025729 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027035 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094600 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079786 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12505.296759 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31494.154257 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.721407 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.884711 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -1539,16 +1533,16 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308183454966 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308183454966 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 38029 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 59437 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status index e41fe50a6..696134c20 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status @@ -1 +1 @@ -build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED! +build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED! diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 5275111e5..e0ab5975e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,13 +10,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.realview.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c7a1b63e2..9c3dda86e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:34:20 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:45:32 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503289265500 because m5_exit instruction encountered +Exiting @ tick 2503099557500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c91fe0ed5..f897e20de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503289 # Number of seconds simulated -sim_ticks 2503289265500 # Number of ticks simulated -final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503100 # Number of seconds simulated +sim_ticks 2503099557500 # Number of ticks simulated +final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65661 # Simulator instruction rate (inst/s) -host_op_rate 84813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2764710189 # Simulator tick rate (ticks/s) -host_mem_usage 389064 # Number of bytes of host memory used -host_seconds 905.44 # Real time elapsed on the host -sim_insts 59452703 # Number of instructions simulated -sim_ops 76793713 # Number of ops (including micro ops) simulated +host_inst_rate 80117 # Simulator instruction rate (inst/s) +host_op_rate 103484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3373282088 # Simulator tick rate (ticks/s) +host_mem_usage 383952 # Number of bytes of host memory used +host_seconds 742.04 # Real time elapsed on the host +sim_insts 59449445 # Number of instructions simulated +sim_ops 76789092 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130753040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9587720 # Number of bytes written to this memory -system.physmem.num_reads 15117482 # Number of read requests responded to by this memory -system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.bytes_read 130740776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9586312 # Number of bytes written to this memory +system.physmem.num_reads 15115704 # Number of read requests responded to by this memory +system.physmem.num_writes 856678 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119784 # number of replacements -system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use -system.l2c.total_refs 1841990 # Total number of references to valid blocks. -system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119794 # number of replacements +system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use +system.l2c.total_refs 1840774 # Total number of references to valid blocks. +system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.483052 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu.inst 17382 # number of overall misses +system.l2c.overall_misses::cpu.data 159492 # number of overall misses +system.l2c.overall_misses::total 177033 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7379766500 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246311 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246311 # 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miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017089 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.248099 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017089 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.248099 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53583.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52411.771488 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52295.753682 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 302.971188 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52587.905823 # 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miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -170,100 +170,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102682 # number of writebacks -system.l2c.writebacks::total 102682 # number of writebacks +system.l2c.writebacks::writebacks 102660 # number of writebacks +system.l2c.writebacks::total 102660 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 79 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 79 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 150 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 147 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17335 # 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number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17335 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159398 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176894 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6012000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 462000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 696908500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765299500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1468682000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 134589000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176940 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5904000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697218500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765075000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1468639500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 133817000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 133817000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636704500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5636704500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6012000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 462000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 696908500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6402004000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7105386500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6012000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 462000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 696908500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6402004000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7105386500 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131761112000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131766619000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348627763 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,27 +278,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51991464 # DTB read hits -system.cpu.dtb.read_misses 102104 # DTB read misses -system.cpu.dtb.write_hits 11910179 # DTB write hits -system.cpu.dtb.write_misses 24558 # DTB write misses +system.cpu.dtb.read_hits 51948606 # DTB read hits +system.cpu.dtb.read_misses 101816 # DTB read misses +system.cpu.dtb.write_hits 11910706 # DTB write hits +system.cpu.dtb.write_misses 24423 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4433 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4440 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52093568 # DTB read accesses -system.cpu.dtb.write_accesses 11934737 # DTB write accesses +system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52050422 # DTB read accesses +system.cpu.dtb.write_accesses 11935129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63901643 # DTB hits -system.cpu.dtb.misses 126662 # DTB misses -system.cpu.dtb.accesses 64028305 # DTB accesses -system.cpu.itb.inst_hits 13706914 # ITB inst hits -system.cpu.itb.inst_misses 11634 # ITB inst misses +system.cpu.dtb.hits 63859312 # DTB hits +system.cpu.dtb.misses 126239 # DTB misses +system.cpu.dtb.accesses 63985551 # DTB accesses +system.cpu.itb.inst_hits 13611127 # ITB inst hits +system.cpu.itb.inst_misses 11794 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -307,504 +307,504 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2596 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2614 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13718548 # ITB inst accesses -system.cpu.itb.hits 13706914 # DTB hits -system.cpu.itb.misses 11634 # DTB misses -system.cpu.itb.accesses 13718548 # DTB accesses -system.cpu.numCycles 414369636 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13622921 # ITB inst accesses +system.cpu.itb.hits 13611127 # DTB hits +system.cpu.itb.misses 11794 # DTB misses +system.cpu.itb.accesses 13622921 # DTB accesses +system.cpu.numCycles 414035717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits +system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued -system.cpu.iq.rate 0.304001 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued +system.cpu.iq.rate 0.303772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 597024 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 929867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216034 # number of nop insts executed -system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed -system.cpu.iew.exec_branches 11571925 # Number of branches executed -system.cpu.iew.exec_stores 12419635 # Number of stores executed -system.cpu.iew.exec_rate 0.296062 # Inst execution rate -system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46911516 # num instructions producing a value -system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value +system.cpu.iew.exec_nop 216875 # number of nop insts executed +system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed +system.cpu.iew.exec_branches 11533456 # Number of branches executed +system.cpu.iew.exec_stores 12420416 # Number of stores executed +system.cpu.iew.exec_rate 0.295954 # Inst execution rate +system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46901063 # num instructions producing a value +system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59603084 # Number of instructions committed -system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59599826 # Number of instructions committed +system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27461448 # Number of memory references committed -system.cpu.commit.loads 15681836 # Number of loads committed -system.cpu.commit.membars 413071 # Number of memory barriers committed -system.cpu.commit.branches 9891470 # Number of branches committed +system.cpu.commit.refs 27459254 # Number of memory references committed +system.cpu.commit.loads 15680449 # Number of loads committed +system.cpu.commit.membars 413031 # Number of memory barriers committed +system.cpu.commit.branches 9890920 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. -system.cpu.commit.function_calls 995631 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. +system.cpu.commit.function_calls 995546 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 248361579 # The number of ROB reads -system.cpu.rob.rob_writes 211126300 # The number of ROB writes -system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59452703 # Number of Instructions Simulated -system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated -system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556236612 # number of integer regfile reads -system.cpu.int_regfile_writes 88987615 # number of integer regfile writes -system.cpu.fp_regfile_reads 8813 # number of floating regfile reads -system.cpu.fp_regfile_writes 2942 # number of floating regfile writes -system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads -system.cpu.misc_regfile_writes 912350 # number of misc regfile writes -system.cpu.icache.replacements 1015901 # number of replacements -system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use -system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 247831805 # The number of ROB reads +system.cpu.rob.rob_writes 210661614 # The number of ROB writes +system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59449445 # Number of Instructions Simulated +system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated +system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555570054 # number of integer regfile reads +system.cpu.int_regfile_writes 88783658 # number of integer regfile writes +system.cpu.fp_regfile_reads 8868 # number of floating regfile reads +system.cpu.fp_regfile_writes 2963 # number of floating regfile writes +system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads +system.cpu.misc_regfile_writes 912266 # number of misc regfile writes +system.cpu.icache.replacements 1016880 # number of replacements +system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use +system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits -system.cpu.icache.overall_hits::total 12592690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses -system.cpu.icache.overall_misses::total 1106667 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits +system.cpu.icache.overall_hits::total 12495254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses +system.cpu.icache.overall_misses::total 1108036 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 58562 # number of writebacks -system.cpu.icache.writebacks::total 58562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 58719 # number of writebacks +system.cpu.icache.writebacks::total 58719 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645034 # number of replacements -system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use -system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644925 # number of replacements +system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use +system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14161876 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14161876 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7265482 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7265482 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 286317 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 286317 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285516 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285516 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21427358 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21427358 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21427358 # number of overall hits -system.cpu.dcache.overall_hits::total 21427358 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 733645 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 733645 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966203 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966203 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13700 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13700 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 14117520 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14117520 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7264910 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264910 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285961 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285961 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285492 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285492 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21382430 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21382430 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21382430 # number of overall hits +system.cpu.dcache.overall_hits::total 21382430 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 735373 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 735373 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966010 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966010 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13726 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13726 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3701383 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701383 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701383 # number of overall misses +system.cpu.dcache.overall_misses::total 3701383 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11086457500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11086457500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110422837752 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110422837752 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223704000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223704000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285524 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285524 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25127206 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25127206 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25127206 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25127206 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045664 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 121509295252 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121509295252 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121509295252 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121509295252 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14852893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14852893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299687 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25083813 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25083813 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25083813 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25083813 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289906 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15060.913657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37222.922120 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16284.562044 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.147561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15075.964850 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16049941 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7647500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2833 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5665.351571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27910.583942 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574496 # number of writebacks -system.cpu.dcache.writebacks::total 574496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 346626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716633 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716633 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1361 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1361 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3063259 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3063259 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3063259 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3063259 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387019 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387019 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249570 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249570 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12339 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks +system.cpu.dcache.writebacks::total 574454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636589 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636589 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636589 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636589 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265487500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265487500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926165441 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926165441 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165358500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191652941 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14191652941 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191652941 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14191652941 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147155039500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147155039500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42275098470 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42275098470 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189430137970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189430137970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.242895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35766.179593 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13401.288597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -823,14 +823,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |