diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/fs/10.linux-boot | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot')
18 files changed, 6259 insertions, 6274 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9e5305367..94dc81bdc 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:31:55 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:55 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107002000 -Exiting @ tick 1899401490000 because m5_exit instruction encountered +info: Launching CPU 1 @ 106801000 +Exiting @ tick 1896395899500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e3ecd4b02..0c462a770 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899401 # Number of seconds simulated -sim_ticks 1899401490000 # Number of ticks simulated -final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.896396 # Number of seconds simulated +sim_ticks 1896395899500 # Number of ticks simulated +final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124517 # Simulator instruction rate (inst/s) -host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4182952627 # Simulator tick rate (ticks/s) -host_mem_usage 300876 # Number of bytes of host memory used -host_seconds 454.08 # Real time elapsed on the host -sim_insts 56540749 # Number of instructions simulated -sim_ops 56540749 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory -system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory -system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory -system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397771 # number of replacements -system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use -system.l2c.total_refs 2469954 # Total number of references to valid blocks. -system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits -system.l2c.Writeback_hits::total 806294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits -system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits -system.l2c.overall_hits::cpu0.data 822730 # number of overall hits -system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits -system.l2c.overall_hits::cpu1.data 135531 # number of overall hits -system.l2c.overall_hits::total 2042553 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses -system.l2c.demand_misses::total 434620 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses -system.l2c.overall_misses::cpu0.data 397745 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses -system.l2c.overall_misses::cpu1.data 19147 # number of overall misses -system.l2c.overall_misses::total 434620 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 707237500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20745010000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 220139500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 998215500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22670602500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 707237500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20745010000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 220139500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 998215500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22670602500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 924232 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 957077 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 177788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 121001 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2180098 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 806294 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 806294 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 824 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3932 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 286 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 324 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 610 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 263398 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 33677 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 297075 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 924232 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1220475 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 177788 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 154678 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2477173 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 924232 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1220475 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 177788 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 154678 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2477173 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency +host_inst_rate 196112 # Simulator instruction rate (inst/s) +host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6628227410 # Simulator tick rate (ticks/s) +host_mem_usage 302056 # Number of bytes of host memory used +host_seconds 286.11 # Real time elapsed on the host +sim_insts 56109524 # Number of instructions simulated +sim_ops 56109524 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory +system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 464949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13082028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 249231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19394296 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 344859 # number of replacements +system.l2c.tagsinuse 65321.127934 # Cycle average of tags in use +system.l2c.total_refs 2609636 # Total number of references to valid blocks. +system.l2c.sampled_refs 410035 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.364423 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6312493000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53767.491128 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5338.607060 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6047.920982 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 140.590955 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 26.517809 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.820427 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.081461 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.092284 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002145 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000405 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996721 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 978177 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 784326 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 102747 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33274 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1898524 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 832872 # number of Writeback hits +system.l2c.Writeback_hits::total 832872 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 159 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 200 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 175658 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 7994 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183652 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 978177 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 959984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 102747 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 41268 # number of demand (read+write) hits +system.l2c.demand_hits::total 2082176 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 978177 # number of overall hits +system.l2c.overall_hits::cpu0.data 959984 # number of overall hits +system.l2c.overall_hits::cpu1.inst 102747 # number of overall hits +system.l2c.overall_hits::cpu1.data 41268 # number of overall hits +system.l2c.overall_hits::total 2082176 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13779 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273160 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1574 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 765 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289278 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2448 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 557 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3005 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 42 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 122 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 114897 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6716 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121613 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13779 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 388057 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1574 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7481 # number of demand (read+write) misses +system.l2c.demand_misses::total 410891 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13779 # number of overall misses +system.l2c.overall_misses::cpu0.data 388057 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1574 # number of overall misses +system.l2c.overall_misses::cpu1.data 7481 # number of overall misses +system.l2c.overall_misses::total 410891 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 720793500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14208419500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 82364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 41213000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15052790000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2256000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1409000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 3665000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 419000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 157000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 576000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6027292500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 352112000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6379404500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 720793500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20235712000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 82364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 393325000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21432194500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 720793500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20235712000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 82364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 393325000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21432194500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 991956 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1057486 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 104321 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 34039 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2187802 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 832872 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832872 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 598 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3205 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 71 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 102 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 173 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 290555 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 14710 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305265 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 991956 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1348041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 104321 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 48749 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2493067 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 991956 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1348041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 104321 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 48749 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2493067 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.258311 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015088 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.022474 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132223 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939010 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.931438 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.937598 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591549 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784314 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.705202 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.395440 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.456560 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.398385 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.287867 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015088 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.153460 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164813 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.287867 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015088 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.153460 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164813 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52035.723422 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 921.568627 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2529.622980 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1219.633943 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9976.190476 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1962.500000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4721.311475 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52456.600035 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52160.291902 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52160.291902 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 122679 # number of writebacks -system.l2c.writebacks::total 122679 # number of writebacks +system.l2c.writebacks::writebacks 81384 # number of writebacks +system.l2c.writebacks::total 81384 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits @@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13520 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 288493 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4190 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3184 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 309387 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2939 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 698 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3637 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 248 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 292 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 540 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 109252 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15963 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 125215 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13520 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 397745 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4190 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 19147 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 434602 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13520 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 397745 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4190 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 19147 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 434602 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 541689500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11548328000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 167980000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 125604000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12383601500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117566000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27923000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 145489000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9921000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11680500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 21601500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4402693000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 641940500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5044633500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 541689500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15951021000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 167980000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 767544500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17428235000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 541689500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15951021000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 167980000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 767544500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17428235000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 568678500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269407000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 838085500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 961824498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 507055500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1468879998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1530502998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 776462500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2306965498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141914 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.924975 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.885246 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.421493 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.175443 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.175443 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40026.250295 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40002.474567 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40002.777778 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40287.773030 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13778 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1557 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 765 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289260 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2448 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 557 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3005 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 42 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 122 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 114897 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6716 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121613 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13778 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 388057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1557 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7481 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410873 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13778 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 388057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1557 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7481 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410873 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 552060500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10929358000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62432500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 31914000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11575765000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97983500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22281000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 120264500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1681500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3200000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4881500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4629799500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270393000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4900192500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 552060500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15559157500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 62432500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 302307000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16475957500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 552060500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15559157500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 62432500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 302307000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16475957500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 821481000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16663000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 838144000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1131946998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 287746500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1419693498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1953427998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 304409500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2257837498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.258311 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132215 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939010 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.931438 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.937598 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591549 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784314 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.705202 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.395440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.456560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.398385 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164806 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164806 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40010.828818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41717.647059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.547328 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.939542 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.795332 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40021.464226 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.714286 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40012.295082 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40295.216585 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40261.018463 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.328016 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.205020 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.462803 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708344834000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.205020 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.012814 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012814 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.warmup_cycle 1708345741000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.462803 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.028925 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.028925 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20513998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20513998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5720296806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5720296806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5740810804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5740810804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5740810804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5740810804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11257998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11257998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8814586 # DTB read hits -system.cpu0.dtb.read_misses 32972 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 619797 # DTB read accesses -system.cpu0.dtb.write_hits 5858085 # DTB write hits -system.cpu0.dtb.write_misses 6892 # DTB write misses -system.cpu0.dtb.write_acv 315 # DTB write access violations -system.cpu0.dtb.write_accesses 207416 # DTB write accesses -system.cpu0.dtb.data_hits 14672671 # DTB hits -system.cpu0.dtb.data_misses 39864 # DTB misses -system.cpu0.dtb.data_acv 833 # DTB access violations -system.cpu0.dtb.data_accesses 827213 # DTB accesses -system.cpu0.itb.fetch_hits 1034325 # ITB hits -system.cpu0.itb.fetch_misses 27665 # ITB misses -system.cpu0.itb.fetch_acv 1025 # ITB acv -system.cpu0.itb.fetch_accesses 1061990 # ITB accesses +system.cpu0.dtb.read_hits 9453856 # DTB read hits +system.cpu0.dtb.read_misses 36184 # DTB read misses +system.cpu0.dtb.read_acv 571 # DTB read access violations +system.cpu0.dtb.read_accesses 675976 # DTB read accesses +system.cpu0.dtb.write_hits 6300368 # DTB write hits +system.cpu0.dtb.write_misses 8347 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 234133 # DTB write accesses +system.cpu0.dtb.data_hits 15754224 # DTB hits +system.cpu0.dtb.data_misses 44531 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 910109 # DTB accesses +system.cpu0.itb.fetch_hits 1108660 # ITB hits +system.cpu0.itb.fetch_misses 28136 # ITB misses +system.cpu0.itb.fetch_acv 1047 # ITB acv +system.cpu0.itb.fetch_accesses 1136796 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 105407779 # number of cpu cycles simulated +system.cpu0.numCycles 111705884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued -system.cpu0.iq.rate 0.482387 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued +system.cpu0.iq.rate 0.489657 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3218084 # number of nop insts executed -system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7980527 # Number of branches executed -system.cpu0.iew.exec_stores 5879131 # Number of stores executed -system.cpu0.iew.exec_rate 0.477396 # Inst execution rate -system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24623982 # num instructions producing a value -system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value +system.cpu0.iew.exec_nop 3462690 # number of nop insts executed +system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8639850 # Number of branches executed +system.cpu0.iew.exec_stores 6323117 # Number of stores executed +system.cpu0.iew.exec_rate 0.485366 # Inst execution rate +system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26624302 # num instructions producing a value +system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50284711 # Number of instructions committed -system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54183968 # Number of instructions committed +system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13762834 # Number of memory references committed -system.cpu0.commit.loads 8083571 # Number of loads committed -system.cpu0.commit.membars 205088 # Number of memory barriers committed -system.cpu0.commit.branches 7564309 # Number of branches committed -system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. -system.cpu0.commit.function_calls 644133 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14789754 # Number of memory references committed +system.cpu0.commit.loads 8697139 # Number of loads committed +system.cpu0.commit.membars 219715 # Number of memory barriers committed +system.cpu0.commit.branches 8176675 # Number of branches committed +system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. +system.cpu0.commit.function_calls 709743 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126892294 # The number of ROB reads -system.cpu0.rob.rob_writes 115369853 # The number of ROB writes -system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47376653 # Number of Instructions Simulated -system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated -system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads -system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes -system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads -system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes +system.cpu0.rob.rob_reads 136054419 # The number of ROB reads +system.cpu0.rob.rob_writes 123888625 # The number of ROB writes +system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51051860 # Number of Instructions Simulated +system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated +system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads +system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes +system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads +system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 923652 # number of replacements -system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use -system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits -system.cpu0.icache.overall_hits::total 6902434 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses -system.cpu0.icache.overall_misses::total 973969 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked +system.cpu0.icache.replacements 991395 # number of replacements +system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use +system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits +system.cpu0.icache.overall_hits::total 7272203 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses +system.cpu0.icache.overall_misses::total 1045096 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 196 # number of writebacks -system.cpu0.icache.writebacks::total 196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 253 # number of writebacks +system.cpu0.icache.writebacks::total 253 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1225027 # number of replacements -system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits -system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses -system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1352160 # number of replacements +system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits +system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses +system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks -system.cpu0.dcache.writebacks::total 689568 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks +system.cpu0.dcache.writebacks::total 805259 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1967803 # DTB read hits -system.cpu1.dtb.read_misses 13979 # DTB read misses -system.cpu1.dtb.read_acv 50 # DTB read access violations -system.cpu1.dtb.read_accesses 344857 # DTB read accesses -system.cpu1.dtb.write_hits 1156959 # DTB write hits -system.cpu1.dtb.write_misses 3426 # DTB write misses -system.cpu1.dtb.write_acv 86 # DTB write access violations -system.cpu1.dtb.write_accesses 133134 # DTB write accesses -system.cpu1.dtb.data_hits 3124762 # DTB hits -system.cpu1.dtb.data_misses 17405 # DTB misses -system.cpu1.dtb.data_acv 136 # DTB access violations -system.cpu1.dtb.data_accesses 477991 # DTB accesses -system.cpu1.itb.fetch_hits 421916 # ITB hits -system.cpu1.itb.fetch_misses 9109 # ITB misses -system.cpu1.itb.fetch_acv 356 # ITB acv -system.cpu1.itb.fetch_accesses 431025 # ITB accesses +system.cpu1.dtb.read_hits 1211336 # DTB read hits +system.cpu1.dtb.read_misses 9865 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 283619 # DTB read accesses +system.cpu1.dtb.write_hits 674221 # DTB write hits +system.cpu1.dtb.write_misses 1908 # DTB write misses +system.cpu1.dtb.write_acv 40 # DTB write access violations +system.cpu1.dtb.write_accesses 107232 # DTB write accesses +system.cpu1.dtb.data_hits 1885557 # DTB hits +system.cpu1.dtb.data_misses 11773 # DTB misses +system.cpu1.dtb.data_acv 46 # DTB access violations +system.cpu1.dtb.data_accesses 390851 # DTB accesses +system.cpu1.itb.fetch_hits 332989 # ITB hits +system.cpu1.itb.fetch_misses 6158 # ITB misses +system.cpu1.itb.fetch_acv 143 # ITB acv +system.cpu1.itb.fetch_accesses 339147 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16642884 # number of cpu cycles simulated +system.cpu1.numCycles 8872891 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued -system.cpu1.iq.rate 0.613946 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued +system.cpu1.iq.rate 0.635693 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 532071 # number of nop insts executed -system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1559516 # Number of branches executed -system.cpu1.iew.exec_stores 1165063 # Number of stores executed -system.cpu1.iew.exec_rate 0.606457 # Inst execution rate -system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4916782 # num instructions producing a value -system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value +system.cpu1.iew.exec_nop 240621 # number of nop insts executed +system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed +system.cpu1.iew.exec_branches 816845 # Number of branches executed +system.cpu1.iew.exec_stores 679274 # Number of stores executed +system.cpu1.iew.exec_rate 0.628773 # Inst execution rate +system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2655801 # num instructions producing a value +system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9615778 # Number of instructions committed -system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5260797 # Number of instructions committed +system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2823987 # Number of memory references committed -system.cpu1.commit.loads 1739300 # Number of loads committed -system.cpu1.commit.membars 35653 # Number of memory barriers committed -system.cpu1.commit.branches 1422938 # Number of branches committed -system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. -system.cpu1.commit.function_calls 153476 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1687646 # Number of memory references committed +system.cpu1.commit.loads 1056770 # Number of loads committed +system.cpu1.commit.membars 18284 # Number of memory barriers committed +system.cpu1.commit.branches 746127 # Number of branches committed +system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. +system.cpu1.commit.function_calls 83297 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25542136 # The number of ROB reads -system.cpu1.rob.rob_writes 23473924 # The number of ROB writes -system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9164096 # Number of Instructions Simulated -system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated -system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads -system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes -system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads -system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes -system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads -system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes -system.cpu1.icache.replacements 177236 # number of replacements -system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use -system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits -system.cpu1.icache.overall_hits::total 1491482 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses -system.cpu1.icache.overall_misses::total 188398 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked +system.cpu1.rob.rob_reads 14229924 # The number of ROB reads +system.cpu1.rob.rob_writes 12929135 # The number of ROB writes +system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5057664 # Number of Instructions Simulated +system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated +system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads +system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes +system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads +system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes +system.cpu1.icache.replacements 103776 # number of replacements +system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use +system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits +system.cpu1.icache.overall_hits::total 841895 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses +system.cpu1.icache.overall_misses::total 109497 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 52 # number of writebacks -system.cpu1.icache.writebacks::total 52 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 39 # number of writebacks +system.cpu1.icache.writebacks::total 39 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 5150 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 5150 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 5150 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 5150 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 5150 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 104347 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 104347 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 104347 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 104347 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 104347 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 104347 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1240890499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1240890499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 156190 # number of replacements -system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 22430 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2413851 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2413851 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2413851 # number of overall hits -system.cpu1.dcache.overall_hits::total 2413851 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 229184 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 229184 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 231703 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 231703 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 3831 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 3831 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 1979 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 1979 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses -system.cpu1.dcache.overall_misses::total 460887 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked +system.cpu1.dcache.replacements 49122 # number of replacements +system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits +system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses +system.cpu1.dcache.overall_misses::total 193505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4676811320 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4676811320 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 52059498 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks -system.cpu1.dcache.writebacks::total 116478 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks +system.cpu1.dcache.writebacks::total 27321 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1589,166 +1589,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed -system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed -system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed -system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed -system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 175342 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 186310 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1161 -system.cpu0.kern.mode_good::user 1162 +system.cpu0.kern.mode_good::kernel 1345 +system.cpu0.kern.mode_good::user 1346 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3714 # number of times the context was actually changed +system.cpu0.kern.swap_context 3894 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed -system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed -system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed -system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed -system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed -system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed -system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed -system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed -system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed -system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed +system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 42196 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 747 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 169 -system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 30107 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 420 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 28 +system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 735 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f3bacddca..3b2f5c4a1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:16:04 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858684403000 because m5_exit instruction encountered +Exiting @ tick 1858879782500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index d7b6a1ccb..90f62bf97 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858684 # Number of seconds simulated -sim_ticks 1858684403000 # Number of ticks simulated -final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.858880 # Number of seconds simulated +sim_ticks 1858879782500 # Number of ticks simulated +final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125153 # Simulator instruction rate (inst/s) -host_op_rate 125153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4381630644 # Simulator tick rate (ticks/s) -host_mem_usage 297044 # Number of bytes of host memory used -host_seconds 424.20 # Real time elapsed on the host -sim_insts 53089851 # Number of instructions simulated -sim_ops 53089851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory -system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory -system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391653 # number of replacements -system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use -system.l2c.total_refs 2427420 # Total number of references to valid blocks. -system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits -system.l2c.Writeback_hits::total 834721 # number of Writeback hits +host_inst_rate 196297 # Simulator instruction rate (inst/s) +host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6876664069 # Simulator tick rate (ticks/s) +host_mem_usage 298988 # Number of bytes of host memory used +host_seconds 270.32 # Real time elapsed on the host +sim_insts 53062487 # Number of instructions simulated +sim_ops 53062487 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338457 # number of replacements +system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use +system.l2c.total_refs 2557615 # Total number of references to valid blocks. +system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits +system.l2c.Writeback_hits::total 841169 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits -system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits -system.l2c.overall_hits::cpu.data 994510 # number of overall hits -system.l2c.overall_hits::total 2003843 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses -system.l2c.demand_misses::total 425412 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 16915 # number of overall misses -system.l2c.overall_misses::cpu.data 408497 # number of overall misses -system.l2c.overall_misses::total 425412 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 884741000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 15168191000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16052932000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 425500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 425500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6138440500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6138440500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 884741000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 21306631500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22191372500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency +system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits +system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits +system.l2c.overall_hits::cpu.data 1012304 # number of overall hits +system.l2c.overall_hits::total 2018690 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses +system.l2c.demand_misses::total 404446 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15144 # number of overall misses +system.l2c.overall_misses::cpu.data 389302 # number of overall misses +system.l2c.overall_misses::total 404446 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,80 +145,72 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117800 # number of writebacks -system.l2c.writebacks::total 117800 # number of writebacks +system.l2c.writebacks::writebacks 76064 # number of writebacks +system.l2c.writebacks::total 76064 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1343000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1343000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4714582500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4714582500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 677644000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 16382770000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17060414000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 677644000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273879 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289022 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404445 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404445 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 606782500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10958767000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11565549500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 606782500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15612112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16218894500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 606782500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15612112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16218894500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166910 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166910 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266745 # Cycle average of tags in use +system.iocache.tagsinuse 1.268378 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +237,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721900806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721900806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741838804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741838804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741838804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741838804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +261,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +287,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +303,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +326,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10017178 # DTB read hits -system.cpu.dtb.read_misses 45828 # DTB read misses -system.cpu.dtb.read_acv 561 # DTB read access violations -system.cpu.dtb.read_accesses 954843 # DTB read accesses -system.cpu.dtb.write_hits 6639084 # DTB write hits -system.cpu.dtb.write_misses 10800 # DTB write misses -system.cpu.dtb.write_acv 415 # DTB write access violations -system.cpu.dtb.write_accesses 340295 # DTB write accesses -system.cpu.dtb.data_hits 16656262 # DTB hits -system.cpu.dtb.data_misses 56628 # DTB misses -system.cpu.dtb.data_acv 976 # DTB access violations -system.cpu.dtb.data_accesses 1295138 # DTB accesses -system.cpu.itb.fetch_hits 1345400 # ITB hits -system.cpu.itb.fetch_misses 36691 # ITB misses -system.cpu.itb.fetch_acv 1385 # ITB acv -system.cpu.itb.fetch_accesses 1382091 # ITB accesses +system.cpu.dtb.read_hits 9957395 # DTB read hits +system.cpu.dtb.read_misses 44300 # DTB read misses +system.cpu.dtb.read_acv 564 # DTB read access violations +system.cpu.dtb.read_accesses 948872 # DTB read accesses +system.cpu.dtb.write_hits 6634412 # DTB write hits +system.cpu.dtb.write_misses 10394 # DTB write misses +system.cpu.dtb.write_acv 384 # DTB write access violations +system.cpu.dtb.write_accesses 338929 # DTB write accesses +system.cpu.dtb.data_hits 16591807 # DTB hits +system.cpu.dtb.data_misses 54694 # DTB misses +system.cpu.dtb.data_acv 948 # DTB access violations +system.cpu.dtb.data_accesses 1287801 # DTB accesses +system.cpu.itb.fetch_hits 1332166 # ITB hits +system.cpu.itb.fetch_misses 40283 # ITB misses +system.cpu.itb.fetch_acv 1114 # ITB acv +system.cpu.itb.fetch_accesses 1372449 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,147 +354,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 115937106 # number of cpu cycles simulated +system.cpu.numCycles 114963877 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits +system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued @@ -529,116 +517,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued -system.cpu.iq.rate 0.495930 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued +system.cpu.iq.rate 0.497364 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3587167 # number of nop insts executed -system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed -system.cpu.iew.exec_branches 9006504 # Number of branches executed -system.cpu.iew.exec_stores 6665235 # Number of stores executed -system.cpu.iew.exec_rate 0.490534 # Inst execution rate -system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27888094 # num instructions producing a value -system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value +system.cpu.iew.exec_nop 3561304 # number of nop insts executed +system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed +system.cpu.iew.exec_branches 8986521 # Number of branches executed +system.cpu.iew.exec_stores 6660022 # Number of stores executed +system.cpu.iew.exec_rate 0.492808 # Inst execution rate +system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27828941 # num instructions producing a value +system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back +system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56284358 # Number of instructions committed -system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56255888 # Number of instructions committed +system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15505080 # Number of memory references committed -system.cpu.commit.loads 9112848 # Number of loads committed -system.cpu.commit.membars 227858 # Number of memory barriers committed -system.cpu.commit.branches 8462387 # Number of branches committed +system.cpu.commit.refs 15498262 # Number of memory references committed +system.cpu.commit.loads 9108436 # Number of loads committed +system.cpu.commit.membars 227920 # Number of memory barriers committed +system.cpu.commit.branches 8459857 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. -system.cpu.commit.function_calls 744427 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. +system.cpu.commit.function_calls 744157 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142888950 # The number of ROB reads -system.cpu.rob.rob_writes 130907900 # The number of ROB writes -system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53089851 # Number of Instructions Simulated -system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated -system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74514493 # number of integer regfile reads -system.cpu.int_regfile_writes 40703979 # number of integer regfile writes -system.cpu.fp_regfile_reads 166152 # number of floating regfile reads -system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads -system.cpu.misc_regfile_writes 949957 # number of misc regfile writes +system.cpu.rob.rob_reads 141652037 # The number of ROB reads +system.cpu.rob.rob_writes 129738562 # The number of ROB writes +system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53062487 # Number of Instructions Simulated +system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated +system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads +system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74266984 # number of integer regfile reads +system.cpu.int_regfile_writes 40553865 # number of integer regfile writes +system.cpu.fp_regfile_reads 166054 # number of floating regfile reads +system.cpu.fp_regfile_writes 167450 # number of floating regfile writes +system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads +system.cpu.misc_regfile_writes 950331 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -670,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1025621 # number of replacements -system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use -system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits -system.cpu.icache.overall_hits::total 7915590 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1086093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1086093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1086093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1086093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1086093 # number of overall misses -system.cpu.icache.overall_misses::total 1086093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16268467995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16268467995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16268467995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16268467995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16268467995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16268467995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked +system.cpu.icache.replacements 1020915 # number of replacements +system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use +system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits +system.cpu.icache.overall_hits::total 7681838 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses +system.cpu.icache.overall_misses::total 1079605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 238 # number of writebacks -system.cpu.icache.writebacks::total 238 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 236 # number of writebacks +system.cpu.icache.writebacks::total 236 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57973 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57973 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57973 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57973 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021632 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1021632 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402627 # number of replacements -system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use -system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1401226 # number of replacements +system.cpu.dcache.tagsinuse 511.995976 # Cycle average of tags in use +system.cpu.dcache.total_refs 11915698 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401738 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.500660 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19319000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995976 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits -system.cpu.dcache.overall_hits::total 11537532 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses -system.cpu.dcache.overall_misses::total 3747076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 83500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97015665026 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97015665026 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97015665026 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97015665026 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9127640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9127640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156968 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156968 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 216878 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 216878 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 220105 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220105 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15284608 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15284608 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.197665 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315555 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000014 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245154 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245154 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21564.412465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29908.900809 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14827.843607 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27833.333333 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25891.032108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25891.032108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7290659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7290659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4213930 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4213930 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190794 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190794 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220142 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11504589 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11504589 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11504589 # number of overall hits +system.cpu.dcache.overall_hits::total 11504589 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1799381 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1799381 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1940587 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1940587 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23075 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23075 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3739968 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3739968 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3739968 # number of overall misses +system.cpu.dcache.overall_misses::total 3739968 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37711411500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37711411500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57880522429 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57880522429 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 335593000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 335593000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 14000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 14000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95591933929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95591933929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95591933929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95591933929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9090040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9090040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6154517 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154517 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213869 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 213869 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220143 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220143 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15244557 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15244557 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15244557 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15244557 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197951 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.197951 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315311 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315311 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107893 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107893 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 805076325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99334 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834483 # number of writebacks -system.cpu.dcache.writebacks::total 834483 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718769 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 718769 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643008 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643008 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5385 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5385 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2361777 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2361777 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2361777 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2361777 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085447 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1085447 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299852 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299852 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17992 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17992 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1385299 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1385299 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1385299 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1385299 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24777383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24777383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8529644820 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8529644820 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212567500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212567500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 74000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 74000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307028320 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33307028320 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33307028320 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33307028320 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904080500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904080500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1233731998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048701 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082959 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000014 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090634 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090634 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22826.893897 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28446.182850 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11814.556470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks +system.cpu.dcache.writebacks::total 840933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2356015 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2356015 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2356015 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083984 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083984 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299969 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299969 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17930 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17930 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383953 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383953 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383953 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383953 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24067895500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24067895500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8474806325 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8474806325 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206484500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206484500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -919,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -979,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192407 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 192549 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 5d60c7bc8..ea1e9a4d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index e36bf2017..570320fa8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,17 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8 -warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013 +warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented +warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 086d512f2..494cdd6ff 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:58:44 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:32:52 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2501685689500 because m5_exit instruction encountered +Exiting @ tick 2500827052500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e9f646cad..655a3d26b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.501686 # Number of seconds simulated -sim_ticks 2501685689500 # Number of ticks simulated -final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.500827 # Number of seconds simulated +sim_ticks 2500827052500 # Number of ticks simulated +final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49441 # Simulator instruction rate (inst/s) -host_op_rate 63837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075989543 # Simulator tick rate (ticks/s) -host_mem_usage 387400 # Number of bytes of host memory used -host_seconds 1205.06 # Real time elapsed on the host -sim_insts 59579009 # Number of instructions simulated -sim_ops 76926775 # Number of ops (including micro ops) simulated +host_inst_rate 76093 # Simulator instruction rate (inst/s) +host_op_rate 98249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3194009596 # Simulator tick rate (ticks/s) +host_mem_usage 386968 # Number of bytes of host memory used +host_seconds 782.97 # Real time elapsed on the host +sim_insts 59579144 # Number of instructions simulated +sim_ops 76926734 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +23,191 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory -system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory +system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119797 # number of replacements -system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use -system.l2c.total_refs 1834134 # Total number of references to valid blocks. -system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits -system.l2c.Writeback_hits::total 635023 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits -system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits -system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits -system.l2c.overall_hits::cpu.data 484171 # number of overall hits -system.l2c.overall_hits::total 1642008 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64425 # number of replacements +system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use +system.l2c.total_refs 2029411 # Total number of references to valid blocks. +system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits +system.l2c.Writeback_hits::total 675876 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits +system.l2c.overall_hits::cpu.inst 977061 # number of overall hits +system.l2c.overall_hits::cpu.data 497363 # number of overall hits +system.l2c.overall_hits::total 1608896 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses -system.l2c.demand_misses::total 177053 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu.inst 17378 # number of overall misses -system.l2c.overall_misses::cpu.data 159472 # number of overall misses -system.l2c.overall_misses::total 177053 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency +system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses +system.l2c.demand_misses::total 156375 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu.inst 12370 # number of overall misses +system.l2c.overall_misses::cpu.data 143952 # number of overall misses +system.l2c.overall_misses::total 156375 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,112 +216,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102651 # number of writebacks -system.l2c.writebacks::total 102651 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 19094 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 59134 # number of writebacks +system.l2c.writebacks::total 59134 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176952 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 188 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176952 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 7532000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1471125000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -339,26 +336,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048343 # DTB read hits -system.cpu.checker.dtb.read_misses 7305 # DTB read misses -system.cpu.checker.dtb.write_hits 11293933 # DTB write hits +system.cpu.checker.dtb.read_hits 15048239 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11293838 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15055547 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296029 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26342276 # DTB hits -system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26351772 # DTB accesses -system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits +system.cpu.checker.dtb.hits 26342077 # DTB hits +system.cpu.checker.dtb.misses 9499 # DTB misses +system.cpu.checker.dtb.accesses 26351576 # DTB accesses +system.cpu.checker.itb.inst_hits 60745761 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -375,36 +372,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses -system.cpu.checker.itb.hits 60745631 # DTB hits +system.cpu.checker.itb.inst_accesses 60750232 # ITB inst accesses +system.cpu.checker.itb.hits 60745761 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60750102 # DTB accesses -system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60750232 # DTB accesses +system.cpu.checker.numCycles 77205158 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52103903 # DTB read hits -system.cpu.dtb.read_misses 93079 # DTB read misses -system.cpu.dtb.write_hits 11946241 # DTB write hits -system.cpu.dtb.write_misses 25022 # DTB write misses +system.cpu.dtb.read_hits 51785537 # DTB read hits +system.cpu.dtb.read_misses 81591 # DTB read misses +system.cpu.dtb.write_hits 11872923 # DTB write hits +system.cpu.dtb.write_misses 18231 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52196982 # DTB read accesses -system.cpu.dtb.write_accesses 11971263 # DTB write accesses +system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51867128 # DTB read accesses +system.cpu.dtb.write_accesses 11891154 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64050144 # DTB hits -system.cpu.dtb.misses 118101 # DTB misses -system.cpu.dtb.accesses 64168245 # DTB accesses -system.cpu.itb.inst_hits 13717584 # ITB inst hits -system.cpu.itb.inst_misses 12272 # ITB inst misses +system.cpu.dtb.hits 63658460 # DTB hits +system.cpu.dtb.misses 99822 # DTB misses +system.cpu.dtb.accesses 63758282 # DTB accesses +system.cpu.itb.inst_hits 13022422 # ITB inst hits +system.cpu.itb.inst_misses 12153 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -413,542 +410,542 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5249 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13729856 # ITB inst accesses -system.cpu.itb.hits 13717584 # DTB hits -system.cpu.itb.misses 12272 # DTB misses -system.cpu.itb.accesses 13729856 # DTB accesses -system.cpu.numCycles 411352060 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13034575 # ITB inst accesses +system.cpu.itb.hits 13022422 # DTB hits +system.cpu.itb.misses 12153 # DTB misses +system.cpu.itb.accesses 13034575 # DTB accesses +system.cpu.numCycles 408047924 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits +system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued -system.cpu.iq.rate 0.307159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued +system.cpu.iq.rate 0.305615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 261908 # number of nop insts executed -system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed -system.cpu.iew.exec_branches 11601340 # Number of branches executed -system.cpu.iew.exec_stores 12455688 # Number of stores executed -system.cpu.iew.exec_rate 0.299278 # Inst execution rate -system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47546734 # num instructions producing a value -system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value +system.cpu.iew.exec_nop 254480 # number of nop insts executed +system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed +system.cpu.iew.exec_branches 11392260 # Number of branches executed +system.cpu.iew.exec_stores 12383469 # Number of stores executed +system.cpu.iew.exec_rate 0.298278 # Inst execution rate +system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46962413 # num instructions producing a value +system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729390 # Number of instructions committed -system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59729525 # Number of instructions committed +system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513639 # Number of memory references committed -system.cpu.commit.loads 15715354 # Number of loads committed -system.cpu.commit.membars 413068 # Number of memory barriers committed -system.cpu.commit.branches 9904424 # Number of branches committed +system.cpu.commit.refs 27513492 # Number of memory references committed +system.cpu.commit.loads 15715290 # Number of loads committed +system.cpu.commit.membars 413064 # Number of memory barriers committed +system.cpu.commit.branches 9904425 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617835 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. +system.cpu.commit.function_calls 995959 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 245922084 # The number of ROB reads -system.cpu.rob.rob_writes 212744706 # The number of ROB writes -system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579009 # Number of Instructions Simulated -system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated -system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558200785 # number of integer regfile reads -system.cpu.int_regfile_writes 89400907 # number of integer regfile writes -system.cpu.fp_regfile_reads 8900 # number of floating regfile reads -system.cpu.fp_regfile_writes 2982 # number of floating regfile writes -system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads -system.cpu.misc_regfile_writes 912729 # number of misc regfile writes -system.cpu.icache.replacements 1019271 # number of replacements -system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use -system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits -system.cpu.icache.overall_hits::total 12598089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses -system.cpu.icache.overall_misses::total 1111711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked +system.cpu.rob.rob_reads 240802540 # The number of ROB reads +system.cpu.rob.rob_writes 206662154 # The number of ROB writes +system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59579144 # Number of Instructions Simulated +system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated +system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 552215112 # number of integer regfile reads +system.cpu.int_regfile_writes 88113132 # number of integer regfile writes +system.cpu.fp_regfile_reads 8314 # number of floating regfile reads +system.cpu.fp_regfile_writes 2878 # number of floating regfile writes +system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads +system.cpu.misc_regfile_writes 912736 # number of misc regfile writes +system.cpu.icache.replacements 990445 # number of replacements +system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use +system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits +system.cpu.icache.overall_hits::total 11943122 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses +system.cpu.icache.overall_misses::total 1075156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 60091 # number of writebacks -system.cpu.icache.writebacks::total 60091 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67776 # number of writebacks +system.cpu.icache.writebacks::total 67776 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645895 # number of replacements -system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use -system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor +system.cpu.dcache.replacements 644124 # number of replacements +system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use +system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits -system.cpu.dcache.overall_hits::total 21500114 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses -system.cpu.dcache.overall_misses::total 3714520 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits +system.cpu.dcache.overall_hits::total 21203803 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses +system.cpu.dcache.overall_misses::total 3698116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks -system.cpu.dcache.writebacks::total 574932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks +system.cpu.dcache.writebacks::total 608100 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -970,16 +967,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index aff8253f7..8259e7988 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..c3484784a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,9 +10,11 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index c0177ee1d..02c5cc88a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:58:50 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:33:16 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2570833934500 because m5_exit instruction encountered +Exiting @ tick 2569716290500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6e759f59e..038e4aa5b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.570834 # Number of seconds simulated -sim_ticks 2570833934500 # Number of ticks simulated -final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.569716 # Number of seconds simulated +sim_ticks 2569716290500 # Number of ticks simulated +final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53678 # Simulator instruction rate (inst/s) -host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2225327298 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 1155.26 # Real time elapsed on the host -sim_insts 62012062 # Number of instructions simulated -sim_ops 80088895 # Number of ops (including micro ops) simulated +host_inst_rate 91215 # Simulator instruction rate (inst/s) +host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3779331614 # Simulator tick rate (ticks/s) +host_mem_usage 391064 # Number of bytes of host memory used +host_seconds 679.94 # Real time elapsed on the host +sim_insts 62020337 # Number of instructions simulated +sim_ops 80105642 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory +system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -80,259 +80,259 @@ system.realview.nvmem.num_reads::cpu0.inst 1 # system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130926 # number of replacements -system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use -system.l2c.total_refs 1855308 # Total number of references to valid blocks. -system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. +system.l2c.replacements 72902 # number of replacements +system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use +system.l2c.total_refs 2024041 # Total number of references to valid blocks. +system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.006762 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2177.920948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1032.752170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 22.717912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.014158 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4068.026765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5070.431306 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231738 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000269 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.033232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.015759 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000347 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.062073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.077369 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420786 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 51294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 335682 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 133493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 112013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 702787 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 231603 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1579905 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606768 # number of Writeback hits -system.l2c.Writeback_hits::total 606768 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 925 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2064 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 217 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 388 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 605 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 35350 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 66066 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101416 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 51294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 335682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 168843 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 112013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 702787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 297669 # number of demand (read+write) hits -system.l2c.demand_hits::total 1681321 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 51294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits -system.l2c.overall_hits::cpu0.inst 335682 # number of overall hits -system.l2c.overall_hits::cpu0.data 168843 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 112013 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7283 # number of overall hits -system.l2c.overall_hits::cpu1.inst 702787 # number of overall hits -system.l2c.overall_hits::cpu1.data 297669 # number of overall hits -system.l2c.overall_hits::total 1681321 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 84 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8376 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8805 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 61 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 10197 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 12824 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40353 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5201 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11020 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 788 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 600 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1388 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65908 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 81633 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 84 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8376 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74713 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 61 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10197 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 94457 # number of demand (read+write) misses -system.l2c.demand_misses::total 187894 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 84 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8376 # number of overall misses -system.l2c.overall_misses::cpu0.data 74713 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 61 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10197 # number of overall misses -system.l2c.overall_misses::cpu1.data 94457 # number of overall misses -system.l2c.overall_misses::total 187894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4383500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 438009000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 459487500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3183500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 533470500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 669975500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2108822500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 18089500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 38874000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 56963500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2245500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5381000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7626500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3455909999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4284020000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7739929999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 4383500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 261000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 438009000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3915397499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 3183500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 533470500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4953995500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9848752499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 4383500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 261000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 438009000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3915397499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 3183500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 533470500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4953995500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9848752499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 51378 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5755 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 344058 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 142298 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 112074 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7284 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 712984 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 244427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1620258 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 606768 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 606768 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6126 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 6958 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13084 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1005 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 988 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1993 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 101258 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 147699 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248957 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 51378 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5755 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 344058 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 243556 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 112074 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7284 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 712984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 392126 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1869215 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 51378 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5755 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 344058 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 243556 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 112074 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7284 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 712984 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 392126 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1869215 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000869 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.024345 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.061877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.306759 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.306759 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.838160 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average ReadReq miss latency +system.l2c.occ_percent::cpu0.inst 0.064291 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045313 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000186 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061467 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062955 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.807414 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 50859 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5940 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 395141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 161674 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 79156 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 619717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 202375 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1521452 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 646021 # number of Writeback hits +system.l2c.Writeback_hits::total 646021 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 861 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1085 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1946 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 373 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 50919 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55813 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106732 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 50859 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5940 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 395141 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212593 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 79156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 619717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 258188 # number of demand (read+write) hits +system.l2c.demand_hits::total 1628184 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 50859 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5940 # number of overall hits +system.l2c.overall_hits::cpu0.inst 395141 # number of overall hits +system.l2c.overall_hits::cpu0.data 212593 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 79156 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6590 # number of overall hits +system.l2c.overall_hits::cpu1.inst 619717 # number of overall hits +system.l2c.overall_hits::cpu1.data 258188 # number of overall hits +system.l2c.overall_hits::total 1628184 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5853 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6139 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6809 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6537 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25366 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5294 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4767 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10061 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 775 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 577 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1352 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 62637 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77700 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140337 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5853 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 68776 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6809 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 84237 # number of demand (read+write) misses +system.l2c.demand_misses::total 165703 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5853 # number of overall misses +system.l2c.overall_misses::cpu0.data 68776 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6809 # number of overall misses +system.l2c.overall_misses::cpu1.data 84237 # number of overall misses +system.l2c.overall_misses::total 165703 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 521500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 53000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 306091000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 320158000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 783000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 104000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 356464000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 341134500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1325309000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 18664500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 31259000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 49923500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1307000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6272500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7579500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3285106999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4081053500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7366160499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 521500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 53000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 306091000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3605264999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 783000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 104000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 356464000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4422188000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8691469499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 521500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 53000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 306091000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3605264999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 783000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 104000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 356464000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4422188000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8691469499 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 50869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5941 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 400994 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 167813 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 79171 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6592 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 626526 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 208912 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1546818 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 646021 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 646021 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6155 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5852 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12007 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 741 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1725 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 113556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 133513 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247069 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 50869 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5941 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 400994 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 281369 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 79171 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6592 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 626526 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 342425 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1793887 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 50869 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5941 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 400994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 281369 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 79171 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6592 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 626526 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 342425 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1793887 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014596 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036582 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000303 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010868 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.031291 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016399 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860114 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814593 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837928 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.778677 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.783768 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.551596 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.581966 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568007 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000168 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244433 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000303 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010868 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.246001 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.092371 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000168 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244433 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000303 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010868 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.246001 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.092371 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 53000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52296.429182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52151.490471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52200 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52351.887208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52185.176687 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52247.457226 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3525.595013 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6557.373610 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4962.081304 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1686.451613 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10870.883882 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5606.139053 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52446.748711 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52523.211068 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52489.083413 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52452.095007 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52452.095007 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,180 +341,180 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 111665 # number of writebacks -system.l2c.writebacks::total 111665 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 47 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 34 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 47 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 47 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 96 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 84 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 8373 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8758 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 61 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 10185 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 12790 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 40257 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5201 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5819 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11020 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 788 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 600 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1388 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 65908 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 81633 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 147541 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 84 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8373 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74666 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 61 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10185 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 94423 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 187798 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 84 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8373 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74666 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 61 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10185 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 94423 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 187798 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3364000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 335581500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 350822000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2444000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 408650000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 512397000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1613499500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 208363000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 232936000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 441299000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31554000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 24037000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 55591000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2638527499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3273235000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5911762499 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3364000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 335581500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2989349499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2444000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 408650000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3785632000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7525261999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3364000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 335581500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2989349499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2444000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 408650000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3785632000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7525261999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5668500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8235934000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123713083500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131956617000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 706976980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31815648332 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32522625312 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5668500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8942910980 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155528731832 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164479242312 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061547 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average ReadReq mshr miss latency +system.l2c.writebacks::writebacks 66834 # number of writebacks +system.l2c.writebacks::total 66834 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5849 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6101 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6803 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6512 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25293 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5294 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4767 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10061 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 775 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 577 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1352 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 62637 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77700 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140337 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5849 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 68738 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6803 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 84212 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165630 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5849 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 68738 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6803 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 84212 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165630 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 41000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 234434500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 244221500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 601000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 273121500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 260689500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1013589000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211949500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190864500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 402814000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31033000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23118500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 54151500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2507451999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3115007000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5622458999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 41000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 234434500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2751673499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 601000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 273121500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3375696500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6636047999 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 41000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 234434500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2751673499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 601000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 273121500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3375696500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6636047999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5501500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 21616744000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2009500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 713445484 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31812115712 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32525561196 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5501500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 22330189484 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2009500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164486076196 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036356 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016352 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.860114 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.837928 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.778677 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783768 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551596 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581966 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568007 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.092330 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.092330 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7530160 # DTB read hits -system.cpu0.dtb.read_misses 32787 # DTB read misses -system.cpu0.dtb.write_hits 4446652 # DTB write hits -system.cpu0.dtb.write_misses 6213 # DTB write misses +system.cpu0.dtb.read_hits 12222008 # DTB read hits +system.cpu0.dtb.read_misses 34799 # DTB read misses +system.cpu0.dtb.write_hits 5155654 # DTB write hits +system.cpu0.dtb.write_misses 4970 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2035 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4401 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 226 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7562947 # DTB read accesses -system.cpu0.dtb.write_accesses 4452865 # DTB write accesses +system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12256807 # DTB read accesses +system.cpu0.dtb.write_accesses 5160624 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11976812 # DTB hits -system.cpu0.dtb.misses 39000 # DTB misses -system.cpu0.dtb.accesses 12015812 # DTB accesses -system.cpu0.itb.inst_hits 3834120 # ITB inst hits -system.cpu0.itb.inst_misses 4594 # ITB inst misses +system.cpu0.dtb.hits 17377662 # DTB hits +system.cpu0.dtb.misses 39769 # DTB misses +system.cpu0.dtb.accesses 17417431 # DTB accesses +system.cpu0.itb.inst_hits 4312814 # ITB inst hits +system.cpu0.itb.inst_misses 5659 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,542 +566,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1800 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 3838714 # ITB inst accesses -system.cpu0.itb.hits 3834120 # DTB hits -system.cpu0.itb.misses 4594 # DTB misses -system.cpu0.itb.accesses 3838714 # DTB accesses -system.cpu0.numCycles 55537360 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses +system.cpu0.itb.hits 4312814 # DTB hits +system.cpu0.itb.misses 5659 # DTB misses +system.cpu0.itb.accesses 4318473 # DTB accesses +system.cpu0.numCycles 91755333 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5204671 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 3944570 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 296840 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3413720 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2557176 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 459948 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 62294 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 10542481 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 27454720 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5204671 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3017124 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6462624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1388283 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64249 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 17511747 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6585 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 32170 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 74952 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 3831976 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 163321 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.003010 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.394306 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 29226357 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 522599 1.46% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 706764 1.98% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 578503 1.62% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 534782 1.50% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 477839 1.34% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 574033 1.61% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 347894 0.97% 92.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2713823 7.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093715 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.494347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 10901751 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17564449 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 5807943 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 476099 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 932352 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 836954 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 56324 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34505102 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 181228 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 932352 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11416627 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4596309 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11321409 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 5748941 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1666956 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33335658 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 999 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 358087 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 883877 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 110 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 33439844 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 151572898 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 151532196 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 25794881 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7644963 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 390853 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 354451 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4284069 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6465672 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4994701 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 841470 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 890235 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 31482040 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 658671 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 31606585 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 78774 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5676384 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13082280 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 117406 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 35682594 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.885770 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514582 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 22866556 64.08% 64.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4972769 13.94% 78.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2602679 7.29% 85.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 1960706 5.49% 90.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1807368 5.07% 95.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 768762 2.15% 98.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 499053 1.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 158868 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 45833 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 35682594 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26479 2.83% 2.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.05% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 724595 77.49% 80.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 183504 19.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 18849345 59.64% 59.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42325 0.13% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7946092 25.14% 84.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4753870 15.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 31606585 # Type of FU issued -system.cpu0.iq.rate 0.569105 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 935032 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029583 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 99937037 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 37821084 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 28987180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10596 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5532 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4395 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 32521589 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5747 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 248744 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued +system.cpu0.iq.rate 0.437871 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1245744 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3732 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10021 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 530307 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1901421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5034 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 932352 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3503280 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 78441 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 32200235 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 121893 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6465672 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4994701 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 398658 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37609 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4704 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10021 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 177778 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116282 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 294060 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 31219910 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7794602 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386675 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 59524 # number of nop insts executed -system.cpu0.iew.exec_refs 12495671 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4074655 # Number of branches executed -system.cpu0.iew.exec_stores 4701069 # Number of stores executed -system.cpu0.iew.exec_rate 0.562142 # Inst execution rate -system.cpu0.iew.wb_sent 31018630 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 28991575 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15563441 # num instructions producing a value -system.cpu0.iew.wb_consumers 30561631 # num instructions consuming a value +system.cpu0.iew.exec_nop 116326 # number of nop insts executed +system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4780864 # Number of branches executed +system.cpu0.iew.exec_stores 5426948 # Number of stores executed +system.cpu0.iew.exec_rate 0.433525 # Inst execution rate +system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18213937 # num instructions producing a value +system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.522019 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.509248 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 19778635 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 26259365 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5789320 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541265 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 257580 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 34779040 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.755034 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.721723 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 24914736 71.64% 71.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 4928764 14.17% 85.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1604217 4.61% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 793137 2.28% 92.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 618967 1.78% 94.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 369015 1.06% 95.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397376 1.14% 96.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 185067 0.53% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 967761 2.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 34779040 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 19778635 # Number of instructions committed -system.cpu0.commit.committedOps 26259365 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23601687 # Number of instructions committed +system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 9684322 # Number of memory references committed -system.cpu0.commit.loads 5219928 # Number of loads committed -system.cpu0.commit.membars 194188 # Number of memory barriers committed -system.cpu0.commit.branches 3591028 # Number of branches committed -system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 23338580 # Number of committed integer instructions. -system.cpu0.commit.function_calls 422336 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 967761 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11516347 # Number of memory references committed +system.cpu0.commit.loads 6366744 # Number of loads committed +system.cpu0.commit.membars 228774 # Number of memory barriers committed +system.cpu0.commit.branches 4268909 # Number of branches committed +system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 492618 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 65245448 # The number of ROB reads -system.cpu0.rob.rob_writes 65031517 # The number of ROB writes -system.cpu0.timesIdled 363170 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 19854766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085481268 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 19754081 # Number of Instructions Simulated -system.cpu0.committedOps 26234811 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 19754081 # Number of Instructions Simulated -system.cpu0.cpi 2.811437 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.811437 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.355690 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.355690 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 145547438 # number of integer regfile reads -system.cpu0.int_regfile_writes 28450023 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4554 # number of floating regfile reads -system.cpu0.fp_regfile_writes 434 # number of floating regfile writes -system.cpu0.misc_regfile_reads 38991088 # number of misc regfile reads -system.cpu0.misc_regfile_writes 443778 # number of misc regfile writes -system.cpu0.icache.replacements 345092 # number of replacements -system.cpu0.icache.tagsinuse 511.631515 # Cycle average of tags in use -system.cpu0.icache.total_refs 3456613 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 345604 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.001658 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6336390000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.631515 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3456613 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3456613 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3456613 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3456613 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3456613 # number of overall hits -system.cpu0.icache.overall_hits::total 3456613 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 375216 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 375216 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 375216 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 375216 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 375216 # number of overall misses -system.cpu0.icache.overall_misses::total 375216 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5700257984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked +system.cpu0.rob.rob_reads 80832744 # The number of ROB reads +system.cpu0.rob.rob_writes 75665562 # The number of ROB writes +system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23536584 # Number of Instructions Simulated +system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated +system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads +system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads +system.cpu0.fp_regfile_writes 934 # number of floating regfile writes +system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads +system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes +system.cpu0.icache.replacements 402234 # number of replacements +system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use +system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits +system.cpu0.icache.overall_hits::total 3875529 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses +system.cpu0.icache.overall_misses::total 435289 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 19422 # number of writebacks -system.cpu0.icache.writebacks::total 19422 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29600 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 29600 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 29600 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 29600 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 345616 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 345616 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 345616 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 345616 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks +system.cpu0.icache.writebacks::total 31582 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 232498 # number of replacements -system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use -system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4805960 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4805960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2599019 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2599019 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154744 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 154744 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152410 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 152410 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7404979 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7404979 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7404979 # number of overall hits -system.cpu0.dcache.overall_hits::total 7404979 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 332693 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 332693 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1446995 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1446995 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8853 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8853 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7938 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7938 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1779688 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1779688 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1779688 # number of overall misses -system.cpu0.dcache.overall_misses::total 1779688 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 64309791899 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 64309791899 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 272390 # number of replacements +system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits +system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses +system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 208397 # number of writebacks -system.cpu0.dcache.writebacks::total 208397 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1502667 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1502667 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 277021 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277021 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks +system.cpu0.dcache.writebacks::total 253456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1111,27 +1111,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 45335988 # DTB read hits -system.cpu1.dtb.read_misses 67766 # DTB read misses -system.cpu1.dtb.write_hits 7974825 # DTB write hits -system.cpu1.dtb.write_misses 20571 # DTB write misses +system.cpu1.dtb.read_hits 40314372 # DTB read hits +system.cpu1.dtb.read_misses 47835 # DTB read misses +system.cpu1.dtb.write_hits 7207214 # DTB write hits +system.cpu1.dtb.write_misses 14308 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2707 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7654 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 597 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1825 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45403754 # DTB read accesses -system.cpu1.dtb.write_accesses 7995396 # DTB write accesses +system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 40362207 # DTB read accesses +system.cpu1.dtb.write_accesses 7221522 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 53310813 # DTB hits -system.cpu1.dtb.misses 88337 # DTB misses -system.cpu1.dtb.accesses 53399150 # DTB accesses -system.cpu1.itb.inst_hits 10447082 # ITB inst hits -system.cpu1.itb.inst_misses 7775 # ITB inst misses +system.cpu1.dtb.hits 47521586 # DTB hits +system.cpu1.dtb.misses 62143 # DTB misses +system.cpu1.dtb.accesses 47583729 # DTB accesses +system.cpu1.itb.inst_hits 9199147 # ITB inst hits +system.cpu1.itb.inst_misses 6537 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1140,546 +1140,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1562 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 5028 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10454857 # ITB inst accesses -system.cpu1.itb.hits 10447082 # DTB hits -system.cpu1.itb.misses 7775 # DTB misses -system.cpu1.itb.accesses 10454857 # DTB accesses -system.cpu1.numCycles 361402922 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses +system.cpu1.itb.hits 9199147 # DTB hits +system.cpu1.itb.misses 6537 # DTB misses +system.cpu1.itb.accesses 9205684 # DTB accesses +system.cpu1.numCycles 321589455 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 11186826 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8978228 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 659649 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7702930 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6115228 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 914050 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 143881 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 24238168 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 79362685 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 11186826 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7029278 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 17037334 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5514806 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 104106 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 74528918 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 113982 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 165536 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10441784 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 854309 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4213 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.807329 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.185858 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102950411 85.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 1027065 0.86% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1252290 1.04% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2222542 1.85% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1450508 1.21% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 763655 0.64% 91.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2450140 2.04% 93.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 546027 0.46% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7314832 6.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030954 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.219596 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25932861 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 74439661 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15341871 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 600655 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3662422 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1558576 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 123600 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90136794 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 402223 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3662422 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 27545183 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32824542 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 37049772 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14316379 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4579172 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 83629464 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2956 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 679775 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3317472 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46248 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 88354418 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 386338466 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 386288470 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 49996 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 54988347 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 33366070 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 602019 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 524737 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8626692 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 16066963 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9656417 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1282659 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1811239 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 75062782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1031692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 98462898 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 155624 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 21632122 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 61142717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 223849 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 119977470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.820678 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.544702 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 85994383 71.68% 71.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9640016 8.03% 79.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5133014 4.28% 83.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4263453 3.55% 87.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11149849 9.29% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2119505 1.77% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1269612 1.06% 99.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 309202 0.26% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 98436 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 119977470 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 44202 0.54% 0.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 979 0.01% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7732056 95.26% 95.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 339451 4.18% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 43271411 43.95% 44.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 69911 0.07% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 29 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 39 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1782 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46626317 47.35% 91.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8400570 8.53% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 98462898 # Type of FU issued -system.cpu1.iq.rate 0.272446 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8116688 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.082434 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 325251459 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 97743765 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 61686980 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12182 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6832 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5554 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 106480420 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6347 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 431690 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued +system.cpu1.iq.rate 0.274443 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4883583 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7497 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24780 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1835710 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32214526 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149867 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3662422 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25277331 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367624 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 76304263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 229674 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 16066963 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9656417 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 636963 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63488 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8504 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24780 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 400468 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 244624 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 645092 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 95561838 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45782046 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2901060 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 209789 # number of nop insts executed -system.cpu1.iew.exec_refs 54078244 # number of memory reference insts executed -system.cpu1.iew.exec_branches 8068913 # Number of branches executed -system.cpu1.iew.exec_stores 8296198 # Number of stores executed -system.cpu1.iew.exec_rate 0.264419 # Inst execution rate -system.cpu1.iew.wb_sent 94191755 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 61692534 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 33977338 # num instructions producing a value -system.cpu1.iew.wb_consumers 61891561 # num instructions consuming a value +system.cpu1.iew.exec_nop 145081 # number of nop insts executed +system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7143156 # Number of branches executed +system.cpu1.iew.exec_stores 7512980 # Number of stores executed +system.cpu1.iew.exec_rate 0.266206 # Inst execution rate +system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30755357 # num instructions producing a value +system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.170703 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.548982 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 42383808 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 53979911 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 22261112 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 807843 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 569017 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 116371049 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.463860 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.434767 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97273421 83.59% 83.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9394437 8.07% 91.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2575050 2.21% 93.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1580988 1.36% 95.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1207821 1.04% 96.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 698590 0.60% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1120414 0.96% 97.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 516932 0.44% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 2003396 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 116371049 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 42383808 # Number of instructions committed -system.cpu1.commit.committedOps 53979911 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38569031 # Number of instructions committed +system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 19004087 # Number of memory references committed -system.cpu1.commit.loads 11183380 # Number of loads committed -system.cpu1.commit.membars 242516 # Number of memory barriers committed -system.cpu1.commit.branches 6784179 # Number of branches committed -system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 48067133 # Number of committed integer instructions. -system.cpu1.commit.function_calls 633379 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 2003396 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17180057 # Number of memory references committed +system.cpu1.commit.loads 10040109 # Number of loads committed +system.cpu1.commit.membars 207982 # Number of memory barriers committed +system.cpu1.commit.branches 6108113 # Number of branches committed +system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. +system.cpu1.commit.function_calls 563417 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 189385035 # The number of ROB reads -system.cpu1.rob.rob_writes 156267900 # The number of ROB writes -system.cpu1.timesIdled 1564769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 241425452 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4780203327 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 42257981 # Number of Instructions Simulated -system.cpu1.committedOps 53854084 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 42257981 # Number of Instructions Simulated -system.cpu1.cpi 8.552300 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.552300 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.116928 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.116928 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 430079753 # number of integer regfile reads -system.cpu1.int_regfile_writes 64515100 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4419 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2066 # number of floating regfile writes -system.cpu1.misc_regfile_reads 102262967 # number of misc regfile reads -system.cpu1.misc_regfile_writes 513108 # number of misc regfile writes -system.cpu1.icache.replacements 714529 # number of replacements -system.cpu1.icache.tagsinuse 498.761723 # Cycle average of tags in use -system.cpu1.icache.total_refs 9665211 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 715041 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.517003 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74296656000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.761723 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9665211 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9665211 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9665211 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9665211 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9665211 # number of overall hits -system.cpu1.icache.overall_hits::total 9665211 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 776521 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 776521 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 776521 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 776521 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 776521 # number of overall misses -system.cpu1.icache.overall_misses::total 776521 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11390030990 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked +system.cpu1.rob.rob_reads 168322862 # The number of ROB reads +system.cpu1.rob.rob_writes 139443210 # The number of ROB writes +system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38483753 # Number of Instructions Simulated +system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated +system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads +system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads +system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes +system.cpu1.icache.replacements 628575 # number of replacements +system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use +system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits +system.cpu1.icache.overall_hits::total 8518604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses +system.cpu1.icache.overall_misses::total 678443 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9197047 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073767 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073767 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073767 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073767 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073767 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073767 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14539.985672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 32858 # number of writebacks -system.cpu1.icache.writebacks::total 32858 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 61445 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 61445 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 61445 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 61445 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 61445 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 61445 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 715076 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 715076 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 715076 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 715076 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 715076 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 715076 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8506439492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8506439492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8506439492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8506439492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8506439492 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8506439492 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 30976 # number of writebacks +system.cpu1.icache.writebacks::total 30976 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49327 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49327 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49327 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49327 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49327 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49327 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 629116 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 629116 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 629116 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 629116 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 629116 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 629116 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7390302499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7390302499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7390302499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7390302499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7390302499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7390302499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2676000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2676000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2676000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2676000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068404 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068404 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068404 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 417022 # number of replacements -system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use -system.cpu1.dcache.total_refs 15242379 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 417534 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.505719 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 72565634000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 464.475329 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.907178 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.907178 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 10057492 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10057492 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4888994 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4888994 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 126446 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 126446 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 120021 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 120021 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 14946486 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 14946486 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 14946486 # number of overall hits -system.cpu1.dcache.overall_hits::total 14946486 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 473003 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 473003 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1726377 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1726377 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14767 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14767 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10580 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10580 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2199380 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2199380 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2199380 # number of overall misses -system.cpu1.dcache.overall_misses::total 2199380 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7143574500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7143574500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57173185397 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 57173185397 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 177446500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 177446500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91928500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 91928500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 64316759897 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 64316759897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 64316759897 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 64316759897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10530495 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10530495 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6615371 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6615371 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141213 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 365990 # number of replacements +system.cpu1.dcache.tagsinuse 486.374853 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 106581 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102282 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102282 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13180633 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13180633 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13180633 # number of overall hits +system.cpu1.dcache.overall_hits::total 13180633 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 408153 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 408153 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1582783 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1582783 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13916 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13916 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10800 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10800 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1990936 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1990936 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1990936 # number of overall misses +system.cpu1.dcache.overall_misses::total 1990936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5766799000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5766799000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 55285236443 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 55285236443 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 141367500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 141367500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 89573500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 89573500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 61052035443 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 61052035443 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 61052035443 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 61052035443 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9203658 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9203658 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5967911 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5967911 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120497 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 346093 # number of writebacks -system.cpu1.dcache.writebacks::total 346093 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1751452 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1751452 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 447928 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 447928 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5551338067 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5551338067 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 121446000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 121446000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60146500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60146500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8961010067 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8961010067 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8961010067 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks +system.cpu1.dcache.writebacks::total 330007 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1701,18 +1697,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 911c40f55..027fdffc2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 9a28ceb37..ab2c07a7f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c37c93eb0..9c5baf3db 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:55:16 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:31:55 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2501685689500 because m5_exit instruction encountered +Exiting @ tick 2500827052500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 93f3afbea..2b0eb45e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.501686 # Number of seconds simulated -sim_ticks 2501685689500 # Number of ticks simulated -final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.500827 # Number of seconds simulated +sim_ticks 2500827052500 # Number of ticks simulated +final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57858 # Simulator instruction rate (inst/s) -host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2429415836 # Simulator tick rate (ticks/s) -host_mem_usage 387132 # Number of bytes of host memory used -host_seconds 1029.75 # Real time elapsed on the host -sim_insts 59579009 # Number of instructions simulated -sim_ops 76926775 # Number of ops (including micro ops) simulated +host_inst_rate 90125 # Simulator instruction rate (inst/s) +host_op_rate 116367 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3783000939 # Simulator tick rate (ticks/s) +host_mem_usage 386964 # Number of bytes of host memory used +host_seconds 661.07 # Real time elapsed on the host +sim_insts 59579144 # Number of instructions simulated +sim_ops 76926734 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +23,191 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory -system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory +system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119797 # number of replacements -system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use -system.l2c.total_refs 1834134 # Total number of references to valid blocks. -system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits -system.l2c.Writeback_hits::total 635023 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits -system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits -system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits -system.l2c.overall_hits::cpu.data 484171 # number of overall hits -system.l2c.overall_hits::total 1642008 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64425 # number of replacements +system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use +system.l2c.total_refs 2029411 # Total number of references to valid blocks. +system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits +system.l2c.Writeback_hits::total 675876 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits +system.l2c.overall_hits::cpu.inst 977061 # number of overall hits +system.l2c.overall_hits::cpu.data 497363 # number of overall hits +system.l2c.overall_hits::total 1608896 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses -system.l2c.demand_misses::total 177053 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu.inst 17378 # number of overall misses -system.l2c.overall_misses::cpu.data 159472 # number of overall misses -system.l2c.overall_misses::total 177053 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency +system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses +system.l2c.demand_misses::total 156375 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu.inst 12370 # number of overall misses +system.l2c.overall_misses::cpu.data 143952 # number of overall misses +system.l2c.overall_misses::total 156375 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,112 +216,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102651 # number of writebacks -system.l2c.writebacks::total 102651 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 19094 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 59134 # number of writebacks +system.l2c.writebacks::total 59134 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176952 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 188 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176952 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 7532000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1471125000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -339,27 +336,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52103903 # DTB read hits -system.cpu.dtb.read_misses 93079 # DTB read misses -system.cpu.dtb.write_hits 11946241 # DTB write hits -system.cpu.dtb.write_misses 25022 # DTB write misses +system.cpu.dtb.read_hits 51785537 # DTB read hits +system.cpu.dtb.read_misses 81591 # DTB read misses +system.cpu.dtb.write_hits 11872923 # DTB write hits +system.cpu.dtb.write_misses 18231 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4506 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52196982 # DTB read accesses -system.cpu.dtb.write_accesses 11971263 # DTB write accesses +system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51867128 # DTB read accesses +system.cpu.dtb.write_accesses 11891154 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64050144 # DTB hits -system.cpu.dtb.misses 118101 # DTB misses -system.cpu.dtb.accesses 64168245 # DTB accesses -system.cpu.itb.inst_hits 13717584 # ITB inst hits -system.cpu.itb.inst_misses 12272 # ITB inst misses +system.cpu.dtb.hits 63658460 # DTB hits +system.cpu.dtb.misses 99822 # DTB misses +system.cpu.dtb.accesses 63758282 # DTB accesses +system.cpu.itb.inst_hits 13022422 # ITB inst hits +system.cpu.itb.inst_misses 12153 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -368,542 +365,542 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2627 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13729856 # ITB inst accesses -system.cpu.itb.hits 13717584 # DTB hits -system.cpu.itb.misses 12272 # DTB misses -system.cpu.itb.accesses 13729856 # DTB accesses -system.cpu.numCycles 411352060 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13034575 # ITB inst accesses +system.cpu.itb.hits 13022422 # DTB hits +system.cpu.itb.misses 12153 # DTB misses +system.cpu.itb.accesses 13034575 # DTB accesses +system.cpu.numCycles 408047924 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits +system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued -system.cpu.iq.rate 0.307159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued +system.cpu.iq.rate 0.305615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 261908 # number of nop insts executed -system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed -system.cpu.iew.exec_branches 11601340 # Number of branches executed -system.cpu.iew.exec_stores 12455688 # Number of stores executed -system.cpu.iew.exec_rate 0.299278 # Inst execution rate -system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47546734 # num instructions producing a value -system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value +system.cpu.iew.exec_nop 254480 # number of nop insts executed +system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed +system.cpu.iew.exec_branches 11392260 # Number of branches executed +system.cpu.iew.exec_stores 12383469 # Number of stores executed +system.cpu.iew.exec_rate 0.298278 # Inst execution rate +system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46962413 # num instructions producing a value +system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729390 # Number of instructions committed -system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59729525 # Number of instructions committed +system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513639 # Number of memory references committed -system.cpu.commit.loads 15715354 # Number of loads committed -system.cpu.commit.membars 413068 # Number of memory barriers committed -system.cpu.commit.branches 9904424 # Number of branches committed +system.cpu.commit.refs 27513492 # Number of memory references committed +system.cpu.commit.loads 15715290 # Number of loads committed +system.cpu.commit.membars 413064 # Number of memory barriers committed +system.cpu.commit.branches 9904425 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617835 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. +system.cpu.commit.function_calls 995959 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 245922084 # The number of ROB reads -system.cpu.rob.rob_writes 212744706 # The number of ROB writes -system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579009 # Number of Instructions Simulated -system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated -system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558200782 # number of integer regfile reads -system.cpu.int_regfile_writes 89400906 # number of integer regfile writes -system.cpu.fp_regfile_reads 8900 # number of floating regfile reads -system.cpu.fp_regfile_writes 2982 # number of floating regfile writes -system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads -system.cpu.misc_regfile_writes 912729 # number of misc regfile writes -system.cpu.icache.replacements 1019271 # number of replacements -system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use -system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits -system.cpu.icache.overall_hits::total 12598089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses -system.cpu.icache.overall_misses::total 1111711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked +system.cpu.rob.rob_reads 240802540 # The number of ROB reads +system.cpu.rob.rob_writes 206662154 # The number of ROB writes +system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59579144 # Number of Instructions Simulated +system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated +system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 552215109 # number of integer regfile reads +system.cpu.int_regfile_writes 88113131 # number of integer regfile writes +system.cpu.fp_regfile_reads 8314 # number of floating regfile reads +system.cpu.fp_regfile_writes 2878 # number of floating regfile writes +system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads +system.cpu.misc_regfile_writes 912736 # number of misc regfile writes +system.cpu.icache.replacements 990445 # number of replacements +system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use +system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits +system.cpu.icache.overall_hits::total 11943122 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses +system.cpu.icache.overall_misses::total 1075156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 60091 # number of writebacks -system.cpu.icache.writebacks::total 60091 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67776 # number of writebacks +system.cpu.icache.writebacks::total 67776 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645895 # number of replacements -system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use -system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor +system.cpu.dcache.replacements 644124 # number of replacements +system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use +system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits -system.cpu.dcache.overall_hits::total 21500114 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses -system.cpu.dcache.overall_misses::total 3714520 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits +system.cpu.dcache.overall_hits::total 21203803 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses +system.cpu.dcache.overall_misses::total 3698116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks -system.cpu.dcache.writebacks::total 574932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks +system.cpu.dcache.writebacks::total 608100 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -925,16 +922,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index a9da64c54..fefd6bd25 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 17:03:49 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:25:59 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5157514159500 because m5_exit instruction encountered +Exiting @ tick 5147413032500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index bfc607b4f..674b1d778 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.157514 # Number of seconds simulated -sim_ticks 5157514159500 # Number of ticks simulated -final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.147413 # Number of seconds simulated +sim_ticks 5147413032500 # Number of ticks simulated +final_tick 5147413032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123762 # Simulator instruction rate (inst/s) -host_op_rate 243888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1496586873 # Simulator tick rate (ticks/s) -host_mem_usage 369148 # Number of bytes of host memory used -host_seconds 3446.18 # Real time elapsed on the host -sim_insts 426506235 # Number of instructions simulated -sim_ops 840483958 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory -system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory -system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory -system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 167142 # number of replacements -system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use -system.l2c.total_refs 3843284 # Total number of references to valid blocks. -system.l2c.sampled_refs 202399 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.988651 # Average number of references to valid blocks. +host_inst_rate 192321 # Simulator instruction rate (inst/s) +host_op_rate 378987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2320932369 # Simulator tick rate (ticks/s) +host_mem_usage 367552 # Number of bytes of host memory used +host_seconds 2217.82 # Real time elapsed on the host +sim_insts 426532736 # Number of instructions simulated +sim_ops 840526050 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2503168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1073280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10624512 # Number of bytes read from this memory +system.physmem.bytes_read::total 14204736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1073280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1073280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9409088 # Number of bytes written to this memory +system.physmem.bytes_written::total 9409088 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 221949 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 147017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 147017 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 208509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2064049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2759587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1827926 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1827926 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1827926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2064049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4587513 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 110659 # number of replacements +system.l2c.tagsinuse 64846.009272 # Cycle average of tags in use +system.l2c.total_refs 3990913 # Total number of references to valid blocks. +system.l2c.sampled_refs 174907 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.817343 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.043125 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2426.285000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8680.262415 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.407441 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000122 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.037022 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.132450 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.577037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 109565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1063948 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1334758 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2517075 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1600724 # number of Writeback hits -system.l2c.Writeback_hits::total 1600724 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 336 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 151728 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151728 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 109565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1063948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1486486 # number of demand (read+write) hits -system.l2c.demand_hits::total 2668803 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 109565 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8804 # number of overall hits -system.l2c.overall_hits::cpu.inst 1063948 # number of overall hits -system.l2c.overall_hits::cpu.data 1486486 # number of overall hits -system.l2c.overall_hits::total 2668803 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 105 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 19652 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 45660 # number of ReadReq misses -system.l2c.ReadReq_misses::total 65434 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2521 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2521 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141129 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141129 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 19652 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 186789 # number of demand (read+write) misses -system.l2c.demand_misses::total 206563 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 105 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 17 # number of overall misses -system.l2c.overall_misses::cpu.inst 19652 # number of overall misses -system.l2c.overall_misses::cpu.data 186789 # number of overall misses -system.l2c.overall_misses::total 206563 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5480500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 886000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 1027000000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 2399872000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3433238500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39054500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39054500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7349617000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7349617000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 5480500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 886000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 1027000000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 9749489000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10782855500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 5480500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 886000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 1027000000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 9749489000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10782855500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 109670 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1083600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380418 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2582509 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1600724 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1600724 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2857 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2857 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292857 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292857 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 109670 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8821 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1083600 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1673275 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2875366 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 109670 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency +system.l2c.occ_blocks::writebacks 50048.797239 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 13.777958 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.155980 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3384.461133 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11398.816962 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.763684 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000210 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051643 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.173932 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989472 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 111705 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9478 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055456 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1342066 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2518705 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1610504 # number of Writeback hits +system.l2c.Writeback_hits::total 1610504 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 161822 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 161822 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 111705 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9478 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1055456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1503888 # number of demand (read+write) hits +system.l2c.demand_hits::total 2680527 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 111705 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9478 # number of overall hits +system.l2c.overall_hits::cpu.inst 1055456 # number of overall hits +system.l2c.overall_hits::cpu.data 1503888 # number of overall hits +system.l2c.overall_hits::total 2680527 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16771 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 36056 # number of ReadReq misses +system.l2c.ReadReq_misses::total 52886 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1746 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1746 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 130897 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130897 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16771 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166953 # number of demand (read+write) misses +system.l2c.demand_misses::total 183783 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 53 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses +system.l2c.overall_misses::cpu.inst 16771 # number of overall misses +system.l2c.overall_misses::cpu.data 166953 # number of overall misses +system.l2c.overall_misses::total 183783 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2763500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 876462500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1897742000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2777280000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 38052500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 38052500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6815913500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6815913500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2763500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 876462500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8713655500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9593193500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2763500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 876462500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8713655500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9593193500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 111758 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9484 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1072227 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1378122 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2571591 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1610504 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1610504 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2061 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2061 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292719 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292719 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 111758 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9484 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1072227 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1670841 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2864310 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 111758 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9484 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1072227 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1670841 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2864310 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000474 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.015641 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026163 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020565 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.847162 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847162 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.447176 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.447176 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000474 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.015641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.099922 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.064163 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000474 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.015641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.099922 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.064163 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52141.509434 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52260.598652 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52633.181717 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52514.465076 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 21794.100802 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 21794.100802 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52070.815221 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52070.815221 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52141.509434 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52260.598652 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52192.266686 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52198.481361 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52141.509434 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52260.598652 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52192.266686 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52198.481361 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,8 +189,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 141616 # number of writebacks -system.l2c.writebacks::total 141616 # number of writebacks +system.l2c.writebacks::writebacks 100350 # number of writebacks +system.l2c.writebacks::total 100350 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -200,88 +200,88 @@ system.l2c.demand_mshr_hits::total 2 # nu system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 105 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 17 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 19651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 45659 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 65432 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2521 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2521 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 141129 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 141129 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 17 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 19651 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 186788 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 206561 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 105 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 17 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 19651 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 186788 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 206561 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 4210000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 680000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 786943000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1841762000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2633595000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 101204500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 101204500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646584500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5646584500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 4210000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 680000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 786943000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 7488346500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8280179500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 4210000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 680000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 786943000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 7488346500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8280179500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975402500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59975402500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229367500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1229367500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204770000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61204770000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 16770 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 36055 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 52884 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 1746 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1746 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 130897 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 130897 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16770 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 166952 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 183781 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16770 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 166952 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 183781 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2121000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 671584500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1456546000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2130491500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 70212000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 70212000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5237071500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5237071500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2121000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 671584500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6693617500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7367563000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2121000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 671584500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6693617500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7367563000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59976004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59976004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230258000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1230258000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206262500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61206262500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026162 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020565 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.847162 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847162 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.447176 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.447176 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.064162 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064162 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47578 # number of replacements -system.iocache.tagsinuse 0.166155 # Cycle average of tags in use +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.147452 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47594 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.010385 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.010385 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.warmup_cycle 4996357767000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.147452 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009216 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009216 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses -system.iocache.demand_misses::total 47633 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses -system.iocache.overall_misses::total 47633 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114379932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 114379932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6373400160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6373400160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6487780092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6487780092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6487780092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6487780092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 113343932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 113343932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6309295160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6309295160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6422639092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6422639092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6422639092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6422639092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125380.455752 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 135044.845034 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134861.395347 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134861.395347 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 66555216 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5928.138951 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66880982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66312982 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66312982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3879551568 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3879551568 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3945864550 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3945864550 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,413 +393,413 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 461333918 # number of cpu cycles simulated +system.cpu.numCycles 459902894 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90003796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90003796 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1173183 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84315614 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81694619 # Number of BTB hits +system.cpu.BPredUnit.lookups 90033870 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90033870 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1172024 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84304215 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81702749 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29624871 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446885817 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90003796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81694619 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169759235 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5280537 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141697 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98681847 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37869 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9366803 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 526850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4968 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 302354351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.908315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29359737 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 447000113 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90033870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81702749 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169792580 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290860 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 149776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97806900 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 36600 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 214 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9375679 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523969 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5232 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 301265833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.919513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.390338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133032171 44.00% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1767192 0.58% 44.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72774261 24.07% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988290 0.33% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1636300 0.54% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3666710 1.21% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1141173 0.38% 71.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1450765 0.48% 71.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85897489 28.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131910949 43.79% 43.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1767278 0.59% 44.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72780383 24.16% 68.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 988082 0.33% 68.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1637864 0.54% 69.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3667894 1.22% 70.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1147346 0.38% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1446143 0.48% 71.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85919894 28.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 302354351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195095 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.968682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34659888 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94852238 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163950875 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4820336 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4071014 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876062076 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 946 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4071014 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38916721 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39863124 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10415671 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 164017891 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45069930 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872218550 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9888 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34551329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3873333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31844673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1393807250 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2487751490 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2487750754 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 736 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347499622 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46307621 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 471559 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 478592 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46419855 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18887370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10441908 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1295912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1023550 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865497785 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1720774 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864256485 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25797308 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 52868100 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205226 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 302354351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.858423 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.389396 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 301265833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195767 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.971945 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34474494 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93907388 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163990791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4810664 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4082496 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876264710 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4082496 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38727929 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39278399 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10114969 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 164053704 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45008336 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872424503 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9763 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34576608 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3790570 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31863881 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394114241 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488384373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488383477 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347565425 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46548809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469868 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476809 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46309775 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18907776 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10445518 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1298255 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1025454 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865635268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1719822 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864337626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112774 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25913081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53108345 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 204185 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 301265833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.869020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.387854 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 95961753 31.74% 31.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22210791 7.35% 39.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 18920489 6.26% 45.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7861035 2.60% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80643891 26.67% 74.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3288348 1.09% 75.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72804040 24.08% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 531965 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 94932773 31.51% 31.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22142074 7.35% 38.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 18888671 6.27% 45.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7860945 2.61% 47.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80656411 26.77% 74.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3302785 1.10% 75.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72810465 24.17% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 540656 0.18% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 131053 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 302354351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 301265833 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 168781 8.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1775830 84.20% 92.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 164454 7.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 170381 8.07% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1776523 84.09% 92.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 165648 7.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 295147 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829365416 95.96% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25156928 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9438994 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 297256 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829421724 95.96% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25169917 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9448729 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864256485 # Type of FU issued -system.cpu.iq.rate 1.873386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2109065 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002440 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2033227215 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893026339 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853844323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 314 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 348 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866070258 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1582954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864337626 # Type of FU issued +system.cpu.iq.rate 1.879392 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2112552 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2032304206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893278706 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853918308 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 381 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 98 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866152744 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1572054 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3588586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21998 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11829 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2035325 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3603717 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21501 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11898 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2033136 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821677 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821637 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2389 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4071014 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26002336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1398631 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867218559 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 301512 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18887370 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10441908 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 882377 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 699130 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12813 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11829 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 701390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323826 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862338984 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24725426 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1917500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4082496 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25489851 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1396862 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867355090 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297196 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18907776 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10445518 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 881207 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 698514 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12367 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11898 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 698869 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624345 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1323214 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862415633 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24733940 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1921992 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33920026 # number of memory reference insts executed -system.cpu.iew.exec_branches 86488789 # Number of branches executed -system.cpu.iew.exec_stores 9194600 # Number of stores executed -system.cpu.iew.exec_rate 1.869230 # Inst execution rate -system.cpu.iew.wb_sent 861878608 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853844403 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669889230 # num instructions producing a value -system.cpu.iew.wb_consumers 1919047361 # num instructions consuming a value +system.cpu.iew.exec_refs 33937040 # number of memory reference insts executed +system.cpu.iew.exec_branches 86496224 # Number of branches executed +system.cpu.iew.exec_stores 9203100 # Number of stores executed +system.cpu.iew.exec_rate 1.875212 # Inst execution rate +system.cpu.iew.wb_sent 861954133 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853918406 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669978264 # num instructions producing a value +system.cpu.iew.wb_consumers 1919317191 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.850816 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.349074 # average fanout of values written-back +system.cpu.iew.wb_rate 1.856736 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.349071 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426506235 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840483958 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26630365 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515546 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1177301 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 298298866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.817590 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864095 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426532736 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840526050 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26723975 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515635 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1176103 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 297198870 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.828160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 117621447 39.43% 39.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14371375 4.82% 44.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4300832 1.44% 45.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76665686 25.70% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3908070 1.31% 72.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1784515 0.60% 73.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1116090 0.37% 73.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984342 24.13% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6546509 2.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116541377 39.21% 39.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14339767 4.82% 44.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4295097 1.45% 45.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76671720 25.80% 71.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3910835 1.32% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1786901 0.60% 73.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1117084 0.38% 73.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71988132 24.22% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6547957 2.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 298298866 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426506235 # Number of instructions committed -system.cpu.commit.committedOps 840483958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 297198870 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426532736 # Number of instructions committed +system.cpu.commit.committedOps 840526050 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23705364 # Number of memory references committed -system.cpu.commit.loads 15298781 # Number of loads committed -system.cpu.commit.membars 781557 # Number of memory barriers committed -system.cpu.commit.branches 85502209 # Number of branches committed +system.cpu.commit.refs 23716438 # Number of memory references committed +system.cpu.commit.loads 15304056 # Number of loads committed +system.cpu.commit.membars 781569 # Number of memory barriers committed +system.cpu.commit.branches 85505804 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768310964 # Number of committed integer instructions. +system.cpu.commit.int_insts 768351683 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6546509 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6547957 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1158787398 # The number of ROB reads -system.cpu.rob.rob_writes 1738314967 # The number of ROB writes -system.cpu.timesIdled 2905540 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 158979567 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9853691832 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426506235 # Number of Instructions Simulated -system.cpu.committedOps 840483958 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426506235 # Number of Instructions Simulated -system.cpu.cpi 1.081658 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.081658 # CPI: Total CPI of All Threads -system.cpu.ipc 0.924507 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.924507 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163093750 # number of integer regfile reads -system.cpu.int_regfile_writes 1362601470 # number of integer regfile writes -system.cpu.fp_regfile_reads 80 # number of floating regfile reads -system.cpu.misc_regfile_reads 281025584 # number of misc regfile reads -system.cpu.misc_regfile_writes 403474 # number of misc regfile writes -system.cpu.icache.replacements 1083149 # number of replacements -system.cpu.icache.tagsinuse 510.211811 # Cycle average of tags in use -system.cpu.icache.total_refs 8213603 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1083661 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579495 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56616978000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.211811 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996507 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996507 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8213603 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8213603 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8213603 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8213603 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8213603 # number of overall hits -system.cpu.icache.overall_hits::total 8213603 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1153196 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1153196 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1153196 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1153196 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1153196 # number of overall misses -system.cpu.icache.overall_misses::total 1153196 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17226505491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17226505491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17226505491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17226505491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17226505491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1157821631 # The number of ROB reads +system.cpu.rob.rob_writes 1738597524 # The number of ROB writes +system.cpu.timesIdled 2901104 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 158637061 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9834920608 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426532736 # Number of Instructions Simulated +system.cpu.committedOps 840526050 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426532736 # Number of Instructions Simulated +system.cpu.cpi 1.078236 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.078236 # CPI: Total CPI of All Threads +system.cpu.ipc 0.927441 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.927441 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163268420 # number of integer regfile reads +system.cpu.int_regfile_writes 1362711366 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.misc_regfile_reads 281060274 # number of misc regfile reads +system.cpu.misc_regfile_writes 403581 # number of misc regfile writes +system.cpu.icache.replacements 1071746 # number of replacements +system.cpu.icache.tagsinuse 509.688073 # Cycle average of tags in use +system.cpu.icache.total_refs 8235470 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072258 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.680493 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56594855000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.688073 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8235470 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8235470 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8235470 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8235470 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8235470 # number of overall hits +system.cpu.icache.overall_hits::total 8235470 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1140205 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1140205 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1140205 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1140205 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1140205 # number of overall misses +system.cpu.icache.overall_misses::total 1140205 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16916733991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16916733991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16916733991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16916733991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16916733991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16916733991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9375675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9375675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9375675 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9375675 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9375675 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9375675 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121613 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121613 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121613 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121613 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121613 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121613 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14836.572363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14836.572363 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2216492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9197.062241 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1570 # number of writebacks -system.cpu.icache.writebacks::total 1570 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68394 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68394 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68394 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68394 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68394 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68394 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1084802 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1084802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1084802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1084802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1084802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1572 # number of writebacks +system.cpu.icache.writebacks::total 1572 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67614 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67614 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67614 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67614 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67614 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67614 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072591 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072591 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1072591 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1072591 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1072591 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1072591 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12848213492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12848213492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12848213492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12848213492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12848213492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12848213492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114401 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114401 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114401 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11978.669868 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11978.669868 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10825 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375712 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375712 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27407 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27407 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 12981 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.013322 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25373 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 12993 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.952821 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5123561713000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.013322 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375833 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375833 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25418 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25418 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27410 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27410 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27410 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27410 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11687 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11687 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11687 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11687 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11687 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11687 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 148214000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 148214000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 148214000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 148214000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 148214000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 148214000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39094 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 39094 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25421 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25421 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25421 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25421 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13864 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 13864 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13864 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 13864 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13864 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 13864 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 165480500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 165480500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 165480500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 165480500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 165480500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 165480500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39282 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 39282 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39097 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 39097 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39285 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 39285 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39285 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 39285 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352935 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352935 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352908 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.352908 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352908 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.352908 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11935.985286 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11935.985286 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11935.985286 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11935.985286 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11935.985286 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11935.985286 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1456 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1456 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11687 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11687 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11687 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11687 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11687 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1460 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1460 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13864 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13864 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13864 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 13864 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13864 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 13864 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 123445500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 123445500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 123445500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 123445500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 123445500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 123445500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352935 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352935 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352908 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352908 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8904.032025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 116553 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866227 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866227 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135961 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135961 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135961 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135961 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135961 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135961 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117570 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 117570 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117570 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 117570 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117570 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 117570 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1642151000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1642151000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1642151000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1642151000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1642151000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 120380 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.933344 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 133363 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 120396 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.107703 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5104613509000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.933344 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133363 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 133363 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133363 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 133363 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133363 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 133363 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 121457 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 121457 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 121457 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 121457 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 121457 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 121457 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1679660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1679660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1679660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1679660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1679660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1679660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 254820 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 254820 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 254820 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 254820 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 254820 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 254820 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.476638 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.476638 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.476638 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.476638 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.476638 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.476638 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36817 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36817 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117570 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117570 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117570 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 117570 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117570 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 37082 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 37082 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 121457 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 121457 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 121457 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 121457 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 121457 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 121457 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1312360500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1312360500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1312360500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.476638 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.476638 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.476638 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673290 # number of replacements -system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use -system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1670972 # number of replacements +system.cpu.dcache.tagsinuse 511.998179 # Cycle average of tags in use +system.cpu.dcache.total_refs 19056575 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1671484 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.400992 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10943323 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10943323 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8079241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8079241 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19022564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19022564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19022564 # number of overall hits -system.cpu.dcache.overall_hits::total 19022564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2411423 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2411423 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318003 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318003 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2729426 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2729426 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2729426 # number of overall misses -system.cpu.dcache.overall_misses::total 2729426 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36183001500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36183001500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10564799496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10564799496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46747800996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46747800996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46747800996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46747800996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13354746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.998179 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10967822 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10967822 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085914 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085914 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19053736 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19053736 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19053736 # number of overall hits +system.cpu.dcache.overall_hits::total 19053736 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2407391 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2407391 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724500 # number of overall misses +system.cpu.dcache.overall_misses::total 2724500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35545734500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35545734500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10083377990 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10083377990 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45629112490 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45629112490 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45629112490 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45629112490 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13375213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13375213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8403023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21778236 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21778236 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21778236 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21778236 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.179989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.179989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037737 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037737 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.125102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.125102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.125102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.125102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.251885 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.251885 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31797.829737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31797.829737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16747.701409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16747.701409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19144990 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3356 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5704.705006 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560881 # number of writebacks -system.cpu.dcache.writebacks::total 1560881 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1029888 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1029888 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22394 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1052282 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1052282 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1052282 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1052282 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381535 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381535 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 295609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18178804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18178804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9348322497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9348322497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27527126997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27527126997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27527126997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1570390 # number of writebacks +system.cpu.dcache.writebacks::total 1570390 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1028077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1028077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22422 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22422 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1050499 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1050499 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1050499 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1050499 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1379314 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1379314 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294687 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294687 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1674001 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1674001 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1674001 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1674001 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17753874500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17753874500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8876538990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8876538990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26630413490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26630413490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26630413490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26630413490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208379000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208379000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393915000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393915000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602294000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602294000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103125 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103125 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076866 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076866 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.524903 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.524903 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30121.922548 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30121.922548 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |