diff options
| author | Gabe Black <gabeblack@google.com> | 2017-04-04 03:11:17 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:37:29 +0000 |
| commit | 3a5f469b14b66e56b8764646b132d1c69458fab7 (patch) | |
| tree | 4144d39116ec4af4e4ef6b5e92690ca9b8882c87 /tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini | |
| parent | 16f632f1b8b95ca3e80268680936b6eff498540e (diff) | |
| download | gem5-3a5f469b14b66e56b8764646b132d1c69458fab7.tar.xz | |
stats: Update the solaris boot stats for the new op classes.
The change below introduced some new op classes which have their own stats,
and the counts the instructions used to be under have gone down.
commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318
Author: Fernando Endo <fernando.endo2@gmail.com>
Date: Sat Oct 15 14:58:45 2016 -0500
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb
Reviewed-on: https://gem5-review.googlesource.com/2648
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini')
| -rw-r--r-- | tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index e473f5b49..ed41ed4a0 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -28,7 +28,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic -mem_ranges=1048576:68157439 2147483648:2415919103 +mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0 memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom mmap_using_noreserve=false multi_thread=false @@ -71,7 +71,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 +ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -204,6 +204,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -211,7 +212,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=133446500352:133446508543 +range=133446500352:133446508543:0:0:0:0 port=system.membus.master[5] [system.intrctrl] @@ -297,6 +298,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -304,7 +306,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=133429198848:133429207039 +range=133429198848:133429207039:0:0:0:0 port=system.membus.master[4] [system.partition_desc] @@ -315,6 +317,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -322,7 +325,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=133445976064:133445984255 +range=133445976064:133445984255:0:0:0:0 port=system.membus.master[6] [system.physmem0] @@ -333,6 +336,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -340,7 +344,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=1048576:68157439 +range=1048576:68157439:0:0:0:0 port=system.membus.master[7] [system.physmem1] @@ -351,6 +355,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -358,7 +363,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 port=system.membus.master[8] [system.rom] @@ -369,6 +374,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=60 latency_var=0 null=false @@ -376,7 +382,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=2000000000 p_state_clk_gate_min=2 power_model=Null -range=1099243192320:1099251580927 +range=1099243192320:1099251580927:0:0:0:0 port=system.membus.master[3] [system.t1000] |